PCA9502BS,128

## **PCA9502** 

## **8-bit I/O expander with I[2] C-bus/SPI interface** 

**Rev. 4 — 23 February 2016** 

## **Product data sheet** 

## **1. General description** 

The PCA9502 is an 8-bit I/O expander with I[2] C-bus/SPI host interface. The device comes in a very small HVQFN24 package, which makes it ideally suitable for hand-held, battery operated applications. 

The device also supports software reset, which allows the host to reset the device at any time, independent of the hardware reset signal. 

## **2. Features and benefits** 

## **2.1 General features** 

- Selectable I[2] C-bus or SPI interface 

- 3.3 V or 2.5 V operation 

- Industrial temperature range: 40 C to +85 C 

- Eight programmable I/O pins 

- Software reset 

- Industrial and commercial temperature ranges 

- Available in HVQFN24 package 

- 16 hardware-selectable slave addresses 

## **2.2 I[2] C-bus features** 

- Noise filter on SCL/SDA inputs 

- 400 kbit/s (maximum) 

- Compliant with I[2] C-bus Fast-mode 

- Slave mode only 

## **2.3 SPI features** 

- 15 Mbit/s maximum speed 

- Slave mode only 

- SPI Mode 0 

## **3. Applications** 

- Factory automation and process control 

- Portable and battery operated devices 

- Cellular data devices 

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**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

## **4. Ordering information** 

**Table 1. Ordering information** 

|**Type number**|**Package**|**Package**|**Package**|
|---|---|---|---|
||**Name**|**Description**|**Version**|
|PCA9502BS|HVQFN24|plastic thermal enhanced very thin quad flat package;<br>no leads; 24 terminals; body 440.85 mm|SOT616-3|



## **5. Block diagram** 

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**----- Start of picture text -----**<br>
VDD<br>PCA9502<br>RESET<br>SCL<br>SDA GPIO 8<br>REGISTER GPIO[7:0]<br>A0<br>A1 I [2] C-BUS<br>IRQ<br>1 k Ω  (3.3 V)<br>1.5 k Ω  (2.5 V)<br>VDD<br>VDD<br>I2C/SPI<br>002aab837<br>VSS<br>**----- End of picture text -----**<br>


**Fig 1. Block diagram of PCA9502 I[2] C-bus interface** 

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VDD<br>PCA9502<br>RESET<br>SCLK<br>CS GPIO 8<br>REGISTER GPIO[7:0]<br>SO<br>SI SPI<br>IRQ<br>1 k Ω  (3.3 V)<br>1.5 k Ω  (2.5 V)<br>VDD<br>I2C/SPI<br>002aab838<br>VSS<br>Fig 2. Block diagram of PCA9502 SPI interface<br>**----- End of picture text -----**<br>


© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. 

**Rev. 4 — 23 February 2016** 

**2 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

## **6. Pinning information** 

## **6.1 Pinning** 

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**----- Start of picture text -----**<br>
terminal 1 terminal 1<br>index area index area<br>RESET 1 18 GPIO4 RESET 1 18 GPIO4<br>VDD 2 17 VSS VDD 2 17 VSS<br>VDD 3 16 GPIO3 VDD 3 16 GPIO3<br>PCA9502BS PCA9502BS<br>VDD 4 15 GPIO2 VSS 4 15 GPIO2<br>A0 5 14 GPIO1 CS 5 14 GPIO1<br>A1 6 13 GPIO0 SI 6 13 GPIO0<br>002aab839 002aab840<br>Transparent top view Transparent top view<br>a. I [2] C-bus interface b. SPI interface<br>Fig 3. Pin configuration for HVQFN24<br>DD SS DD DD SS DD<br>V V V GPIO7 GPIO6 GPIO5 V V V GPIO7 GPIO6 GPIO5<br>24 23 22 21 20 19 24 23 22 21 20 19<br>7 8 9 10 11 12 7 8 9 10 11 12<br>n.c. SCL SDA VSS VDD IRQ SO SCLK VSS VSS VDD IRQ<br>**----- End of picture text -----**<br>


## **6.2 Pin description** 

**Table 2. Pin description** 

|**Symbol**|**Pin**|**Type**|**Description**|
|---|---|---|---|
|RESET|1|I|device hardware reset (active LOW)[1]|
|VDD|2, 3, 11,<br>22, 24|-|power supply|
|I2C/SPI|4|I|I2C-bus or SPI interface select. I2C-bus interface is selected if this<br>pin is at logic HIGH. SPI interface is selected if this pin is at logic<br>LOW.|
|CS<br>/A0|5|I|SPI chip select or I2C-bus device address select A0. If SPI<br>configuration is selected by I2C/SPI<br>pin, this pin is the SPI chip<br>select pin (Schmitt trigger, active LOW). If I2C-bus configuration<br>is selected by I2C/SPI<br>pin, this pin along with A1 pin allows user<br>to change the device’s base address.|
|SI/A1|6|I|SPI data input pin or I2C-bus device address select A1. If SPI<br>configuration is selected by I2C/SPI<br>pin, this is the SPI data input<br>pin. If I2C-bus configuration is selected by I2C/SPI<br>pin, this pin<br>along with A0 pin allows user to change the device’s base<br>address. To select the device address, please refer to Table 11<br>.|
|SO|7|O|SPI data output pin. If SPI configuration is selected by I2C/SPI<br>pin, this is a 3-stateable output pin. If I2C-bus configuration is<br>selected by I2C/SPI<br>pin, this pin function is undefined and must<br>be left as n.c. (not connected).|
|SCL/SCLK|8|I|I2C-bus or SPI input clock.|
|SDA|9|I/O|I2C-bus data input/output, open-drain if I2C-bus configuration is<br>selected by I2C/SPI<br>pin. If SPI configuration is selected then this<br>pin is an undefined pin and must be connected to VSS.|



© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4 — 23 February 2016** 

**3 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

**Table 2. Pin description** _…continued_ 

|**Symbol**|**Pin**|**Type**|**Description**|
|---|---|---|---|
|IRQ|12|O|Interrupt (open-drain, active LOW). Interrupt is enabled when<br>interrupt sources are enabled in the I/O Interrupt Enable register<br>(IOIntEna). The interrupt condition is the change of state of the<br>input pins. An external resistor (1 kfor 3.3 V, 1.5 kfor 2.5 V)<br>must be connected between this pin and VDD.|
|GPIO0|13|I/O|programmable I/O pin|
|GPIO1|14|I/O|programmable I/O pin|
|GPIO2|15|I/O|programmable I/O pin|
|GPIO3|16|I/O|programmable I/O pin|
|GPIO4|18|I/O|programmable I/O pin|
|GPIO5|19|I/O|programmable I/O pin|
|GPIO6|20|I/O|programmable I/O pin|
|GPIO7|21|I/O|programmable I/O pin|
|VSS|10, 17,<br>23|-|ground|
|VSS|center<br>pad|-|The center pad on the back side of the HVQFN24 package is<br>metallic and should be connected to ground on the printed-circuit<br>board.|



[1] See Section 7.1 “Hardware reset, Power-On Reset (POR) and software reset” 

## **7. Functional description** 

The device interfaces to a host through either I[2] C-bus or SPI interface (selectable through I2C/SPI pin), and provides the host with eight programmable GPIO pins. 

## **7.1 Hardware reset, Power-On Reset (POR) and software reset** 

These three reset methods are identical and will reset the internal registers as indicated in Table 3. 

Table 3 summarizes the state of registers after reset. 

## **Table 3. Registers after reset** 

|**Register**|**Reset state**|
|---|---|
|I/O direction|all bits cleared|
|I/O interrupt enable|all bits cleared|
|I/O control|all bits cleared|



Table 4 summarizes the state of hardware pins after reset. 

**Table 4. Signals after reset** 

|**Signal**|**Reset state**|
|---|---|
|I/Os|inputs|
|IRQ|HIGH by external pull-up|



© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4 — 23 February 2016** 

**4 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

## **7.2 Interrupts** 

The PCA9502 has interrupt generation capability. The interrupt enable register (IOIntEna) enables interrupts due to I/O pin change of state, and the IRQ signal in response to an interrupt generation. 

## **8. Register descriptions** 

The programming combinations for register selection are shown in Table 5. 

## **Table 5. Register map - read/write properties** 

|**Register name**|**Read mode**|**Write mode**|
|---|---|---|
|IODir|I/O pin direction|I/O pin direction|
|IOState|I/O pin states|n/a|
|IOIntEna|I/O interrupt enable register|I/O interrupt enable register|
|IOControl|I/O pins control|I/O pins control|



**Table 6. PCA9502 internal registers** 

|**Register**<br>**address**|**Register**|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|**R/W**|
|---|---|---|---|---|---|---|---|---|---|---|
|**General Register Set**|||||||||||
|0x0A[1]|IODir|bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0|R/W|
|0x0B[1]|IOState|bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0|R/W|
|0x0~~C~~[1]|IOIntEna|bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0|R/W|
|0x0~~D~~[1]|reserved<br>[2]|reserved<br>[2]|reserved<br>[2]|reserved<br>[2]|reserved<br>[2]|reserved<br>[2]|reserved<br>[2]|reserved<br>[2]|reserved<br>[2]||
|0x0~~E~~[1]|IOControl|reserved<br>[2]|reserved<br>[2]|reserved<br>[2]|reserved<br>[2]|SReset|reserved<br>[2]|reserved<br>[2]|IOLatch|R/W|



[1] Other addresses 0x00 through 0x09, 0x0F are reserved and should not be accessed (read or write). 

- [2] These bits are reserved and should be set to 0. 

## **8.1 Programmable I/O pins Direction register (IODir)** 

This register is used to program the I/O pins direction. Bit 0 to bit 7 control GPIO0 to GPIO7. 

**Table 7. IODir register (address 0x0A) bit description** 

|**Bit**|**Symbol**|**Description**|
|---|---|---|
|7:0|IODir|set GPIO pins 7:0 to input or output<br>0 = input<br>1 = output|



**Remark:** If there is a pending input (GPIO) interrupt and IODir is written, this pending interrupt will be cleared, that is, the interrupt signal will be negated. 

© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4 — 23 February 2016** 

**5 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

## **8.2 Programmable I/O pins State register (IOState)** 

When ‘read’, this register returns the actual state of all I/O pins. When ‘write’, each register bit will be transferred to the corresponding IO pin programmed as output. 

## **Table 8. IOState register (address 0x0B) bit description** 

|**Bit**|**Symbol**|**Description**|
|---|---|---|
|7:0|IOState|Write this register: set the logic level on the output pins<br>0 = set output pin to zero<br>1 = set output pin to one<br>Read this register: return states of all pins|



## **8.3 I/O Interrupt Enable register (IOIntEna)** 

This register enables the interrupt due to a change in the I/O configured as inputs. 

## **Table 9. IOIntEna register (address 0x0C) bit description** 

|**Bit**|**Symbol**|**Description**|
|---|---|---|
|7:0|IOIntEna|input interrupt enable<br>0 = a change in the input pin will not generate an interrupt<br>1 = a change in the input will generate an interrupt|



## **8.4 I/O Control register (IOControl)** 

## **Table 10. IOControl register (address 0x0E) bit description** 

|**Bit**|**Symbol**|**Description**|
|---|---|---|
|7:4|-|reserved for future use|
|3|SReset|software reset<br>A write to this bit will reset the device. Once the device is reset this<br>bit is automatically set to 0.|
|2:1|-|reserved for future use|
|0|IOLatch|enable/disable inputs latching<br>0 = input values are not latched. A change in any input generates an<br>interrupt. A read of the input register clears the interrupt. If the input<br>goes back to its initial logic state before the input register is read,<br>then the interrupt is cleared.<br>1 = input values are latched. A change in the input generates an<br>interrupt and the input logic value is loaded in the bit of the<br>corresponding input state register (IOState). A read of the IOState<br>register clears the interrupt. If the input pin goes back to its initial<br>logic state before the interrupt register is read, then the interrupt is<br>not cleared and the corresponding bit of the IOState register keeps<br>the logic value that initiates the interrupt.<br>Example: If GPIO4 input was as logic 0 and the input goes to logic 1<br>then back to logic 0, the IOState register will capture this change and<br>an interrupt is generated (if enabled). When the read is performed on<br>the IOState register, the interrupt is de-asserted, assuming there were<br>no additional input(s) that changed, and bit 4 of the IOState register<br>will read ‘1’. The next read of the IOState register should now read ‘0’.|



© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4 — 23 February 2016** 

**6 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

## **9. I[2] C-bus operation** 

The two lines of the I[2] C-bus are a serial data line (SDA) and a serial clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy. Each device is recognized by a unique address whether it is a microcomputer, LCD driver, memory or keyboard interface and can operate as either a transmitter or receiver, depending on the function of the device. A device generating a message or data is a transmitter, and a device receiving the message or data is a receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a microcontroller or a memory can both transmit and receive data. 

## **9.1 Data transfers** 

One data bit is transferred during each clock pulse (see Figure 4). The data on the SDA line must remain stable during the HIGH period of the clock pulse in order to be valid. Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP condition (see Figure 5). The bus is considered to be busy after the START condition and free again at a certain time interval after the STOP condition. The START and STOP conditions are always generated by the master. 

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**----- Start of picture text -----**<br>
SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>Fig 4. Bit transfer on the I [2] C-bus<br>**----- End of picture text -----**<br>


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SDA<br>SCL<br>S P<br>START condition STOP condition<br>mba608<br>**----- End of picture text -----**<br>


**Fig 5. START and STOP conditions** 

The number of data bytes transferred between the START and STOP condition from transmitter to receiver is not limited. Each byte, which must be eight bits long, is transferred serially with the most significant bit first, and is followed by an acknowledge bit. (see Figure 6). The clock pulse related to the acknowledge bit is generated by the master. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, while the transmitting device releases this pulse (see Figure 7). 

© NXP Semiconductors N.V. 2016. All rights reserved. **7 of 27** 

PCA9502 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. 

**Rev. 4 — 23 February 2016** 

**PCA9502** 

**NXP Semiconductors** 

## **8-bit I/O expander with I[2] C-bus/SPI interface** 

**==> picture [466 x 122] intentionally omitted <==**

**----- Start of picture text -----**<br>
acknowledgement signal<br>from receiver<br>SDA<br>MSB<br>SCL S 0 1 6 7 8 0 1 2 to 7 8 P<br>ACK ACK<br>START STOP<br>condition byte complete, clock line held LOW condition<br>interrupt within receiver while interrupt is serviced<br>002aab012<br>**----- End of picture text -----**<br>


## **Fig 6. Data transfer on the I[2] C-bus** 

**==> picture [400 x 107] intentionally omitted <==**

**----- Start of picture text -----**<br>
data output transmitter stays off of the bus<br>by transmitter during the acknowledge clock<br>data output acknowledgement signal<br>by receiver from receiver<br>SCL from master S 0 1 6 7 8<br>002aab013<br>START<br>condition<br>**----- End of picture text -----**<br>


**Fig 7. Acknowledge on the I[2] C-bus** 

A slave receiver must generate an acknowledge after the reception of each byte, and a master must generate one after the reception of each byte clocked out of the slave transmitter. 

There is an exception to the ‘acknowledge after every byte’ rule. It occurs when a master is a receiver: it must signal an end of data to the transmitter by **not** signalling an acknowledge on the last byte that has been clocked out of the slave. The acknowledge related clock, generated by the master should still take place, but the SDA line will not be pulled down. In order to indicate that this is an active and intentional lack of acknowledgement, we shall term this special condition as a ‘negative acknowledge’. 

## **9.2 Addressing and transfer formats** 

Each device on the bus has its own unique address. Before any data is transmitted on the bus, the master transmits on the bus the address of the slave to be accessed for this transaction. A well-behaved slave with a matching address, if it exists on the network, should of course acknowledge the master's addressing. The addressing is done by the first byte transmitted by the master after the START condition. 

An address on the network is seven bits long, appearing as the most significant bits of the address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is shown in Figure 8. 

© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 

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**Product data sheet** 

**Rev. 4 — 23 February 2016** 

**8 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

**==> picture [449 x 93] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>SCL S 0 to 6 7 8 0 to 6 7 8 0 to 6 7 8 P<br>START address R/W ACK data ACK data ACK STOP<br>condition condition<br>002aab046<br>**----- End of picture text -----**<br>


**Fig 8. A complete data transfer** 

When an address is sent, each device in the system compares the first seven bits after the START with its own address. If there is a match, the device will consider itself addressed by the master, and will send an acknowledge. The device could also determine if in this transaction it is assigned the role of a slave receiver or slave transmitter, depending on the R/W bit. 

Each node of the I[2] C-bus network has a unique seven-bit address. The address of a microcontroller is of course fully programmable, while peripheral devices usually have fixed and programmable address portions. 

When the master is communicating with one device only, data transfers follow the format of Figure 8, where the R/W bit could indicate either direction. After completing the transfer and issuing a STOP condition, if a master would like to address some other device on the network, it could start another transaction by issuing a new START. 

Another way for a master to communicate with several different devices would be by using a ‘repeated START’. After the last byte of the transaction was transferred, including its acknowledge (or negative acknowledge), the master issues another START, followed by address byte and data, without effecting a STOP. The master may communicate with a number of different devices, combining ‘reads’ and ‘writes’. After the last transfer takes place, the master issues a STOP and releases the bus. Possible data formats are demonstrated in Figure 9. Note that the repeated START allows for both change of a slave and a change of direction, without releasing the bus. We shall see later on that the change of direction feature can come in handy even when dealing with a single device. 

In a single master system, the repeated START mechanism may be more efficient than terminating each transfer with a STOP and starting again. In a multimaster environment, the determination of which format is more efficient could be more complicated, as when a master is using repeated STARTs it occupies the bus for a long time and thus preventing other devices from initiating transfers. 

© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4 — 23 February 2016** 

**9 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

**==> picture [478 x 300] intentionally omitted <==**

**----- Start of picture text -----**<br>
data transferred<br>(n bytes + acknowledge)<br>master write: S SLAVE ADDRESS W A DATA A DATA A P<br>START condition write acknowledge acknowledge acknowledge<br>STOP condition<br>data transferred<br>(n bytes + acknowledge)<br>master read: S SLAVE ADDRESS R A DATA A DATA NA P<br>START condition read acknowledge acknowledge not<br>acknowledge<br>STOP condition<br>data transferred data transferred<br>(n bytes + acknowledge) (n bytes + acknowledge)<br>combined<br>S SLAVE ADDRESS R/W A DATA A Sr SLAVE ADDRESS R/W A DATA A P<br>formats:<br>START condition read or acknowledge acknowledge repeated read or acknowledge acknowledge<br>write START condition write<br>STOP condition<br>direction of transfer<br>may change at this point<br>002aab458<br>Fig 9. I [2] C-bus data formats<br>**----- End of picture text -----**<br>


© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. **Rev. 4 — 23 February 2016** 

**10 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

## **9.3 Addressing** 

Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. Table 11 shows how the PCA9502’s address can be selected by using A1 and A0 pins. For example, if these 2 pins are connected to VDD, then the PCA9502’s address is set to 0x90, and the master communicates with it through this address. 

**Table 11. PCA9502 address map** 

|**A1**|**A0**|**PCA9502 I2C-bus addresses (hex)[1]**|
|---|---|---|
|VDD|VDD|0x90 (1001 000X)|
|VDD|VSS|0x92 (1001 001X)|
|VDD|SCL|0x94 (1001 010X)|
|VDD|SDA|0x96 (1001 011X)|
|VSS|VDD|0x98 (1001 100X)|
|VSS|VSS|0x9A (1001 101X)|
|VSS|SCL|0x9C (1001 110X)|
|VSS|SDA|0x9E (1001 111X)|
|SCL|VDD|0xA0 (1010 000X)|
|SCL|VSS|0xA2 (1010 001X)|
|SCL|SCL|0xA4 (1010 010X)|
|SCL|SDA|0xA6 (1010 011X)|
|SDA|VDD|0xA8 (1010 100X)|
|SDA|VSS|0xAA (1010 101X)|
|SDA|SCL|0xAC (1010 110X)|
|SDA|SDA|0xAE (1010 111X)|



[1] X = logic 0 for write cycle; X = logic 1 for read cycle. 

## **9.4 Use of sub-addresses** 

When a master communicates with the PCA9502 it must send a sub-address in the byte following the slave address byte. This sub-address is the internal address of the word the master wants to access for a single byte transfer, or the beginning of a sequence of locations for a multi-byte transfer. A sub-address is an 8-bit byte. Unlike the device address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus it must be followed by an acknowledge. 

A register write cycle is shown in Figure 10. The START is followed by a slave address byte with the direction bit set to ‘write’, a sub-address byte, a number of data bytes, and a STOP signal. The sub-address indicates which register the master wants to access. and the data bytes which follow will be written one after the other to the sub-address location. 

© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 

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**Product data sheet** 

**Rev. 4 — 23 February 2016** 

**11 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

**==> picture [374 x 38] intentionally omitted <==**

**----- Start of picture text -----**<br>
S SLAVE ADDRESS W A REGISTER ADDRESS [(1)] A nDATA A P<br>002aab047<br>**----- End of picture text -----**<br>


White block: host to PCA9502 Grey block: PCA9502 to host **Fig 10. Master writes to slave** 

The register read cycle (see Figure 11) commences in a similar manner, with the master sending a slave address with the direction bit set to ‘write’ with a following sub-address. Then, in order to reverse the direction of the transfer, the master issues a repeated START followed again by the device address, but this time with the direction bit set to ‘read’. The data bytes starting at the internal sub-address will be clocked out of the device, each followed by a master-generated acknowledge. The last byte of the read cycle will be followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated by a STOP signal. 

**==> picture [458 x 97] intentionally omitted <==**

**----- Start of picture text -----**<br>
S SLAVE ADDRESS W A REGISTER ADDRESS [(1)] A S SLAVE ADDRESS R A<br>nDATA A LAST DATA NA P<br>002aab048<br>**----- End of picture text -----**<br>


White block: host to PCA9502 Grey block: PCA9502 to host 

**Fig 11. Master read from Slave** 

## **Table 12. Register address byte (I[2] C-bus)** 

|**Bit**|**Name**|**Function**|
|---|---|---|
|7|-|not used|
|6:3|A[3:0]|internal register select|
|2:1|-|not used, set to 0|
|0|-|not used|



© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 **Product data sheet** 

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**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

## **10. SPI operation** 

SCLK SI R/W A3 A2 A1 A0 0 0 X D7 D6 D5 D4 D3 D2 D1 D0 _002aab925_ R/W = 0; A[3:0] = register address a. Register write SCLK SI R/W A3 A2 A1 A0 0 0 X SO D7 D6 D5 D4 D3 D2 D1 D0 _002aab926_ 

R/W = 1; A[3:0] = register address 

b. Register read 

**Fig 12. SPI operation** 

**Table 13. Register address byte (SPI)** 

|**Bit**|**Name**|**Function**|
|---|---|---|
|7|R/W|1: read from PCA9502<br>0: write to PCA9502|
|6:3|A[3:0]|internal register select|
|2:1|-|not used, set to 0|
|0|-|not used|



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## **11. Limiting values** 

**Table 14. Limiting values[[][1][]]** 

_In accordance with the Absolute Maximum Rating System (IEC 60134)._ 

|**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**|
|---|---|
|VDD<br>supply voltage|0.3<br>+4.6<br>V|
|VI<br>input voltage|any input<br>[2]<br>0.3<br>+5.5<br>V|
|II<br>input current|any input<br>10<br>+10<br>mA|
|IO<br>output current|any output<br>10<br>+10<br>mA|
|Ptot<br>total power dissipation|-<br>300<br>mW|
|P/out<br>power dissipation per output|-<br>50<br>mW|
|Tamb<br>ambient temperature|40<br>+85<br>C|
|Tstg<br>storage temperature|65<br>+150<br>C|
|VESD<br>electrostatic discharge|HBM<br>[3]<br>-<br>5000<br>V|
||CDM<br>[4]<br>-<br>750<br>V|



- [1] Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 

- [2] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present. 

- [3] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 

- [4] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. 

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## **12. Static characteristics** 

## **Table 15. Static characteristics** 

_VDD = (2.5 V_  _0.2 V) or (3.3 V_  _0.3 V); Tamb =_  _40_  _C to +85_  _C; unless otherwise specified._ 

|**Symbol**|**Parameter**|**Conditions**||**VDD = 2.5 V**|**VDD = 2.5 V**|**VDD = 3.3 V**|**VDD = 3.3 V**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||||**Min**|**Max**|**Min**|**Max**||
|**Supplies**|||||||||
|VDD|supply voltage|||2.3|2.7|3.0|3.6|V|
|IDD|supply current|operating; no load||-|750|-|750|A|
|||static; no load||-|600|-|600|A|
|**Inputs I2C/SPI**|||||||||
|VIH|HIGH-level input voltage|||1.6|5.5[1]|2.0|5.~~5~~[1]|V|
|VIL|LOW-level input voltage|||-|0.6|-|0.8|V|
|IL|leakage current|input; VI= 0 V or 5.5 V[1]||-|1|-|1|A|
|Ci|input capacitance|||-|3|-|3|pF|
|**Output SO**|||||||||
|VOH|HIGH-level output voltage|IOH=400A||1.85|-|-|-|V|
|||IOH=4 mA||-|-|2.4|-|V|
|VOL|LOW-level output voltage|IOL= 1.6 mA||-|0.4|-|-|V|
|||IOL= 4 mA||-|-|-|0.4|V|
|Co|output capacitance|||-|4|-|4|pF|
|**Inputs/outputs GPIO0 to GPIO7**|||||||||
|VIH|HIGH-level input voltage|||1.6|5.5[1]|2.0|5.~~5~~[1]|V|
|VIL|LOW-level input voltage|||-|0.6|-|0.8|V|
|VOH|HIGH-level output voltage|IOH=400A||1.85|-|-|-|V|
|||IOH=4 mA||-|-|2.4|-|V|
|VOL|LOW-level output voltage|IOL= 1.6 mA||-|0.4|-|-|V|
|||IOL= 4 mA||-|-|-|0.4|V|
|IL|leakage current|input; VI= 0 V or 5.5 V[1]||-|1|-|1|A|
|Co|output capacitance|||-|4|-|4|pF|
|**Output IRQ**|||||||||
|VOL|LOW-level output voltage|IOL= 1.6 mA||-|0.4|-|-|V|
|||IOL= 4 mA||-|-|-|0.4|V|
|Co|output capacitance|||-|4|-|4|pF|
|**I2C-bus input/output SDA**|||||||||
|VIH|HIGH-level input voltage|||1.6|5.5[1]|2.0|5.~~5~~[1]|V|
|VIL|LOW-level input voltage|||-|0.6|-|0.8|V|
|VOL|LOW-level output voltage|IOL= 1.6 mA||-|0.4|-|-|V|
|||IOL= 4 mA||-|-|-|0.4|V|
|IL|leakage current|input; VI= 0 V or 5.5 V[1]||-|10|-|10|A|
|Co|output capacitance|||-|7|-|7|pF|



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## **Table 15. Static characteristics** _…continued_ 

_VDD = (2.5 V_  _0.2 V) or (3.3 V_  _0.3 V); Tamb =_  _40_  _C to +85_  _C; unless otherwise specified._ 

|**Symbol**|**Parameter**|**Conditions**||**VDD = 2.5 V**|**VDD = 2.5 V**|**VDD = 3.3 V**|**VDD = 3.3 V**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||||**Min**|**Max**|**Min**|**Max**||
|**I2C-bus inputs SCL, CS**<br>**/A0, SI/A1**|||||||||
|VIH|HIGH-level input voltage|||1.6|5.5[1]|2.0|5.~~5~~[1]|V|
|VIL|LOW-level input voltage|||-|0.6|-|0.8|V|
|IL|leakage current|input; VI= 0 V or 5.5 V[1]||-|10|-|10|A|
|Ci|input capacitance|||-|7|-|7|pF|



[1] 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage tolerance on inputs and outputs when no supply voltage is present. 

## **13. Dynamic characteristics** 

## **Table 16. I[2] C-bus timing specifications** 

_All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = (2.5 V_  _0.2 V) or (3.3 V_  _0.3 V); Tamb =_  _40_  _C to +85_  _C; refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, except SDA output load = 400 pF_ ~~_._~~ _[[][1][]]_ 

|**Symbol**|**Parameter**|**Conditions**||**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||||**Min**|**Max**|**Min**|**Max**||
|fSCL|SCL clock frequency||[2]|0|100|0|400|kHz|
|tBUF|bus free time between a STOP and<br>START condition|||4.7|-|1.3|-|s|
|tHD;STA|hold time (repeated) START condition|||4.0|-|0.6|-|s|
|tSU;STA|set-up time for a repeated START<br>condition|||4.7|-|0.6|-|s|
|tSU;STO|set-up time for STOP condition|||4.7|-|0.6|-|s|
|tHD;DAT|data hold time|||0|-|0|-|ns|
|tVD;ACK|data valid acknowledge time|||-|0.6|-|0.6|s|
|tVD;DAT|data valid time|SCL LOW to data out valid||-|0.6|-|0.6|ns|
|tSU;DAT|data set-up time|||250|-|150|-|ns|
|tLOW|LOW period of the SCL clock|||4.7|-|1.3|-|s|
|tHIGH|HIGH period of the SCL clock|||4.0|-|0.6|-|s|
|tf|fall time of both SDA and SCL signals|||-|300|-|300|ns|
|tr|rise time of both SDA and SCL signals|||-|1000|-|300|ns|
|tSP|pulse width of spikes that must be<br>suppressed by the input filter|||-|50|-|50|ns|
|td1|I2C-bus GPIO output valid time|||0.5|-|0.5|-|s|
|td4|I2C input pin interrupt valid time|||0.2|-|0.2|-|s|
|td5|I2C input pin interrupt clear time|||0.2|-|0.2|-|s|



[1] A detailed description of the I[2] C-bus specification, with applications, is given in brochure _“The I[2] C-bus and how to use it”_ . This brochure may be ordered using the code 9398 393 40011. 

[2] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a minimum of 25 ms. 

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## **8-bit I/O expander with I[2] C-bus/SPI interface** 

**==> picture [353 x 157] intentionally omitted <==**

**----- Start of picture text -----**<br>
START bit 7 bit 0 STOP<br>protocol condition MSB bit 6 LSB acknowledge condition<br>(A6) (A)<br>(S) (A7) (R/W) (P)<br>tSU;STA tLOW tHIGH 1/fSCL<br>SCL<br>tBUF tr tf tSP<br>SDA<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab489<br>**----- End of picture text -----**<br>


Rise and fall times refer to VIL and VIH. 

**Fig 13. I[2] C-bus timing diagram** 

**==> picture [350 x 63] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA SLAVE ADDRESS W A A IOSTATE REG. A DATA A<br>td1<br>GPIOn<br>002aab255<br>**----- End of picture text -----**<br>


**Fig 14. Write to output** 

**==> picture [471 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
ACK from slave ACK from slave ACK from master<br>SDA SLAVE ADDRESS W A A IOSTATE REG. A S SLAVE ADDRESS R A DATA A P<br>IRQ<br>td4 td5<br>GPIOn<br>002aab877<br>Fig 15. GPIO pin interrupt<br>**----- End of picture text -----**<br>


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**Product data sheet** 

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**8-bit I/O expander with I[2] C-bus/SPI interface** 

## **Table 17. SPI-bus timing specifications** 

_All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = (2.5 V_  _0.2 V) or (3.3 V_  _0.3 V); Tamb =_  _40_  _C to +85_  _C; and refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified._ 

|**Symbol**|**Parameter**|**Conditions**||**VDD = 2.5 V**|**VDD = 2.5 V**|**VDD = 3.3 V**|**VDD = 3.3 V**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|||||**Min**|**Max**|**Min**|**Max**||
|td(CS_NH-SOZ)|CS<br>HIGH to SO 3-state delay time|CL= 100 pF||-|100|-|100|ns|
|tsu(CS_N-SCLK)|CS<br>to SCLK setup time|||100|-|100|-|ns|
|th(CS_N-SCLK)|CS<br>to SCLK hold time|||20|-|20|-|ns|
|td(SCLK-SO)|SCLK fall to SO valid delay time|CL= 100 pF||-|25|-|20|ns|
|tsu(SI-SCLK)|SI to SCLK setup time|||10|-|20|-|ns|
|th(SI-SCLK)|SI to SCLK hold time|||10|-|10|-|ns|
|TSCLK|SCLK period|tSCLKL+ tSCLKL||83|-|67|-|ns|
|tSCLKH|SCLK HIGH time|||30|-|25|-|ns|
|tSCLKL|SCLK LOW time|||30|-|25|-|ns|
|tw(CS_NH)|CS<br>HIGH pulse width|||200|-|200|-|ns|
|td9|SPI output data valid time|||200|-|200|-|ns|
|td13|SPI<br>interrupt clear time|||200|-|200|-|ns|



**==> picture [497 x 352] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>th(CS_N-SCLK) tsu(CS_N-SCLK) tSCLKL tSCLKH th(CS_N-SCLK) tw(CS_NH)<br>SCLK<br>th(SI-SCLK)<br>tsu(SI-SCLK)<br>SI<br>td(SCLK-SO) td(CS_N-SOZ)<br>SO<br>002aac429<br>Fig 16. Detailed SPI-bus timing<br>CS<br>SCLK<br>SI R/W A3 A2 A1 A0 0 0 X D7 D6 D5 D4 D3 D2 D1 D0<br>td9<br>GPIOn<br>002aab878<br>R/W = 0; A[3:0] = IOState (0x0B)<br>Fig 17. SPI write IOState to GPIO switch<br>**----- End of picture text -----**<br>


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**==> picture [443 x 142] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS<br>SCLK<br>SI R/W A3 A2 A1 A0 0 0 X<br>SO D7 D6 D5 D4 D3 D2 D1 D0<br>td13<br>IRQ<br>002aab879<br>R/W = 1; A[3:0] = IOState (0x0B)<br>Fig 18. Read IOState to clear GPIO INT<br>**----- End of picture text -----**<br>


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## **14. Package outline** 

**HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm** 

**==> picture [44 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT616-3A<br>**----- End of picture text -----**<br>


**==> picture [481 x 554] intentionally omitted <==**

**----- Start of picture text -----**<br>
D B A<br>terminal 1<br>index area<br>A<br>A1<br>E c<br>detail X<br>e1 C<br>1/2 e<br>e b v C A B y1 C y<br>7 12 w C<br>L<br>13<br>6<br>e<br>Eh e2<br>1/2 e<br>1<br>18<br>terminal 1<br>index area<br>24 19<br>Dh X<br>0 2.5 5 mm<br>Dimensions (mm are the original dimensions) scale<br>Unit [(1)] A [(1)] A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>max 1 0.05 0.30 4.1 2.75 4.1 2.75 0.5<br>mm nom 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1<br>min 0.00 0.18 3.9 2.45 3.9 2.45 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. sot616-3a_po<br>Outline References European Issue date<br>version IEC JEDEC JEITA projection<br>16-02-16<br>SOT616-3A MO-220<br>16-02-17<br>**----- End of picture text -----**<br>


**Fig 19. Package outline SOT616-3 (HVQFN24)** 

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## **15. Handling information** 

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. 

## **16. Soldering of SMD packages** 

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . 

## **16.1 Introduction to soldering** 

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 

## **16.2 Wave and reflow soldering** 

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: 

- Through-hole components 

- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board 

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. 

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. 

Key characteristics in both wave and reflow soldering are: 

- Board specifications, including the board finish, solder masks and vias 

- Package footprints, including solder thieves and orientation 

- The moisture sensitivity level of the packages 

- Package placement 

- Inspection and repair 

- Lead-free soldering versus SnPb soldering 

## **16.3 Wave soldering** 

Key characteristics in wave soldering are: 

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- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave 

- Solder bath specifications, including temperature and impurities 

## **16.4 Reflow soldering** 

Key characteristics in reflow soldering are: 

- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 20) than a SnPb process, thus reducing the process window 

- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board 

- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19 

## **Table 18. SnPb eutectic process (from J-STD-020D)** 

|**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|
|---|---|---|
||**Volume (mm3)**||
||**< 350**|**350**|
|< 2.5|235|220|
|2.5|220|220|



## **Table 19. Lead-free process (from J-STD-020D)** 

|**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|
|---|---|---|---|
||**Volume (mm3)**|||
||**< 350**|**350 to 2000**|**> 2000**|
|< 1.6|260|260|260|
|1.6 to 2.5|260|250|245|
|> 2.5|250|245|245|



Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. 

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 20. 

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**==> picture [352 x 223] intentionally omitted <==**

**----- Start of picture text -----**<br>
maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 20. Temperature profiles for large and small components<br>**----- End of picture text -----**<br>


For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . 

## **17. Abbreviations** 

## **Table 20. Abbreviations** 

|**Acronym**|**Description**|
|---|---|
|GPIO|General Purpose Input/Output|
|I2C-bus|Inter Integrated Circuit bus|
|I/O|Input/Output|
|LCD|Liquid Crystal Display|
|POR|Power-On Reset|
|SPI|Serial Peripheral Interface|



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## **18. Revision history** 

**Table 21. Revision history** 

|**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**|
|---|---|---|---|---|
|PCA9502 v.4|20160223|Product data sheet|-|PCA9502 v.3|
|Modifications:|**•** Table 14“<br>Limiting values<br>[1]<br>”<br>,added ESD information||||
|PCA9502 v.3|20061013|Product data sheet|-|PCA9502 v.2|
|Modifications:|**•** The format of this data sheet has been redesigned to comply with the new identity guidelines of<br>NXP Semiconductors.<br>**•** Legal texts have been adapted to the new company name where appropriate.<br>**•** Table 15“<br>Static characteristics<br>”<br>,sub-section “Supplies”:<br>**–**<br>IDD, supply current, operating; no load: changed maximum limit from 6.0 mA to 750A for both<br>2.5 V and 3.3 V supply voltage ranges<br>**–**<br>IDD, supply current: added “static; no load” Conditions (max 600A)||||
|PCA9502 v.2|20060803|Product data sheet|-|PCA9502 v.1|
|PCA9502 v.1|20060707|Product data sheet|-|-|



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## **19. Legal information** 

## **19.1 Data sheet status** 

|**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**|
|---|---|---|
|Objective [short] data sheet|Development|This document contains data from the objective specification for product development.|
|Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.|
|Product [short] data sheet|Production|This document contains the product specification.|



[1] Please consult the most recently issued document before initiating or completing a design. 

[2] The term ‘short data sheet’ is explained in section “Definitions”. 

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 

## **19.2 Definitions** 

**Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 

**Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 

**Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. 

**Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. 

## **19.3 Disclaimers** 

**Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 

**Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 

**Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. 

**Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 

**No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4 — 23 February 2016** 

**25 of 27** 

**PCA9502** 

**NXP Semiconductors** 

## **8-bit I/O expander with I[2] C-bus/SPI interface** 

**Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 

**Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s 

own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 

**Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 

## **19.4 Trademarks** 

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 

**I[2] C-bus  —** logo is a trademark of NXP B.V. 

## **20. Contact information** 

For more information, please visit: **http://www.nxp.com** 

For sales office addresses, please send an email to: **salesaddresses@nxp.com** 

© NXP Semiconductors N.V. 2016. All rights reserved. 

PCA9502 

All information provided in this document is subject to legal disclaimers. 

**Product data sheet** 

**Rev. 4 — 23 February 2016** 

**26 of 27** 

**PCA9502** 

**NXP Semiconductors** 

**8-bit I/O expander with I[2] C-bus/SPI interface** 

## **21. Contents** 

|**1**|**General description . . . . . . . . . . . . . . . . . . . . . .  1**|**20**|
|---|---|---|
|**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . .  1**|**21**|
|2.1|General features. . . . . . . . . . . . . . . . . . . . . . . .  1||
|2.2|I2C-bus features . . . . . . . . . . . . . . . . . . . . . . . .  1||
|2.3|SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . .  1||
|**3**|**Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1**||
|**4**|**Ordering information. . . . . . . . . . . . . . . . . . . . .  2**||
|**5**|**Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . .  2**||
|**6**|**Pinning information. . . . . . . . . . . . . . . . . . . . . .  3**||
|6.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3||
|6.2|Pin description  . . . . . . . . . . . . . . . . . . . . . . . . .  3||
|**7**|**Functional description  . . . . . . . . . . . . . . . . . . .  4**||
|7.1|Hardware reset, Power-On Reset (POR) and||
||software reset . . . . . . . . . . . . . . . . . . . . . . . . . .  4||
|7.2|Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5||
|**8**|**Register descriptions  . . . . . . . . . . . . . . . . . . . .  5**||
|8.1|Programmable I/O pins Direction register||
||(IODir). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5||
|8.2|Programmable I/O pins State register (IOState)  6||
|8.3|I/O Interrupt Enable register (IOIntEna) . . . . . .  6||
|8.4|I/O Control register (IOControl). . . . . . . . . . . . .  6||
|**9**|**I2C-bus operation. . . . . . . . . . . . . . . . . . . . . . . .  7**||
|9.1|Data transfers . . . . . . . . . . . . . . . . . . . . . . . . . .  7||
|9.2|Addressing and transfer formats. . . . . . . . . . . .  8||
|9.3|Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . .  11||
|9.4|Use of sub-addresses. . . . . . . . . . . . . . . . . . .  11||
|**10**|**SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . .  13**||
|**11**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .  14**||
|**12**|**Static characteristics. . . . . . . . . . . . . . . . . . . .  15**||
|**13**|**Dynamic characteristics . . . . . . . . . . . . . . . . .  16**||
|**14**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . .  20**||
|**15**|**Handling information. . . . . . . . . . . . . . . . . . . .  21**||
|**16**|**Soldering of SMD packages . . . . . . . . . . . . . .  21**||
|16.1|Introduction to soldering . . . . . . . . . . . . . . . . .  21||
|16.2|Wave and reflow soldering . . . . . . . . . . . . . . .  21||
|16.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .  21||
|16.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . .  22||
|**17**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . .  23**||
|**18**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . .  24**||
|**19**|**Legal information. . . . . . . . . . . . . . . . . . . . . . .  25**||
|19.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . .  25||
|19.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . .  25||
|19.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .  25||
|19.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .  26||



**Contact information  . . . . . . . . . . . . . . . . . . . .  26 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27** 

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 

**© NXP Semiconductors N.V. 2016.** 

**All rights reserved.** 

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 23 February 2016 Document identifier: PCA9502**