PCA9501PW,118

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins** 

**==> picture [35 x 38] intentionally omitted <==**

## **PCA9501** 

**Rev. 04 — 10 February 2009** 

**Product data sheet** 

## **1. General description** 

The PCA9501 is an 8-bit I/O expander with an on-board 2-kbit EEPROM. 

The I/O expandable eight quasi-bidirectional data pins can be independently assigned as inputs or outputs to monitor board level status or activate indicator devices such as LEDs. The system master writes to the I/O configuration bits in the same way as for the PCF8574. The data for each input or output is kept in the corresponding input or output register. The system master can read all registers. 

The EEPROM can be used to store error codes or board manufacturing data for read-back by application software for diagnostic purposes and are included in the I/O expander package. 

The PCA9501 active LOW open-drain interrupt output is activated when any input state differs from its corresponding input port register state. It is used to indicate to the system master that an input state has changed and the device needs to be interrogated. 

The PCA9501 has six address pins with internal pull-up resistors allowing up to 64 devices to share the common two-wire I[2] C-bus software protocol serial data bus. The fixed GPIO address starts with ‘0’ and the fixed EEPROM I[2] C-bus address starts with ‘1’, so the PCA9501 appears as two separate devices to the bus master. 

The PCA9501 supports hot insertion to facilitate usage in removable cards on backplane systems. 

## **2. Features** 

I 8 general purpose input/output expander/collector 

- I Replacement for PCF8574 with integrated 2-kbit EEPROM 

- I Internal 256 × 8 EEPROM 

- I Self timed write cycle (5 ms typical) 

- I 16 byte page write operation 

- I I[2] C-bus and SMBus interface logic 

- I Internal power-on reset 

- I 

- I Active LOW interrupt output 

- I 6 address pins allowing up to 64 devices on the I[2] C-bus/SMBus 

- I No glitch on power-up 

- I Supports hot insertion 

- I 

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**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

I Low standby current 

- I Operating power supply voltage range of 2.5 V to 3.6 V 

- I 5 V tolerant inputs/outputs 

- I 0 Hz to 400 kHz clock frequency 

- I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 

- I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA 

- I Packages offered: SO20, TSSOP20, HVQFN20 

## **3. Applications** 

- I 

- I Board health monitoring and status reporting 

- I Multi-card systems in telecom, networking, and base station infrastructure equipment 

- I Field recall and troubleshooting functions for installed boards 

- I General-purpose integrated I/O with memory 

- I Replacement for PCF8574 with integrated 2-kbit EEPROM 

- I Bus master sees GPIO and EEPROM as two separate devices 

- I Six hardware address pins allow up to 64 PCA9501s to be located in the same I[2] C-bus/SMBus 

## **4. Ordering information** 

## **Table 1. Ordering information** 

|**Type number**|**Package**|**Package**|**Package**|
|---|---|---|---|
||**Name**|**Description**|**Version**|
|PCA9501D|SO20<br>plastic small outline package; 20 leads;<br>body width 7.5 mm<br>SOT163-1|||
|PCA9501PW|TSSOP20<br>plastic thin shrink small outline package; 20 leads;<br>body width 4.4 mm<br>SOT360-1|||
|PCA9501BS|HVQFN20<br>plastic thermal enhanced very thin quad fat package;<br>no leads; 20 terminals; body 5×5×0.85 mm<br>SOT662-1|||



## **4.1 Ordering options** 

## **Table 2. Ordering options** 

|**Type number**|**Topside mark**|**Temperature range**|
|---|---|---|
|PCA9501D|PCA9501D|−40°C to +85°C|
|PCA9501PW|PCA9501|−40°C to +85°C|
|PCA9501BS|9501|−40°C to +85°C|



© NXP B.V. 2009. All rights reserved. 

PCA9501_4 

**Product data sheet** 

**Rev. 04 — 10 February 2009** 

**2 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **5. Block diagram** 

**==> picture [360 x 287] intentionally omitted <==**

**----- Start of picture text -----**<br>
PCA9501<br>300 kΩ<br>A0 IO0<br>IO1<br>A1 8-bit<br>IO2<br>A2 INPUT/ IO3<br>OUTPUT<br>A3 write pulse PORTS IO4<br>A4 IO5<br>read pulse IO6<br>A5<br>IO7<br>SCL INPUT I [2] C-BUS/SMBus VDD<br>SDA FILTER CONTROL<br>LP<br>INT<br>FILTER<br>VDD<br>POWER-ON<br>VSS RESET<br>EEPROM<br>WC<br>256 × 8<br>002aac000<br>**----- End of picture text -----**<br>


**Fig 1. Block diagram of PCA9501** 

## **6. Pinning information** 

## **6.1 Pinning** 

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**----- Start of picture text -----**<br>
A0 1 20 VDD A0 1 20 VDD<br>A1 2 19 SDA A1 2 19 SDA<br>A2 3 18 SCL A2 3 18 SCL<br>IO0 4 17 WC IO0 4 17 WC<br>IO1 5 16 IO7 IO1 5 16 IO7<br>PCA9501D PCA9501PW<br>IO2 6 15 IO6 IO2 6 15 IO6<br>IO3 7 14 IO5 IO3 7 14 IO5<br>INT 8 13 IO4 INT 8 13 IO4<br>A5 9 12 A3 A5 9 12 A3<br>VSS 10 11 A4 VSS 10 11 A4<br>002aab997 002aab998<br>Fig 2. Pin configuration for SO20 Fig 3. Pin configuration for TSSOP20<br>**----- End of picture text -----**<br>


© NXP B.V. 2009. All rights reserved. 

PCA9501_4 **Product data sheet** 

**Rev. 04 — 10 February 2009** 

**3 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**==> picture [180 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
terminal 1<br>index area<br>A2 1 15 WC<br>IO0 2 14 IO7<br>IO1 3 PCA9501BS 13 IO6<br>IO2 4 12 IO5<br>IO3 5 11 IO4<br>002aab999<br>Transparent top view<br>A1 A0 VDD SDA SCL<br>20 19 18 17 16<br>6 7 8 9 10<br>INT A5 VSS A4 A3<br>**----- End of picture text -----**<br>


**Fig 4.** 

## **6.2 Pin description** 

**Table 3. Pin description** 

|**Symbol**|**Pin**|**Pin**|**Description**|
|---|---|---|---|
||**SO20, TSSOP20**|**HVQFN20**||
|A0|1<br>19<br>address lines (internal pull-up)<br>2<br>20<br>3<br>1<br>12<br>10<br>11<br>9<br>9<br>7|||
|A1||||
|A2||||
|A3||||
|A4||||
|A5||||
|IO0|4<br>2<br>quasi-bidirectional I/O pins<br>5<br>3<br>6<br>4<br>7<br>5<br>13<br>11<br>14<br>12<br>15<br>13<br>16<br>14|||
|IO1||||
|IO2||||
|IO3||||
|IO4||||
|IO5||||
|IO6||||
|IO7||||
|INT|8<br>6<br>active LOW interrupt output (open-drain)|||
|VSS|10<br>~~8~~<br>[1]<br>supply ground|||
|WC|17<br>15<br>active LOW write control pin|||
|SCL|18<br>16<br>I2C-bus serial clock|||
|SDA|19<br>17<br>I2C-bus serial data|||
|VDD|20<br>18<br>supply voltage|||



[1] HVQFN20 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. 

© NXP B.V. 2009. All rights reserved. 

PCA9501_4 **Product data sheet** 

**Rev. 04 — 10 February 2009** 

**4 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **7. Functional description** 

Refer also to Figure 1 “Block diagram of PCA9501”. 

**==> picture [346 x 178] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>write pulse<br>100 µA<br>data from shift register D Q<br>FF<br>IO0 to IO7<br>CI<br>S<br>power-on reset VSS<br>D Q<br>FF<br>read pulse CI<br>S<br>to interrupt logic<br>data to shift register<br>002aac001<br>**----- End of picture text -----**<br>


**Fig 5.** 

## **7.1 Device addressing** 

Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9501 is shown in Figure 6. Internal pull-up resistors are incorporated on the hardware-selectable address pins. 

a read is selected, while a logic 0 selects a write operation. 

**==> picture [359 x 94] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address slave address<br>0 A5 A4 A3 A2 A1 A0 R/W 1 A5 A4 A3 A2 A1 A0 R/W<br>fixed hardware programmable fixed hardware programmable<br>002aac002 002aac003<br>a. I/O expander b. Memory<br>Fig 6. PCA9501 slave addresses<br>**----- End of picture text -----**<br>


**Remark:** Reserved I[2] C-bus addresses must be used with caution since they can interfere with: 

- Reserved for future use I[2] C-bus addresses (0000 011, 1111 1xx) 

- Slave devices that use the 10-bit addressing scheme (1111 0xx) 

- Slave devices that are designed to respond to the General Call address (0000 000) 

- Hs-mode master code (0000 1xx) 

© NXP B.V. 2009. All rights reserved. 

PCA9501_4 

**Product data sheet** 

**Rev. 04 — 10 February 2009** 

**5 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **7.2 Control register** 

The PCA9501 contains a single 8-bit register called the Control register, which can be written and read via the I[2] C-bus. This register is sent after a successful acknowledgment of the slave address. 

It contains the I/O operation information. 

## **7.3 I/O operations** 

(Refer also to Figure 5.) 

Each of the PCA9501's eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O Write mode (see Figure 7). Input I/O data is transferred from the port to the microcontroller by the Read mode (see Figure 8). 

**==> picture [422 x 133] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>slave address (I/O expander) data to port data to port<br>SDA S 0 A5 A4 A3 A2 A1 A0 0 A DATA 1 A DATA 2 A<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>write to port<br>tv(Q) tv(Q)<br>data out from port DATA 1 VALID DATA 2 VALID<br>002aad290<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Fig 7. I/O Write mode (output)<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>no acknowledge<br>from master<br>slave address (I/O expander) data from port data from port<br>SDA S 0 A5 A4 A3 A2 A1 A0 1 A DATA 1 A DATA 4 1 P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from master condition<br>read from<br>port<br>DATA 2<br>data into<br>DATA 1 DATA 3 DATA 4<br>port<br>th(D) tsu(D)<br>INT<br>tv(INT) trst(INT)<br>002aad291<br>Fig 8. I/O Read mode (input)<br>**----- End of picture text -----**<br>


© NXP B.V. 2009. All rights reserved. 

PCA9501_4 

**Product data sheet** 

**Rev. 04 — 10 February 2009** 

**6 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **7.3.1 Quasi-bidirectional I/Os** 

A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. See Figure 9. 

**==> picture [408 x 151] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address (I/O expander) data to port data to port<br>SDA S 0 A5 A4 A3 A2 A1 A0 0 A 1 A 0 A P<br>START condition R/W acknowledge IO3 acknowledge IO3 acknowledge<br>from slave from slave from slave<br>IO3 output voltage<br>IO3 pull-up output current<br>IOHt IOH<br>002aad292<br>**----- End of picture text -----**<br>


**Fig 9. Transient pull-up current (IOHt) while IO3 changes from LOW to HIGH and back to LOW** 

## **7.3.2 Interrupt** 

The PCA9501 provides an open-drain output (INT) which can be fed to a corresponding input of the microcontroller. This gives these chips a type of master function which can initiate an action elsewhere in the system. See Figure 10. 

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tv(INT) the signal INT is valid. See Figure 11. 

Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from or written to the port which has generated the interrupt. 

Resetting occurs as follows: 

- In the Read mode at the acknowledge bit after the rising edge of the SCL signal 

- In the Write mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL signal 

- Returning of the port data to its original setting 

- Interrupts which occur during the acknowledge clock pulse may be lost (or very short) due to the resetting of the interrupt during this pulse. 

Each change of the I/Os after resetting will be detected and, after the next rising clock edge, will be transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit. 

© NXP B.V. 2009. All rights reserved. 

PCA9501_4 **Product data sheet** 

**Rev. 04 — 10 February 2009** 

**7 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**==> picture [397 x 303] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD device 1 device 2 device 16<br>PCA9501 PCA9501 PCA9501<br>MICROCONTROLLER<br>INT INT INT<br>INT<br>002aad293<br>Fig 10. Application of multiple PCA9501s with interrupt<br>SCL 1 2 3 4 5 6 7 8 9<br>slave address (I/O expander) data from port<br>SDA S 0 A5 A4 A3 A2 A1 A0 1 A 1 1 P<br>START condition R/W IO5 STOP<br>condition<br>acknowledge<br>from slave<br>data into IO5<br>tv(INT) trst(INT)<br>INT<br>002aad294<br>Fig 11. Interrupt generated by a change of input to IO5<br>**----- End of picture text -----**<br>


## **7.4 Memory operations** 

## **7.4.1 Write operations** 

location to be written. The address field is eight bits long providing access to any one of the 256 words of memory. There are two types of write operations, ‘byte write’ and ‘page write’. 

Write operation is possible when the Write Control pin (WC) is put at a LOW logic level (0). When this control signal is set at 1, write operation is not possible and data in the memory is protected. 

‘Byte write’ and ‘page write’ explained below assume that WC is set to 0. 

## **7.4.1.1 Byte write** 

To perform a byte write, the START condition is followed by the memory slave address and the R/W bit set to 0. The PCA9501 will respond with an acknowledge and then consider the next eight bits sent as the word address and the eight bits after the word address as the data. The PCA9501 will issue an acknowledge after the receipt of both the word address and the data. To terminate the data transfer the master issues the STOP condition, initiating the internal write cycle to the non-volatile memory. Only write and read operations to the quasi-bidirectional I/Os are allowed during the internal write cycle. 

© NXP B.V. 2009. All rights reserved. 

PCA9501_4 

**Product data sheet** 

**Rev. 04 — 10 February 2009** 

**8 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**==> picture [392 x 77] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address (memory) word address data<br>SDA S 1 A5 A4 A3 A2 A1 A0 0 A A A P<br>START condition R/W acknowledge acknowledge acknowledge STOP condition.<br>from slave from slave from slave Write to the memory<br>is performed.<br>002aad296<br>**----- End of picture text -----**<br>


**Fig 12. Byte write** 

## **7.4.1.2 Page write** 

data the STOP condition is not received, the PCA9501 considers subsequent words as data. After each data word the PCA9501 responds with an acknowledge and the four least significant bits of the memory address field are incremented. Should the master not send a STOP condition after 16 data words, the address counter will return to its initial value and overwrite the data previously written. After the receipt of the STOP condition the inputs will behave as with the byte write during the internal write cycle. 

**==> picture [463 x 114] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address (memory) word address data to memory data to memory<br>SDA S 1 A5 A4 A3 A2 A1 A0 0 A A DATA n A DATA n + 3 A P<br>START condition R/W acknowledge acknowledge acknowledge acknowledge<br>from slave from slave from slave from slave<br>STOP condition.<br>Write to the memory is performed.<br>002aad297<br>Fig 13. Page write<br>**----- End of picture text -----**<br>


## **7.4.2 Read operations** 

PCA9501 read operations are initiated in an identical manner to write operations with the exception that the memory slave address R/W bit is set to ‘1’. There are three types of read operations: current address read, random read and sequential read. 

## **7.4.2.1 Current address read** 

The PCA9501 contains an internal address counter that increments after each read or write access and as a result, if the last word accessed was at address ‘n’ then the address counter contains the address ‘n + 1’. 

When the PCA9501 receives its memory slave address with the R/W bit set to one it issues an acknowledge and uses the next eight clocks to transmit the data contained at the address stored in the address counter. The master ceases the transmission by issuing the STOP condition after the eighth bit. There is no ninth clock cycle for the acknowledge. 

© NXP B.V. 2009. All rights reserved. 

PCA9501_4 

**Product data sheet** 

**Rev. 04 — 10 February 2009** 

**9 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**==> picture [344 x 83] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address (memory) data from memory<br>SDA S 1 A5 A4 A3 A2 A1 A0 1 A P<br>START condition R/W acknowledge STOP condition<br>from slave 002aad298<br>Fig 14. Current address read<br>**----- End of picture text -----**<br>


## **7.4.2.2 Random read** 

the master. This is done by performing a dummy write to set the address counter to the location to be read. The master must perform a byte write to the address location to be read, but instead of transmitting the data after receiving the acknowledge from the PCA9501, the master re-issues the START condition and memory slave address with the R/W bit set to one. The PCA9501 will then transmit an acknowledge and use the next eight clock cycles to transmit the data contained in the addressed location. The master ceases the transmission by issuing the STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge. 

**==> picture [470 x 94] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address (memory) word address slave address (memory) data from memory<br>SDA S 1 A5 A4 A3 A2 A1 A0 0 A A S 1 A5 A4 A3 A2 A1 A0 1 A P<br>START condition R/W acknowledge acknowledge START condition R/W STOP<br>from slave from slave condition<br>acknowledge<br>from slave 002aad299<br>Fig 15. Random read<br>**----- End of picture text -----**<br>


## **7.4.2.3 Sequential read** 

The PCA9501 sequential read is an extension of either the current address read or random read. If the master does not issue a STOP condition after it has received the eighth data bit, but instead issues an acknowledge, the PCA9501 will increment the address counter and use the next eight cycles to transmit the data from that location. The master can continue this process to read the contents of the entire memory. Upon reaching address 255 the counter will return to address 0 and continue transmitting data until a STOP condition is received. The master ceases the transmission by issuing the STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge. 

**==> picture [455 x 92] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address (memory) data from memory data from memory data from memory<br>SDA S 1 A5 A4 A3 A2 A1 A0 1 A DATA n A DATA n + 1 A DATA n + X P<br>START condition R/W acknowledge acknowledge acknowledge STOP<br>from slave from master from master condition<br>002aad300<br>Fig 16. Sequential read<br>**----- End of picture text -----**<br>


© NXP B.V. 2009. All rights reserved. 

PCA9501_4 **Product data sheet** 

**Rev. 04 — 10 February 2009** 

**10 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **8. Characteristics of the I[2] C-bus** 

The I[2] C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 

## **8.1 Bit transfer** 

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 17). 

**==> picture [242 x 88] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>**----- End of picture text -----**<br>


**Fig 17. Bit transfer** 

## **8.1.1 START and STOP conditions** 

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 18). 

**==> picture [320 x 83] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>SCL<br>S P<br>START condition STOP condition<br>mba608<br>**----- End of picture text -----**<br>


**Fig 18.** 

## **8.2** 

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 19). 

© NXP B.V. 2009. All rights reserved. 

PCA9501_4 **Product data sheet** 

**Rev. 04 — 10 February 2009** 

**11 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**==> picture [433 x 109] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>SCL<br>MASTER SLAVE SLAVE MASTER MASTER I [2] C-BUS<br>TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/ MULTIPLEXER<br>RECEIVER RECEIVER RECEIVER<br>SLAVE<br>002aaa966<br>**----- End of picture text -----**<br>


**Fig 19.** 

## **8.3 Acknowledge** 

The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. 

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. 

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 

**==> picture [340 x 140] intentionally omitted <==**

**----- Start of picture text -----**<br>
data output<br>by transmitter<br>not acknowledge<br>data output<br>by receiver<br>acknowledge<br>SCL from master<br>1 2 8 9<br>S<br>clock pulse for<br>START acknowledgement<br>condition 002aaa987<br>Fig 20. Acknowledgement on the I [2] C-bus<br>**----- End of picture text -----**<br>


© NXP B.V. 2009. All rights reserved. 

PCA9501_4 **Product data sheet** 

**Rev. 04 — 10 February 2009** 

**12 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **9. Application design-in information** 

A central processor/controller typically located on the system main board can use the 400 kHz I[2] C-bus/SMBus to poll the PCA9501 devices located on the system cards for status or version control type of information. The PCA9501 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data, and so on. Alternately, these devices can be used as convenient interface for board configuration, thereby utilizing the I[2] C-bus/SMBus as an intra-system communication bus 

**==> picture [409 x 213] intentionally omitted <==**

**----- Start of picture text -----**<br>
up to<br>64 cards<br>I [2] C-bus ASIC<br>CPU I [2] C-bus<br>OR I [2] C-bus BACKPLANE configuration control<br>µC I [2] C-bus<br>PCA9501<br>I [2] C-bus<br>CONTROL<br>I [2] C-bus<br>INPUTS<br>GPIO monitoring ALARM<br>and LEDs<br>EEPROM control<br>card ID, subroutines, configuration data, or revision history<br>002aac026<br>**----- End of picture text -----**<br>


**Fig 21.** 

© NXP B.V. 2009. All rights reserved. 

PCA9501_4 

**Product data sheet** 

**Rev. 04 — 10 February 2009** 

**13 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**==> picture [428 x 241] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>10 kΩ 10 kΩ 10 kΩ 10 k(optional)Ω 2 kΩ (e.g., temp sensor)SUB-SYSTEM 1<br>VDD VDD<br>INT<br>MASTER PCA9501<br>CONTROLLER<br>SCL SCL IO0<br>SUB-SYSTEM 2<br>SDA SDA IO1 (e.g., counter)<br>INT INT<br>IO2 RESET<br>A5 IO3<br>A<br>VSS A4 IO4 enable controlled<br>A3 switch<br>IO5 (e.g., CBT device)<br>A2<br>IO6 B<br>A1<br>A0 IO7 SUB-SYSTEM 3<br>(e.g., alarm system)<br>VSS<br>ALARM<br>VDD<br>002aac025<br>**----- End of picture text -----**<br>


EEPROM device address configured as 1110 000x for this example. IO0, IO2, IO3 configured as outputs. IO1, IO4, IO5 configured as inputs. IO6, IO7 are not used and must be configured as outputs. **Fig 22. Typical application** 

## **10. Limiting values** 

**Table 4. Limiting values** In accordance with the Absolute Maximum Rating System (IEC 60134). 

|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VDD|supply voltage||−0.5|+4.0|V|
|VI|input voltage||VSS−0.5|5.5|V|
|II|input current||−20|+20|mA|
|IO|output current||−25|+25|mA|
|IDD|supply current||−100|+100|mA|
|ISS|ground supply current||−100|+100|mA|
|Ptot|total power dissipation||-|400|mW|
|P/out|power dissipation per output||-|100|mW|
|Tstg|storage temperature||−65|+150|°C|
|Tamb|ambient temperature|operating|−40|+85|°C|



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**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **11. Static characteristics** 

**Table 5. Static characteristics** VDD = 3.3 V; Tamb = −40 °C to +85 °C; unless otherwise specified. 

|**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**|
|---|---|
|**Supply**||
|VDD<br>supply voltage|2.5<br>3.3<br>3.6<br>V|
|IDDQ<br>standby current|A0 to A5;<br>WC = HIGH<br>-<br>-<br>60<br>µA|
|IDD1<br>supply current read|-<br>-<br>1<br>mA|
|IDD2<br>supply current write|-<br>-<br>2<br>mA|
|VPOR<br>power-on reset voltage|-<br>-<br>2.4<br>V|
|**Input SCL; input/output SDA**||
|VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD<br>V|
|VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V|
|IOL<br>LOW-level output current|VOL= 0.4 V<br>3<br>-<br>-<br>mA|
|ILI<br>input leakage current|VI= VDDor VSS<br>−1<br>-<br>+1<br>µA|
|Ci<br>input capacitance|VI= VSS<br>-<br>-<br>7<br>pF|
|**I/O expander port**||
|VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD<br>V|
|VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V|
|IIHL(max)<br>input current through protection diodes|−400<br>-<br>+400<br>µA|
|IOL<br>LOW-level output current|VOL= 1 V<br>[1] 10<br>25<br>-<br>mA|
|IOH<br>HIGH-level output current|VOH= VSS<br>30<br>100<br>300<br>µA|
|IOHt<br>transient pull-up current|-<br>2<br>-<br>mA|
|Ci<br>input capacitance|-<br>-<br>10<br>pF|
|Co<br>output capacitance|-<br>-<br>10<br>pF|
|**Address inputs A0 to A5;**<br>**WC input**||
|VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD<br>V|
|VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V|
|ILI<br>input leakage current|VI= VDD<br>−1<br>-<br>+1<br>µA|
||pull-up; VI= VSS<br>10<br>25<br>100<br>µA|
|**Interrupt output**<br>**INT**||
|IOL<br>LOW-level output current|VOL= 0.4 V<br>1.6<br>-<br>-<br>mA|
|IL<br>leakage current|VI= VDDor VSS<br>−1<br>-<br>+1<br>µA|



[1] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. 

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**Product data sheet** 

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**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**==> picture [482 x 371] intentionally omitted <==**

**----- Start of picture text -----**<br>
002aad307 002aad308<br>20 20<br>IOH VDD = 2.5 V2.7 V IOH VDD = 2.5 V2.7 V<br>(µA) 3.0 V (µA) 3.0 V<br>3.3 V −20 3.3 V<br>−40 3.6 V 3.6 V<br>−60<br>−100<br>−100<br>−160 −140<br>0 1.2 2.4 3.6 0 1.2 2.4 3.6<br>VOH (V) VOH (V)<br>a. Tamb = −40 °C b. Tamb = 25 °C<br>002aad309<br>20<br>IOH VDD = 2.5 V2.7 V<br>(µA) 3.0 V<br>−20 3.3 V<br>3.6 V<br>−60<br>−100<br>−140<br>0 1.2 2.4 3.6<br>VOH (V)<br>c. Tamb = 85 °C<br>Fig 23. VOH versus IOH<br>**----- End of picture text -----**<br>


**Remark:** Rapid fall-off in VOH at current inception is due to a diode that provides 5 V overvoltage protection for the GPIO I/O pins. When the GPIO I/Os are being used as inputs, the internal current source VOH should be evaluated to determine if external pull-up resistors are required to provide sufficient VIH threshold noise margin. 

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**16 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **12. Dynamic characteristics** 

## **Table 6. Dynamic characteristics** 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**I2C-bus timin**~~**g**~~<br>**[1]** **(see**<br>**Figure**<br>**24)**||||||||
|fSCL|SCL clock frequency|||-|-|400|kHz|
|tSP|pulse width of spikes that must be<br>suppressed by the input flter|||-|-|50|ns|
|tBUF|bus free time between a STOP and START|||1.3|-|-|µs|
||condition|||||||
|tSU;STA|set-up time for a repeated START condition|||0.6|-|-|µs|
|tHD;STA|hold time (repeated) START condition|||0.6|-|-|µs|
|tr|rise time of both SDA and SCL signals|||-|-|0.3|µs|
|tf|fall time of both SDA and SCL signals|||-|-|0.3|µs|
|tSU;DAT|data set-up time|||250|-|-|ns|
|tHD;DAT|data hold time|||0|-|-|ns|
|tVD;DAT|data valid time|SCL LOW to||-|-|1.0|µs|
|||data output||||||
|tSU;STO|set-up time for STOP condition|||0.6|-|-|µs|
|**Port timing**||||||||
|tv(Q)|data output valid time|CL≤100 pF||-|-|4|µs|
|tsu(D)|data input set-up time|CL≤100 pF||0|-|-|µs|
|th(D)|data input hold time|CL≤100 pF||4|-|-|µs|
|**Interrupt timing**||||||||
|tv(INT)|valid time on pin<br>INT|CL≤100 pF||-|-|4|µs|
|trst(INT)|reset time on pin<br>INT|CL≤100 pF||-|-|4|µs|
|**Power-up timing**||||||||
|tpu(R)|read power-up time||[2]|-|-|1|ms|
|tpu(W)|write power-up time||[2]|-|-|5|ms|
|**Write cycle**|**limits (see**<br>**Figure**<br>**25)**|||||||
|Tcy(W)|write cycle time||[3]|-|5|10|ms|



[1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. 

[2] tpu(R) and tpu(W) are the delays required from the time VDD guaranteed by design. 

[3] Tcy(W) is the maximum time that the device requires to perform the internal write operation. 

**Table 7.** 

|**Parameter**|**Specifcation**|
|---|---|
|memory cell data retention|10 years minimum|
|number of memory cell write cycles|100,000 cycles minimum|



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PCA9501_4 

**Product data sheet** 

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**17 of 28** 

**PCA9501** 

**NXP Semiconductors** 

## **8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**==> picture [497 x 329] intentionally omitted <==**

**----- Start of picture text -----**<br>
START bit 7 STOP<br>protocol condition MSB bit 6 bit 0 acknowledge condition<br>(A6) (R/W) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH 1/fSCL<br>SCL<br>tBUF tf<br>tr<br>SDA<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab175<br>Fig 24. I [2] C-bus timing<br>SCL<br>SDA 8 [th]  bit ACK<br>memory<br>word n Tcy(W) address<br>STOP START<br>condition condition 002aad310<br>Fig 25. Write cycle timing<br>**----- End of picture text -----**<br>


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**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **13. Package outline** 

## **SO20: plastic small outline package; 20 leads; body width 7.5 mm** 

## **SOT163-1** 

**==> picture [478 x 570] intentionally omitted <==**

**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>20 11<br>Q<br>A2 A<br>A1 (A  )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 10 detail X<br>e w M<br>b p<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>0.3 2.45 0.49 0.32 13.0 7.6 10.65 1.1 1.1 0.9<br>mm 2.65 0.1 2.25 0.25 0.36 0.23 12.6 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o<br>0.012 0.096 0.019 0.013 0.51 0.30 0.419 0.043 0.043 0.035 0o<br>inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004<br>0.004 0.089 0.014 0.009 0.49 0.29 0.394 0.016 0.039 0.016<br>Note<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>99-12-27<br> SOT163-1  075E04  MS-013<br>03-02-19<br>**----- End of picture text -----**<br>


**Fig 26. Package outline SOT163-1 (SO20)** 

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**Product data sheet** 

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**PCA9501** 

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**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm** 

**SOT360-1** 

**==> picture [478 x 570] intentionally omitted <==**

**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>20 11<br>Q<br>A2 (A  )3 A<br>pin 1 index A1<br>θ<br>L p<br>L<br>1 10<br>detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp Q v w y Z (1) θ<br>mm 1.1 0.150.05 0.950.80 0.25 0.300.19 0.20.1 6.66.4 4.54.3 0.65 6.66.2 1 0.750.50 0.40.3 0.2 0.13 0.1 0.50.2 80oo<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>99-12-27<br> SOT360-1  MO-153<br>03-02-19<br>**----- End of picture text -----**<br>


**Fig 27. Package outline SOT360-1 (TSSOP20)** 

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**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm** 

**SOT662-1** 

**==> picture [478 x 559] intentionally omitted <==**

**----- Start of picture text -----**<br>
D B A<br>terminal 1<br>index area<br>A<br>A1<br>E c<br>detail X<br>C<br>e1<br>e b v M C A B y1 C y<br>6 10 w M C<br>L<br>11<br>5<br>e<br>Eh e2<br>1<br>15<br>terminal 1<br>index area 20 16<br>X<br>Dh<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.38 5.1 3.25 5.1 3.25 0.75<br>mm 1 0.2 0.65 2.6 2.6 0.1 0.05 0.05 0.1<br>0.00 0.23 4.9 2.95 4.9 2.95 0.50<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>01-08-08<br> SOT662-1 - - - MO-220 - - -<br>02-10-22<br>**----- End of picture text -----**<br>


**Fig 28. Package outline SOT662-1 (HVQFN20)** 

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**PCA9501** 

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**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **14. Soldering of SMD packages** 

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 

## **14.1 Introduction to soldering** 

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 

## **14.2** 

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: 

- Through-hole components 

- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board 

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. 

component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. 

- 

- Package footprints, including solder thieves and orientation 

- The moisture sensitivity level of the packages 

- Package placement 

- Inspection and repair 

- Lead-free soldering versus SnPb soldering 

## **14.3 Wave soldering** 

Key characteristics in wave soldering are: 

- transport, the solder wave parameters, and the time during which components are exposed to the wave 

- 

© NXP B.V. 2009. All rights reserved. 

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**Product data sheet** 

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**PCA9501** 

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**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **14.4** 

- higher minimum peak temperatures (see Figure 29) than a SnPb process, thus reducing the process window 

- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board 

- heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 8 and 9 

**Table 8. SnPb eutectic process (from J-STD-020C)** 

|**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**|
|---|---|---|
||**Volume (mm3)**||
||**< 350**|≥**350**|
|< 2.5|235<br>220||
|≥2.5|220<br>220||



## **Table 9. Lead-free process (from J-STD-020C)** 

|**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**|
|---|---|---|---|
||**Volume (mm3)**|||
||**< 350**|**350 to 2000**|**> 2000**|
|< 1.6|260<br>260<br>260|||
|1.6 to 2.5|260<br>250<br>245|||
|> 2.5|250<br>245<br>245|||



Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. 

soldering, see Figure 29. 

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**PCA9501** 

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**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**==> picture [352 x 225] intentionally omitted <==**

**----- Start of picture text -----**<br>
maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 29. Temperature profiles for large and small components<br>**----- End of picture text -----**<br>


“Surface mount reflow soldering description”. 

## **15. Abbreviations** 

**Table 10. Abbreviations** 

|**Acronym**|**Description**|
|---|---|
|ASIC|Application Specifc Integrated Circuit|
|CBT|Cross Bar Technology|
|CDM|Charged-Device Model|
|CPU|Central Processing Unit|
|EEPROM|Electrically Erasable Programmable Read Only Memory|
|ESD|ElectroStatic Discharge|
|GPIO|General Purpose Input/Output|
|HBM|Human Body Model|
|I2C-bus|Inter Integrated Circuit bus|
|I/O|Input/Output|
|IC|Integrated Circuit|
|LED|Light Emitting Diode|
|LP|Low-Pass|
|µC|micro Controller|
|MM|Machine Model|
|SMBus|System Management Bus|



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**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **16. Revision history** 

**Table 11. Revision history** 

|**Document ID**|**Release date**<br>**Data sheet status**<br>**Change notice**|**Release date**<br>**Data sheet status**<br>**Change notice**|**Supersedes**|
|---|---|---|---|
|PCA9501_4|20090210<br>Product data sheet<br>-||PCA9501_3|
|Modifcations:|**•**|The format of this data sheet has been redesigned to comply with the new identity guidelines of||
|||NXP Semiconductors.||
||**•**|Legal texts have been adapted to the new company name where appropriate.||
||**•**|Section 1 “Gener<br>aldescr<br>iption”,5thparagraph, 2ndsentence changed from “The fxed GPIO<br>address starts with ‘1’ and the fxed EEPROM I2C address starts with ‘0’, ...” to “The fxed GPIO<br>address starts with ‘0’ and the fxed EEPROM I2C-bus address starts with ‘1’, ...”||
||**•**|T<br>ab<br>le 3“Pindescr<br>iption”:||
|||||
|||**–**<br>pin “WC” corrected to “<br>WC”||
|||**–**<br>added<br>T<br>ab<br>lenote<br>1and its reference at HVQFN20 pin 8||
|||**–**<br>changed naming convention for pins I/On to “IOn”||
||**•**|Section 7.1 “De<br>vice addressing”: added Remark and bulleted list (4 items)||
||**•**|Figure7 “I/OWr<br>itemode (output)”: changed symbol “tpv” to “tv(Q)”||
||**•**|Figure 8“I/OReadmode (input)”:||
|||**–**<br>changed symbol “tph” to “th(D)”||
|||**–**<br>changed symbol “tps” to “tsu(D)”||
|||**–**<br>changed symbol “tiv” to “tv(INT)”||
|||**–**<br>changed symbol “tir” to “trst(INT)”||
||**•**|Section 7.3.2 “Interr<br>upt”,2ndparagraph: changed symbol “tiv” to “tv(INT)”||
||**•**|Figure11 “Interr<br>upt gener<br>ated b<br>y a change of input toIO5”:||
|||**–**<br>changed symbol “tiv” to “tv(INT)”||
|||**–**<br>changed symbol “tir” to “trst(INT)”||
||**•**|T<br>ab<br>le4 “Limitingv<br>alues”:||
|||**–**<br>changed symbol “VCC” to “VDD”||
|||**–**<br>changed parameter for ISSfrom “supply current” to “ground supply current”||
|||**–**<br>changed symbol “PO” to “P/out”||
||**•**|T<br>ab<br>le 5“Static char<br>acter<br>istics”:||
|||**–**<br>sub-section “Input SCL; input/output SDA”: changed symbol “IL” to “ILI”||
|||**–**<br>sub-section “Address inputs A0 to A5;<br>WC input”: changed symbol “IL” to|“ILI”|
|||**–**<br>added reference to<br>T<br>ab<br>lenote<br>1at IOLin sub-section “I/O expander port”||
||**•**|T<br>ab<br>le 6“Dynamic char<br>acter<br>istics”:||
|||**–**<br>sub-section “I2C-bus timing”: changed symbol/parameter from “tSW, tolerable spike width on<br>bus” to “tSP, pulse width of spikes that must be suppressed by the input flter”||
|||**–**<br>sub-section “Port timing”: changed symbol “tpv” to “tv(Q)”||
|||**–**<br>sub-section “Port timing”: changed symbol “tph” to “th(D)”||
|||**–**<br>sub-section “Port timing”: changed symbol “tps” to “tsu(D)”||
|||**–**<br>sub-section “Interrupt timing”: changed symbol “tiv” to “tv(INT)”||
|||**–**<br>sub-section “Interrupt timing”: changed symbol “tir” to “trst(INT)”||
|||**–**<br>sub-section “Power-up timing”: changed symbol “tPUR” to “tpu(R)”||
|||**–**<br>sub-section “Power-up timing”: changed symbol “tPUW” to “tpu(W)”||



- sub-section “Write cycle limits”: changed symbol “tWR” to “Tcy(W)” 

© NXP B.V. 2009. All rights reserved. 

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**Product data sheet** 

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**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

**Table 11. Revision history** …continued 

|**Document ID**|**Release date**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**|
|---|---|---|---|---|---|
|Modifcations:|**•** added|Section|15“Ab<br>bre<br>viations”|||
|(continued)|**•** updated soldering information|||||
|PCA9501_3|20040930||Product data|-|PCA9501_2|
|(9397 750 14135)||||||
|PCA9501_2|20030912||Product data|853-2370 30128 of|PCA9501_1|
|(9397 750 12058)||||2003 Jul 18||
|PCA9501_1|20020927||Product data|853-2370 28875 of|-|
|(9397 750 10327)||||2002 Sep 09||



© NXP B.V. 2009. All rights reserved. 

PCA9501_4 **Product data sheet** 

**Rev. 04 — 10 February 2009** 

**26 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **17. Legal information** 

## **17.1 Data sheet status** 

|**Document statu**|**s**<br>**[1]**<br>**[2]**<br>**Product status**<br>**[3]**<br>**Defnition**|
|---|---|
|Objective [short] data sheet<br>Development<br>This document contains data from the objective specifcation for product development.||
|Preliminary [short] data sheet<br>Qualifcation<br>This document contains data from the preliminary specifcation.||
|Product [short] data sheet<br>Production<br>This document contains the product specifcation.||



[1] Please consult the most recently issued document before initiating or completing a design. 

[2] 

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 

## **17.2** 

**Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 

## **17.3 Disclaimers** 

**General —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 

**Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 

**Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 

to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 

**Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

**Limiting values —** the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 

**Terms and conditions of sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 

**No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

## **17.4 Trademarks** 

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 

**I[2] C-bus  —** logo is a trademark of NXP B.V. 

## **18. Contact information** 

For more information, please visit: **http://www.nxp.com** 

**salesaddresses@nxp.com** 

© NXP B.V. 2009. All rights reserved. 

PCA9501_4 

**Product data sheet** 

**Rev. 04 — 10 February 2009** 

**27 of 28** 

**PCA9501** 

**NXP Semiconductors** 

**8-bit I[2] C-bus and SMBus I/O port with interrupt, 2-kbit EEPROM** 

## **19. Contents** 

|**1**|**General description . . . . . . . . . . . . . . . . . . . . . .  1**|**18**|
|---|---|---|
|**2**|**Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1**|**19**|
|**3**|**Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2**||
|**4**|**Ordering information . . . . . . . . . . . . . . . . . . . . .  2**||
|4.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2||
|**5**|**Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . .  3**||
|**6**|**Pinning information. . . . . . . . . . . . . . . . . . . . . .  3**||
|6.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3||
|6.2|Pin description  . . . . . . . . . . . . . . . . . . . . . . . . . 4||
|**7**|**Functional description  . . . . . . . . . . . . . . . . . . .  5**||
|7.1|Device addressing  . . . . . . . . . . . . . . . . . . . . . . 5||
|7.2|Control register . . . . . . . . . . . . . . . . . . . . . . . . . 6||
|7.3|I/O operations . . . . . . . . . . . . . . . . . . . . . . . . . . 6||
|7.3.1|Quasi-bidirectional I/Os  . . . . . . . . . . . . . . . . . . 7||
|7.3.2|Interrupt  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7||
|7.4|Memory operations. . . . . . . . . . . . . . . . . . . . . . 8||
|7.4.1|Write operations . . . . . . . . . . . . . . . . . . . . . . . . 8||
|7.4.1.1|Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8||
|7.4.1.2|Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9||
|7.4.2|Read operations . . . . . . . . . . . . . . . . . . . . . . . . 9||
|7.4.2.1|Current address read . . . . . . . . . . . . . . . . . . . . 9||
|7.4.2.2|Random read . . . . . . . . . . . . . . . . . . . . . . . . . 10||
|7.4.2.3|Sequential read. . . . . . . . . . . . . . . . . . . . . . . . 10||
|**8**|**Characteristics of the I2C-bus. . . . . . . . . . . . .  11**||
|8.1|Bit transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . . 11||
|8.1.1|START and STOP conditions . . . . . . . . . . . . . 11||
|8.2|System confguration  . . . . . . . . . . . . . . . . . . . 11||
|8.3|Acknowledge  . . . . . . . . . . . . . . . . . . . . . . . . . 12||
|**9**|**Application design-in information . . . . . . . . .  13**||
|**10**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .  14**||
|**11**|**Static characteristics. . . . . . . . . . . . . . . . . . . .  15**||
|**12**|**Dynamic characteristics . . . . . . . . . . . . . . . . .  17**||
|**13**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . .  19**||
|**14**|**Soldering of SMD packages . . . . . . . . . . . . . .  22**||
|14.1<br>14.2|Introduction to soldering . . . . . . . . . . . . . . . . . 22<br>Wave and refow soldering . . . . . . . . . . . . . . . 22||
|14.3<br>14.4|Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22<br>Refow soldering . . . . . . . . . . . . . . . . . . . . . . . 23||
|**15**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . .  24**||
|**16**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . .  25**||
|**17**|**Legal information. . . . . . . . . . . . . . . . . . . . . . .  27**||
|17.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27||
|17.2|Defnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27||
|17.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27||
|17.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27||



**Contact information  . . . . . . . . . . . . . . . . . . . . 27 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28** 

**==> picture [151 x 121] intentionally omitted <==**

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 

**© NXP B.V. 2009.** 

**All rights reserved.** 

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 10 February 2009 Document identifier: PCA9501_4**