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PCA9500PW,118
I/O Expander, 8bit, 400 kHz, I2C, SMBus, 2.5 V, 3.6 V, TSSOP
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- Manufacturer: NXP
- Product type: I/O Expanders
- No. of Pins: 16Pins
- No. of I/O's: 8I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C, SMBus
- Chip Configuration: 8bit
- Supply Voltage Max: 3.6V
- Supply Voltage Min: 2.5V
- Interface Case Style: TSSOP
| Delivery and price | |
|---|---|
| Units per pack | 1000 |
| Price | 1.32 € |
| Current stock | 1000+ |
| Lead time | 7 days |
Datasheet
## **PCA9500** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM Rev. 4.1 — 5 May 2017** **Product data sheet** ## **1. General description** The PCA9500 is an 8-bit I/O expander with an on-board 2-kbit EEPROM. The I/O expander's eight quasi-bidirectional data pins can be independently assigned as inputs or outputs to monitor board level status or activate indicator devices such as LEDs. The system master writes to the I/O configuration bits in the same way as for the PCF8574. The data for each input or output is kept in the corresponding Input or Output register. The system master can read all registers. The EEPROM can be used to store error codes or board manufacturing data for read-back by application software for diagnostic purposes and is included in the I/O expander package. The PCA9500 has three address pins with internal pull-up resistors allowing up to eight devices to share the common two-wire I[2] C software protocol serial data bus. The fixed GPIO I[2] C-bus address is the same as the PCF8574 and the fixed EEPROM I[2] C-bus address is the same as the PCF8582C-2, so the PCA9500 appears as two separate devices to the bus master. The PCA9500 supports hot insertion to facilitate usage in removable cards on backplane systems. The PCA9501 is an alternative to the functionally similar PCA9500 for systems where a higher number of devices are required to share the same I[2] C-bus or an interrupt output is required. ## **2. Features and benefits** - Eight general purpose input/output expander/collector - Drop-in replacement for PCF8574 with integrated 2-kbit EEPROM - Internal 256 8 EEPROM - Self timed write cycle - 4 byte page write operation - I[2] C-bus and SMBus interface logic - Internal power-on reset - Noise filter on SCL/SDA inputs - Three address pins allowing up to eight devices on the I[2] C-bus/SMBus - No glitch on power-up - Supports hot insertion - Power-up with all channels configured as inputs - Low standby current **==> picture [173 x 100] intentionally omitted <==** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** - Operating power supply voltage range of 2.5 V to 3.6 V - 5 V tolerant inputs/outputs - 0 Hz to 400 kHz clock frequency - ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 - Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA - Packages offered: SO16, TSSOP16, HVQFN16 ## **3. Applications** - Board version tracking and configuration - Board health monitoring and status reporting - Multi-card systems in telecommunications, networking, and base station infrastructure equipment - Field recall and troubleshooting functions for installed boards - General-purpose integrated I/O with memory - Drop-in replacement for PCF8574 with integrated 2-kbit EEPROM - Bus master sees GPIO and EEPROM as two separate devices - Three hardware address pins allow up to eight PCA9500s to be located in the same I[2] C-bus/SMBus © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **2 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **4. Ordering information** ## **Table 1. Ordering information** |**Type number**|**Topside**<br>**marking**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCA9500BS|9500|HVQFN16|plastic thermal enhanced very thin quad flat package;<br>no leads; 16 terminals; body 440.85 mm|SOT629-1| |PCA9500D|PCA9500D|SO16|plastic small outline package; 16 leads;<br>body width 7.5 mm|SOT162-1| |PCA9500PW|PCA9500|TSSOP16|plastic thin shrink small outline package; 16 leads;<br>body width 4.4 mm|SOT403-1| ## **4.1 Ordering options** **Table 2. Ordering options** |**Type number**|**Orderable**<br>**part number**|**Package**|**Packing method**|**Minimum**<br>**order quantity**|**Temperature**| |---|---|---|---|---|---| |PCA9500BS|PCA9500BS,118|HVQFN16|REEL 13" Q1/T1<br>*STANDARD MARK<br>SMD|6000|Tamb=40C to +85C| ||PCA9500BSHP|HVQFN16|REEL 13" Q2/T3<br>*STANDARD MARK<br>SMD|6000|Tamb=40C to +85C| |PCA9500D|PCA9500D,112|SO16|STANDARD<br>MARKING * IC'S<br>TUBE - DSC BULK<br>PACK|1920|Tamb=40C to +85C| ||PCA9500D,118|SO16|REEL 13" Q1/T1<br>*STANDARD MARK<br>SMD|1000|Tamb=40C to +85C| |PCA9500PW|PCA9500PW,112|TSSOP16|STANDARD<br>MARKING * IC'S<br>TUBE - DSC BULK<br>PACK|2400|Tamb=40C to +85C| ||PCA9500PW,118|TSSOP16|REEL 13" Q1/T1<br>*STANDARD MARK<br>SMD|2500|Tamb=40C to +85C| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **3 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **5. Block diagram** **==> picture [345 x 219] intentionally omitted <==** **----- Start of picture text -----**<br> PCA9500<br>300 k Ω<br>IO0<br>A0<br>A1 8-bit IO1<br>IO2<br>A2 INPUT/<br>IO3<br>OUTPUT<br>SCL INPUT write pulse PORTS IO4<br>SDA FILTER read pulse IO5IO6<br>I [2] C-BUS/SMBus<br>IO7<br>CONTROL<br>VDD POWER-ON<br>VSS RESET<br>EEPROM<br>WC<br>256 × 8<br>002aae585<br>**----- End of picture text -----**<br> **Fig 1. Block diagram of PCA9500** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **4 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **6. Pinning information** ## **6.1 Pinning** **==> picture [396 x 317] intentionally omitted <==** **----- Start of picture text -----**<br> A0 1 16 VDD A0 1 16 VDD<br>A1 2 15 SDA A1 2 15 SDA<br>A2 3 14 SCL A2 3 14 SCL<br>IO0 4 13 WC IO0 4 13 WC<br>PCA9500D PCA9500PW<br>IO1 5 12 IO7 IO1 5 12 IO7<br>IO2 6 11 IO6 IO2 6 11 IO6<br>IO3 7 10 IO5 IO3 7 10 IO5<br>VSS 8 9 IO4 VSS 8 9 IO4<br>002aae582 002aae583<br>Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16<br>terminal 1<br>index area<br>A2 1 12 SCL<br>IO0 2 11 WC<br>PCA9500BS<br>IO1 3 10 IO7<br>IO2 4 9 IO6<br>002aae584<br>Transparent top view<br>A1 A2 VDD SDA<br>16 15 14 13<br>5 6 7 8<br>IO3 VSS IO4 IO5<br>**----- End of picture text -----**<br> **Fig 4. Pin configuration for HVQFN16** ## **6.2 Pin description** ## **Table 3. Pin description** |**Symbol**|**Pin**<br>|**Pin**<br>|**Description**| |---|---|---|---| ||**SO16, TSSOP16**|**HVQFN16**|| |A0|1|15<br>|address lines (internal pull-up)| |A1|2|16|| |A2|3|1|| |IO0|4|2<br>|quasi-bidirectional I/O pins| |IO1|5|3|| |IO2|6|4|| |IO3|7|5|| |IO4|9|7|| |IO5|10|8|| |IO6|11|9|| |IO7|12|10|| ||All informationprovided in this document is subject to legal disclaimers.<br>© NXP Semiconductors N.V. 2017. All rights reserved.||| PCA9500 **Product data sheet** **Rev. 4.1 — 5 May 2017** **5 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **Table 3. Pin description** _…continued_ |**Symbol**|**Pin**|**Pin**|**Description**| |---|---|---|---| ||**SO16, TSSOP16**|**HVQFN16**|| |VSS|8|6[1]|supply ground| |WC|13|11|active LOW write control pin| |SCL|14|12|I2C-bus serial clock| |SDA|15|13|I2C-bus serial data| |VDD|16|14|supply voltage| - [1] HVQFN16 package supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **6 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **7. Functional description** “ ” Refer also to Figure 1 Block diagram of PCA9500 . **==> picture [363 x 200] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>write pulse<br>100 μ A<br>data from shift register D Q<br>FF<br>IO0 to IO7<br>CI<br>S<br>power-on reset VSS<br>D Q<br>FF<br>read pulse CI<br>S<br>to interrupt logic<br>data to shift register<br>002aae588<br>Fig 5. Simplified schematic diagram of each I/O<br>**----- End of picture text -----**<br> ## **7.1 Device addressing** Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9500 is shown in Figure 6. Internal pull-up resistors are incorporated on the hardware selectable address pins. The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. **==> picture [360 x 102] intentionally omitted <==** **----- Start of picture text -----**<br> slave address slave address<br>0 1 0 0 A2 A1 A0 R/W 1 0 1 0 A2 A1 A0 R/W<br>fixed hardware fixed hardware<br>programmable programmable<br>002aae589 002aae590<br>a. I/O expander b. Memory<br>Fig 6. PCA9500 slave addresses<br>**----- End of picture text -----**<br> ## **7.2 Control register** The PCA9500 contains a single 8-bit register called the Control register, which can be written and read via the I[2] C-bus. This register is sent after a successful acknowledgment of the slave address. It contains the I/O operation information. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **7 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **7.3 I/O operations** (Refer also to Figure 5.) Each of the PCA9500's eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O Write mode (see Figure 7). Input I/O data is transferred from the port to the microcontroller by the Read mode (see Figure 8). **==> picture [496 x 364] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>slave address (I/O expander) data to port data to port<br>SDA S 0 1 0 0 A2 A1 A0 0 A DATA 1 A DATA 2 A<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>write to port<br>tv(Q) tv(Q)<br>data out from port DATA 1 VALID DATA 2 VALID<br>002aae591<br>Fig 7. I/O Write mode (output)<br>SCL 1 2 3 4 5 6 7 8 9<br>no acknowledge<br>from master<br>slave address (I/O expander) data from port data from port<br>SDA S 0 1 0 0 A2 A1 A0 1 A DATA 1 A DATA 4 1 P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from master condition<br>read from<br>port<br>DATA 2<br>data into<br>DATA 1 DATA 3 DATA 4<br>port<br>th(D) tsu(D)<br>002aae592<br>Fig 8. I/O Read mode (input)<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **8 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **7.3.1 Quasi-bidirectional I/Os** A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. See Figure 9. **==> picture [408 x 151] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address (I/O expander) data to port data to port<br>SDA S 0 1 0 0 A2 A1 A0 0 A 1 A 0 A P<br>START condition R/W acknowledge IO3 acknowledge IO3 acknowledge<br>from slave from slave from slave<br>IO3 output voltage<br>IO3 pull-up output current<br>IOHt IOH<br>002aae593<br>**----- End of picture text -----**<br> **Fig 9. Transient pull-up current (IOHt) while IO3 changes from LOW to HIGH and back to LOW** ## **7.4 Memory operations** ## **7.4.1 Write operations** Write operations require an additional address field to indicate the memory address location to be written. The address field is eight bits long, providing access to any one of the 256 words of memory. There are two types of write operations, ‘byte write’ and ‘page write’. Write operation is possible when the Write Control pin (WC) is put at a LOW logic level (0). When this control signal is set at 1, write operation is not possible and data in the memory is protected. ‘Byte write’ and ‘page write’ explained below assume that WC is set to 0. ## **7.4.1.1 Byte write** To perform a byte write the START condition is followed by the memory slave address and the R/W bit set to 0. The PCA9500 will respond with an acknowledge and then consider the next eight bits sent as the word address and the eight bits after the word address as the data. The PCA9500 will issue an acknowledge after the receipt of both the word address and the data. To terminate the data transfer the master issues the STOP condition, initiating the internal write cycle to the non-volatile memory. Only write and read operations to the quasi-bidirectional I/Os are allowed during the internal write cycle. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **9 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **==> picture [392 x 77] intentionally omitted <==** **----- Start of picture text -----**<br> slave address (memory) word address data<br>SDA S 1 0 1 0 A2 A1 A0 0 A A A P<br>START condition R/W acknowledge acknowledge acknowledge STOP condition.<br>from slave from slave from slave Write to the memory<br>is performed.<br>002aae594<br>**----- End of picture text -----**<br> **Fig 10. Byte write** ## **7.4.1.2 Page write** A page write is initiated in the same way as the byte write. If after sending the first word of data, the STOP condition is not received, the PCA9500 considers subsequent words as data. After each data word the PCA9500 responds with an acknowledge and the two least significant bits of the memory address field are incremented. Should the master not send a STOP condition after four data words, the address counter will return to its initial value and overwrite the data previously written. After the receipt of the STOP condition the inputs will behave as with the byte write during the internal write cycle. **==> picture [440 x 91] intentionally omitted <==** **----- Start of picture text -----**<br> slave address (memory) word address data to memory data to memory<br>SDA S 1 0 1 0 A2 A1 A0 0 A A DATA n A DATA n + 3 A P<br>START condition R/W acknowledge acknowledge acknowledge acknowledge<br>from slave from slave from slave from slave<br>STOP condition.<br>Write to the memory is performed.<br>002aae595<br>**----- End of picture text -----**<br> **Fig 11. Page write** ## **7.4.2 Read operations** PCA9500 read operations are initiated in an identical manner to write operations with the exception that the memory slave address R/W bit is set to ‘1’. There are three types of read operations: current address read, random read and sequential read. ## **7.4.2.1 Current address read** The PCA9500 contains an internal address counter that increments after each read or write access and as a result, if the last word accessed was at address ‘n’, then the address counter contains the address ‘n + 1’. When the PCA9500 receives its memory slave address with the R/W bit set to one it issues an acknowledge and uses the next eight clocks to transmit the data contained at the address stored in the address counter. The master ceases the transmission by issuing the STOP condition after the eighth bit. There is no ninth clock cycle for the acknowledge. See Figure 12. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **10 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **==> picture [343 x 83] intentionally omitted <==** **----- Start of picture text -----**<br> slave address (memory) data from memory<br>SDA S 1 0 1 0 A2 A1 A0 1 A P<br>START condition R/W acknowledge STOP condition<br>from slave 002aae596<br>Fig 12. Current address read<br>**----- End of picture text -----**<br> ## **7.4.2.2 Random read** The PCA9500's random read mode allows the address to be read from to be specified by the master. This is done by performing a dummy write to set the address counter to the location to be read. The master must perform a byte write to the address location to be read, but instead of transmitting the data after receiving the acknowledge from the PCA9500, the master re-issues the START condition and memory slave address with the R/W bit set to one. The PCA9500 will then transmit an acknowledge and use the next eight clock cycles to transmit the data contained in the addressed location. The master ceases the transmission by issuing the STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge. **==> picture [469 x 93] intentionally omitted <==** **----- Start of picture text -----**<br> slave address (memory) word address slave address (memory) data from memory<br>SDA S 1 0 1 0 A2 A1 A0 0 A A S 1 0 1 0 A2 A1 A0 1 A P<br>START condition R/W acknowledge acknowledge START condition R/W STOP<br>from slave from slave condition<br>acknowledge<br>from slave 002aae597<br>Fig 13. Random read<br>**----- End of picture text -----**<br> ## **7.4.2.3 Sequential read** The PCA9500 sequential read is an extension of either the current address read or random read. If the master does not issue a STOP condition after it has received the eighth data bit, but instead issues an acknowledge, the PCA9500 will increment the address counter and use the next eight cycles to transmit the data from that location. The master can continue this process to read the contents of the entire memory. Upon reaching address 255 the counter will return to address 0 and continue transmitting data until a STOP condition is received. The master ceases the transmission by issuing the STOP condition after the eighth bit, omitting the ninth clock cycle acknowledge. **==> picture [425 x 69] intentionally omitted <==** **----- Start of picture text -----**<br> slave address (memory) data from memory data from memory data from memory<br>SDA S 1 0 1 0 A2 A1 A0 1 A DATA n A DATA n + 1 A DATA n + X P<br>START condition R/W acknowledge acknowledge acknowledge STOP<br>from slave from master from master condition<br>002aae598<br>**----- End of picture text -----**<br> **==> picture [104 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 14. Sequential read<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **11 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **8. Characteristics of the I[2] C-bus** The I[2] C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ## **8.1 Bit transfer** One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 15). **==> picture [240 x 88] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>**----- End of picture text -----**<br> **Fig 15. Bit transfer** ## **8.1.1 START and STOP conditions** Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 16). **==> picture [318 x 76] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>S P<br>START condition STOP condition<br>mba608<br>**----- End of picture text -----**<br> **Fig 16. Definition of START and STOP conditions** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **12 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **8.2 System configuration** A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 17). **==> picture [382 x 101] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>MASTER SLAVE MASTER<br>SLAVE MASTER<br>TRANSMITTER/ TRANSMITTER/ TRANSMITTER/<br>RECEIVER TRANSMITTER<br>RECEIVER RECEIVER RECEIVER<br>002aaa381<br>Fig 17. System configuration<br>**----- End of picture text -----**<br> ## **8.3 Acknowledge** The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. **==> picture [297 x 129] intentionally omitted <==** **----- Start of picture text -----**<br> data output<br>by transmitter<br>not acknowledge<br>data output<br>by receiver<br>acknowledge<br>SCL from master<br>1 2 8 9<br>S<br>clock pulse for<br>START acknowledgement<br>condition 002aaa987<br>**----- End of picture text -----**<br> **Fig 18. Acknowledgement on the I[2] C-bus** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **13 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **9. Application design-in information** A central processor/controller typically located on the system main board can use the 400 kHz I[2] C-bus/SMBus to poll the PCA9500 devices located on the system cards for status or version control type of information. The PCA9500 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data, and so on. Alternately, these devices can be used as convenient interface for board configuration, thereby utilizing the I[2] C-bus/SMBus as an intra-system communication bus. **==> picture [409 x 213] intentionally omitted <==** **----- Start of picture text -----**<br> up to<br>8 cards<br>I [2] C-bus ASIC<br>CPU I [2] C-bus<br>OR I [2] C-bus BACKPLANE configuration control<br>μ C I [2] C-bus<br>PCA9500<br>I [2] C-bus<br>CONTROL<br>I [2] C-bus<br>INPUTS<br>GPIO monitoring ALARM<br>and LEDs<br>EEPROM control<br>card ID, subroutines, configuration data, or revision history<br>002aae586<br>**----- End of picture text -----**<br> **Fig 19. PCA9500 used as interface for board configuration** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **14 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **==> picture [400 x 241] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>10 k Ω 10 k Ω 10 k(optional) Ω 2 k Ω (e.g., temp sensor)SUB-SYSTEM 1<br>VDD VDD<br>INT<br>MASTER PCA9500<br>CONTROLLER<br>SCL SCL IO0<br>SUB-SYSTEM 2<br>SDA SDA IO1 (e.g., counter)<br>IO2 RESET<br>IO3<br>A<br>VSS IO4 enable controlled<br>switch<br>IO5 (e.g., CBT device)<br>A2<br>IO6 B<br>A1<br>A0 IO7 SUB-SYSTEM 3<br>(e.g., alarm system)<br>VSS<br>ALARM<br>VDD<br>002aae599<br>**----- End of picture text -----**<br> GPIO device address configured as 0100 100x for this example. EEPROM device address configured as 1010 100x for this example. IO0, IO2, IO3 configured as outputs. IO1, IO4, IO5 configured as inputs. IO6, IO7 are not used and must be configured as outputs. **Fig 20. Typical application** ## **10. Limiting values** ## **Table 4. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**||**Min**|**Max**|**Unit**| |---|---|---|---|---|---|---| |VDD|supply voltage|||0.5|+4.0|V| |VI|input voltage|||VSS0.5|5.5|V| |II|input current|||20|+20|mA| |IO|output current|||25|+25|mA| |IDD|supply current|||100|+100|mA| |ISS|ground supply current|||100|+100|mA| |Ptot|total power dissipation|||-|400|mW| |P/out|power dissipation per output|||-|100|mW| |Tstg|storage temperature|||65|+150|C| |Tamb|ambient temperature|operating||40|+85|C| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **15 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **11. Static characteristics** |**Table 5.**<br>**Static characteristics**|**Table 5.**<br>**Static characteristics**||||||| |---|---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |**Supply**|||||||| |VDD|supply voltage|||2.5|3.3|3.6|V| |IDDQ|standby current|A0, A1, A2, WC<br>= HIGH||-|-|60|A| |IDD1|supply current read|||-|-|1|mA| |IDD2|supply current write|||-|-|2|mA| |VPOR|power-on reset voltage|||-|-|2.4|V| |**Input SCL; input/output SDA**|||||||| |VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |IOL|LOW-level output current|VOL= 0.4 V||3|-|-|mA| |ILI|input leakage current|VI= VDDor VSS||1|-|+1|A| |Ci|input capacitance|VI= VSS||-|-|7|pF| |**I/O expander port**|||||||| |VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |IIHL(max)|input current through protection diodes|||400|-|+400|A| |IOL|LOW-level output current|VOL= 1 V|[1]|10|25|-|mA| |IOH|HIGH-level output current|VOH= VSS||30|100|300|A| |IOHt|transient pull-up current|||-|2|-|mA| |Ci|input capacitance|||-|-|10|pF| |Co|output capacitance|||-|-|10|pF| |**Address inputs A0, A1, A2; WC**<br>**input**|||||||| |VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |ILI|input leakage current|VI= VDD||1|-|+1|A| |||pull-up; VI= VSS||10|25|100|A| [1] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **16 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **==> picture [480 x 355] intentionally omitted <==** **----- Start of picture text -----**<br> 002aad307 002aad308<br>20 20<br>IOH VDD = 2.5 V 2.7 V IOH VDD = 2.5 V 2.7 V<br>( μ A) 3.0 V ( μ A) 3.0 V<br>3.3 V − 20 3.3 V<br>−4 0 3.6 V 3.6 V<br>− 60<br>− 100<br>− 100<br>− 160 − 140<br>0 1.2 2.4 3.6 0 1.2 2.4 3.6<br>VOH (V) VOH (V)<br>a. Tamb = 40 C b. Tamb = 25 C<br>002aad309<br>20<br>IOH VDD = 2.5 V 2.7 V<br>( μ A) 3.0 V<br>− 20 3.3 V<br>3.6 V<br>− 60<br>− 100<br>− 140<br>0 1.2 2.4 3.6<br>VOH (V)<br>c. Tamb = 85 C<br>**----- End of picture text -----**<br> **==> picture [100 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 21. VOH versus IOH<br>**----- End of picture text -----**<br> **Remark:** Rapid fall-off in VOH at current inception is due to a diode that provides 5 V overvoltage protection for the GPIO I/O pins. When the GPIO I/O are being used as inputs, the internal current source VOH should be evaluated to determine if external pull-up resistors are required to provide sufficient VIH threshold noise margin. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **17 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **12. Dynamic characteristics** ## **Table 6. Dynamic characteristics** |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |**I2C-bus timing[1]**<br> **(see Figure 22**<br>**)**|||||||| |fSCL|SCL clock frequency|||-|-|400|kHz| |tSP|pulse width of spikes that must be<br>suppressed by the input filter|||-|-|50|ns| |tBUF|bus free time between a STOP and START<br>condition|||1.3|-|-|s| |tSU;STA|set-up time for a repeated START condition|||0.6|-|-|s| |tHD;STA|hold time (repeated) START condition|||0.6|-|-|s| |tr|rise time of both SDA and SCL signals|||-|-|0.3|s| |tf|fall time of both SDA and SCL signals|||-|-|0.3|s| |tSU;DAT|data set-up time|||250|-|-|ns| |tHD;DAT|data hold time|||0|-|-|ns| |tVD;DAT|data valid time|SCL LOW to<br>data output||-|-|1.0|s| |tSU;STO|set-up time for STOP condition|||0.6|-|-|s| |**Port timing**|||||||| |tv(Q)|data output valid time|CL100 pF||-|-|4|s| |tsu(D)|data input set-up time|CL100 pF||0|-|-|s| |th(D)|data input hold time|CL100 pF||4|-|-|s| |**Power-up timing**|||||||| |tpu(R)|read power-up time||[2]|-|-|1|ms| |tpu(W)|write power-up time||[2]|-|-|5|ms| |**Write cycle limits (seeFigure 23**<br>**)**|||||||| |Tcy(W)|write cycle time||[3]|-|5|10|ms| [1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. [2] tpu(R) and tpu(W) are the delays required from the time VDD is stable until the specified operation can be initiated. These parameters are guaranteed by design. [3] Tcy(W) is the maximum time that the device requires to perform the internal write operation. ## **Table 7. Non-volatile storage specifications** |**Parameter**|**Specification**| |---|---| |memory cell data retention|10 years minimum| |number of memory cell write cycles|100,000 cycles minimum| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **18 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **==> picture [496 x 325] intentionally omitted <==** **----- Start of picture text -----**<br> START bit 7 STOP<br>protocol condition MSB bit 6 bit 0 acknowledge condition<br>(A6) (R/W) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH<br>1 / fSCL<br>SCL 0.7 × VDD<br>0.3 × VDD<br>tBUF tf<br>tr<br>SDA 0.7 × VDD<br>0.3 × VDD<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab175<br>Fig 22. I [2] C-bus timing<br>SCL<br>SDA 8 [th] bit ACK<br>memory<br>word n Tcy(W) address<br>STOP START<br>condition condition 002aad310<br>Fig 23. Write cycle timing<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **19 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **13. Package outline** ## **SO16: plastic small outline package; 16 leads; body width 7.5 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT162-1<br>**----- End of picture text -----**<br> **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>16 9<br>Q<br>A2 A<br>A1 (A )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 8 detail X<br>e w M<br>b p<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>0.3 2.45 0.49 0.32 10.5 7.6 10.65 1.1 1.1 0.9<br>mm 2.65 0.1 2.25 0.25 0.36 0.23 10.1 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o<br>0.012 0.096 0.019 0.013 0.41 0.30 0.419 0.043 0.043 0.035 0o<br>inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004<br>0.004 0.089 0.014 0.009 0.40 0.29 0.394 0.016 0.039 0.016<br>Note<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT162-1 075E03 MS-013<br>03-02-19<br>**----- End of picture text -----**<br> ## **Fig 24. Package outline SOT162-1 (SO16)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 **Product data sheet** **Rev. 4.1 — 5 May 2017** **20 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT403-1<br>**----- End of picture text -----**<br> **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>16 9<br>Q<br>A2 (A )3 A<br>pin 1 index A1<br>θ<br>L p<br>L<br>1 8<br>detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp Q v w y Z (1) θ<br>mm 1.1 0.150.05 0.950.80 0.25 0.300.19 0.20.1 5.14.9 4.54.3 0.65 6.66.2 1 0.750.50 0.40.3 0.2 0.13 0.1 0.400.06 80oo<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT403-1 MO-153<br>03-02-18<br>**----- End of picture text -----**<br> ## **Fig 25. Package outline SOT403-1 (TSSOP16)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 **Product data sheet** **Rev. 4.1 — 5 May 2017** **21 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT629-1<br>**----- End of picture text -----**<br> **==> picture [478 x 559] intentionally omitted <==** **----- Start of picture text -----**<br> D B A<br>terminal 1<br>index area A<br>A1<br>E c<br>detail X<br>e1<br>C<br>1/2 e<br>e b v M C A B y1 C y<br>5 8 w M C<br>L<br>9<br>4<br>e<br>Eh e2<br>1/2 e<br>1<br>12<br>terminal 1<br>index area 16 13<br>Dh X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.38 4.1 2.25 4.1 2.25 0.75<br>mm 1 0.2 0.65 1.95 1.95 0.1 0.05 0.05 0.1<br>0.00 0.23 3.9 1.95 3.9 1.95 0.50<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>01-08-08<br> SOT629-1 - - - MO-220 - - -<br>02-10-22<br>**----- End of picture text -----**<br> **Fig 26. Package outline SOT629-1 (HVQFN16)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 **Product data sheet** **Rev. 4.1 — 5 May 2017** **22 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **14. Soldering of SMD packages** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **14.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **14.2 Wave and reflow soldering** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: - Board specifications, including the board finish, solder masks and vias - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus SnPb soldering ## **14.3 Wave soldering** Key characteristics in wave soldering are: - Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave - Solder bath specifications, including temperature and impurities © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Rev. 4.1 — 5 May 2017** **Product data sheet** **23 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **14.4 Reflow soldering** Key characteristics in reflow soldering are: - Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 27) than a SnPb process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 8 and 9 ## **Table 8. SnPb eutectic process (from J-STD-020C)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|**350**| |< 2.5|235|220| |2.5|220|220| **Table 9. Lead-free process (from J-STD-020C)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260|260|260| |1.6 to 2.5|260|250|245| |> 2.5|250|245|245| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 27. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **24 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **==> picture [320 x 207] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>**----- End of picture text -----**<br> **Fig 27. Temperature profiles for large and small components** For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **15. Abbreviations** ## **Table 10. Abbreviations** |**Acronym**|**Description**| |---|---| |ASIC|Application Specific Integrated Circuit| |CBT|Cross-Bar Technology| |CDM|Charged-Device Model| |CPU|Central Processing Unit| |EEPROM|Electrically Erasable Programmable Read-Only Memory| |ESD|ElectroStatic Discharge| |FF|Flip-Flop| |GPIO|General Purpose Input/Output| |I2C-bus|Inter-Integrated Circuit bus| |I/O|Input/Output| |HBM|Human Body Model| |LED|Light-Emitting Diode| |MM|Machine Model| |SMBus|System Management Bus| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **25 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **16. Revision history** **Table 11. Revision history** |**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |---|---|---|---|---| |PCA9500 v.4.1|20170505|Product data sheet|-|PCA9500_4| |Modifications:|**•** Updated Section 4“<br>Ordering information<br>”|||| |PCA9500_4|20090415|Product data sheet|-|PCA9500_3| |Modifications:|**•** The format of this data sheet has been redesigned to comply with the new identity<br>guidelines of NXP Semiconductors.<br>**•** Legal texts have been adapted to the new company name where appropriate.<br>**•** Table 3“<br>Pin description<br>”<br>:<br>**–**<br>addedTable note [1]<br> and its reference at HVQFN16 pin 6<br>**–**<br>changed naming convention for pins I/On to “IOn”<br>**•** Figure 7“<br>I/O Write mode (output)<br>”<br>:changed symbol “tpv” to “tv(Q)”<br>**•** Figure 8“<br>I/O Read mode (input)<br>”<br>:<br>**–**<br>changed symbol “tph” to “th(D)”<br>**–**<br>changed symbol “tps” to “tsu(D)”<br>**•** Table 4“<br>Limiting values<br>”<br>:<br>**–**<br>changed symbol “VCC” to “VDD”<br>**–**<br>changed parameter for ISSfrom “supply current” to “ground supply current”<br>**–**<br>changed symbol “PO” to “P/out”<br>**–**<br>changed parameter for Tambfrom “operating temperature” to “ambient temperature”;<br>placed “operating” in Conditions column<br>**•** Table 5“<br>Static characteristics<br>”<br>:<br>**–**<br>added reference toTable note [1]<br> at IOLin sub-section “I/O expander port”<br>**•** Table 6“<br>Dynamic characteristics<br>”<br>:<br>**–**<br>sub-section “I2C-bus timing”: changed symbol/parameter from “tSW, tolerable spike<br>width on bus” to “tSP, pulse width of spikes that must be suppressed by the input filter”<br>**–**<br>sub-section “Port timing”: changed symbol “tpv” to “tv(Q)”<br>**–**<br>sub-section “Port timing”: changed symbol “tps” to “tsu(D)”<br>**–**<br>sub-section “Port timing”: changed symbol “tph” to “th(D)”<br>**–**<br>sub-section “Power-up timing”: changed symbol “tPUR” to “tpu(R)”<br>**–**<br>sub-section “Power-up timing”: changed symbol “tPUW” to “tpu(W)”<br>**–**<br>sub-section “Write cycle limits”: changed symbol “tWR” to “Tcy(W)”<br>**•** Figure 23“<br>Write cycle timing<br>”<br>:changed symbol “tWR” to “Tcy(W)”<br>**•** addedSection 15“<br>Abbreviations<br>”<br>**•** updated soldering information|||| |PCA9500_3<br>(9397 750 14134)|20040930|Product data sheet|-|PCA9500_2| |PCA9500_2|20030627|Product data|853-2369 30018<br>of 2003 Jun 11|PCA9500_1| |PCA9500_1|20020927|Product data|853-2369 28875<br>of 2002 Sep 27|-| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **26 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **17. Legal information** ## **17.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. - [2] The term ‘short data sheet’ is explained in section “Definitions”. - [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **17.2 Definitions** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ## **17.3 Disclaimers** **Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **27 of 29** **PCA9500** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Quick reference data —** The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. **Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. **Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **17.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP Semiconductors N.V. ## **18. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9500 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4.1 — 5 May 2017** **28 of 29** **PCA9500** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with 2-kbit EEPROM** ## **19. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 1**| |**3**|**Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2**| |**4**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 3**| |4.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3| |**5**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4**| |**6**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 5**| |6.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| |6.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5| |**7**|**Functional description . . . . . . . . . . . . . . . . . . . 7**| |7.1|Device addressing . . . . . . . . . . . . . . . . . . . . . . 7| |7.2|Control register . . . . . . . . . . . . . . . . . . . . . . . . . 7| |7.3|I/O operations . . . . . . . . . . . . . . . . . . . . . . . . . . 8| |7.3.1|Quasi-bidirectional I/Os . . . . . . . . . . . . . . . . . . 9| |7.4|Memory operations. . . . . . . . . . . . . . . . . . . . . . 9| |7.4.1|Write operations . . . . . . . . . . . . . . . . . . . . . . . . 9| |7.4.1.1|Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |7.4.1.2|Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10| |7.4.2|Read operations . . . . . . . . . . . . . . . . . . . . . . . 10| |7.4.2.1|Current address read . . . . . . . . . . . . . . . . . . . 10| |7.4.2.2|Random read . . . . . . . . . . . . . . . . . . . . . . . . . 11| |7.4.2.3|Sequential read . . . . . . . . . . . . . . . . . . . . . . . 11| |**8**|**Characteristics of the I2C-bus . . . . . . . . . . . . 12**| |8.1|Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12| |8.1.1|START and STOP conditions . . . . . . . . . . . . . 12| |8.2|System configuration . . . . . . . . . . . . . . . . . . . 13| |8.3|Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13| |**9**|**Application design-in information . . . . . . . . . 14**| |**10**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15**| |**11**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 16**| |**12**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 18**| |**13**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20**| |**14**|**Soldering of SMD packages . . . . . . . . . . . . . . 23**| |14.1|Introduction to soldering . . . . . . . . . . . . . . . . . 23| |14.2|Wave and reflow soldering . . . . . . . . . . . . . . . 23| |14.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 23| |14.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24| |**15**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25**| |**16**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26**| |**17**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 27**| |17.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27| |17.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27| |17.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27| |17.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28| **18** **19** **Contact information . . . . . . . . . . . . . . . . . . . . 28 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29** Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP Semiconductors N.V. 2017.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 5 May 2017 Document identifier: PCA9500**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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