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PCA8575PW,112
I/O Expander, 16bit, 400 kHz, I2C, 2.3 V, 5.5 V, TSSOP
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- Manufacturer: NXP
- Product type: I/O Expanders
- No. of Pins: 24Pins
- No. of I/O's: 16I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C
- Chip Configuration: 16bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 2.3V
- Interface Case Style: TSSOP
| Delivery and price | |
|---|---|
| Units per pack | 2500 |
| Price | 0.553 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**==> picture [35 x 38] intentionally omitted <==** ## **PCA8575** ## **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **Rev. 02 — 21 March 2007** **Product data sheet** ## **1. General description** The PCA8575 provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional I[2] C-bus (serial clock (SCL), serial data (SDA)). The device consists of a 16-bit quasi-bidirectional port and an I[2] C-bus interface. The PCA8575 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. The PCA8575 also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I[2] C-bus. The internal Power-On Reset (POR) initializes the I/Os as inputs. ## **2. Features** - I 400 kHz I[2] C-bus interface - I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os - I 16-bit remote I/O pins that default to inputs at power-up - I Latched outputs with 25 mA sink capability for directly driving LEDs - I Total package sink capability of 400 mA - I Active LOW open-drain interrupt output - I 8 programmable slave addresses using 3 address pins - I Readable device ID (manufacturer, device type, and revision) - I Low standby current (10 µA max.) - I −40 °C to +85 °C operation - I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 - I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA - I Packages offered: SO24, SSOP24 (QSOP24), TSSOP24, HVQFN24, DHVQFN24 ## **3. Applications** - I LED signs and displays - I Servers - I Industrial control - I Medical equipment - I PLCs - I Cellular telephones **==> picture [211 x 101] intentionally omitted <==** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## I Gaming machines I Instrumentation and test measurement ## **4. Ordering information** **Table 1. Ordering information** |**Type number**|**Topside**<br>**mark**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCA8575D<br>PCA8575D||SO24<br>plastic small outline package; 24 leads; body width 7.5 mm<br>SOT137-1||| |PCA8575DB<br>PCA8575DB||SSOP24<br>plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1||| |PCA8575DK<br>PCA8575||SSOP2~~4~~<br>[1]<br>plastic shrink small outline package; 24 leads;<br>body width 3.9 mm; lead pitch 0.635 mm<br>SOT556-1||| |PCA8575PW<br>PCA8575PW||TSSOP24<br>plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm<br>SOT355-1||| |PCA8575BQ<br>8575||DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad<br>fat package; no leads; 24 terminals; body 3.5×5.5×0.85 mm<br>SOT815-1||| |PCA8575BS<br>8575||HVQFN24<br>plastic thermal enhanced very thin quad fat package; no leads;<br>24 terminals; body 4×4×0.85 mm<br>SOT616-1||| [1] Also known as QSOP24. ## **5. Block diagram** **==> picture [350 x 192] intentionally omitted <==** **----- Start of picture text -----**<br> PCA8575<br>INTERRUPT<br>INT LP FILTER<br>LOGIC<br>AD0<br>AD1<br>AD2<br>P00 to P07<br>SCL INPUT I [2] C-BUS SHIFT I/O<br>16 BITS<br>FILTER CONTROL REGISTER PORT<br>SDA P10 to P17<br>write pulse<br>read pulse<br>POWER-ON<br>VDD RESET<br>VSS<br>002aac669<br>**----- End of picture text -----**<br> **Fig 1. Block diagram of PCA8575** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **2 of 30** **PCA8575** **NXP Semiconductors** ## **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **==> picture [350 x 178] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>write pulse IOH<br>100 µA<br>Itrt(pu)<br>data from Shift Register D Q<br>FF P00 to P07<br>CI IOL P10 to P17<br>S<br>power-on reset VSS<br>D Q<br>FF<br>read pulse CI<br>S<br>to interrupt logic<br>data to Shift Register<br>002aab631<br>**----- End of picture text -----**<br> **Fig 2.** ## **6. Pinning information** ## **6.1 Pinning** **==> picture [397 x 201] intentionally omitted <==** **----- Start of picture text -----**<br> INT 1 24 VDD INT 1 24 VDD<br>AD1 2 23 SDA AD1 2 23 SDA<br>AD2 3 22 SCL AD2 3 22 SCL<br>P00 4 21 AD0 P00 4 21 AD0<br>P01 5 20 P17 P01 5 20 P17<br>P02 6 19 P16 P02 6 19 P16<br>PCA8575D PCA8575PW<br>P03 7 18 P15 P03 7 18 P15<br>P04 8 17 P14 P04 8 17 P14<br>P05 9 16 P13 P05 9 16 P13<br>P06 10 15 P12 P06 10 15 P12<br>P07 11 14 P11 P07 11 14 P11<br>VSS 12 13 P10 VSS 12 13 P10<br>002aac670 002aac671<br>Fig 3. Pin configuration for SO24 Fig 4. Pin configuration for TSSOP24<br>**----- End of picture text -----**<br> © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **3 of 30** **PCA8575** **NXP Semiconductors** ## **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **==> picture [369 x 195] intentionally omitted <==** **----- Start of picture text -----**<br> INT 1 24 VDD INT 1 24 VDD<br>AD1 2 23 SDA AD1 2 23 SDA<br>AD2 3 22 SCL AD2 3 22 SCL<br>P00 4 21 AD0 P00 4 21 AD0<br>P01 5 20 P17 P01 5 20 P17<br>P02 6 19 P16 P02 6 19 P16<br>PCA8575DK PCA8575DB<br>P03 7 18 P15 P03 7 18 P15<br>P04 8 17 P14 P04 8 17 P14<br>P05 9 16 P13 P05 9 16 P13<br>P06 10 15 P12 P06 10 15 P12<br>P07 11 14 P11 P07 11 14 P11<br>VSS 12 13 P10 VSS 12 13 P10<br>002aac672 002aac673<br>Fig 5. Pin configuration for SSOP24 Fig 6. Pin configuration for SSOP24<br>(QSOP24)<br>**----- End of picture text -----**<br> **==> picture [374 x 218] intentionally omitted <==** **----- Start of picture text -----**<br> terminal 1<br>index area<br>AD1 2 23 SDA<br>terminal 1 AD2 3 22 SCL<br>index area P00 4 21 AD0<br>P01 5 20 P17<br>P00 1 18 AD0 P02 6 19 P16<br>PCA8575BQ<br>P01 2 17 P17 P03 7 18 P15<br>P02 3 16 P16 P04 8 17 P14<br>PCA8575BS<br>P03 4 15 P15 P05 9 16 P13<br>P04 5 14 P14 P06 10 15 P12<br>P05 6 13 P13 P07 11 14 P11<br>002aac675<br>002aac674<br>Transparent top view Transparent top view<br>Fig 7. Pin configuration for HVQFN24 Fig 8. Pin configuration for DHVQFN24<br>INT VDD<br>1 24<br>AD2 AD1 INT VDD SDA SCL<br>24 23 22 21 20 19<br>7 8 9 10 11 12 12 13<br>P06 P07 VSS P10 P11 P12 VSS P10<br>**----- End of picture text -----**<br> © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **4 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **6.2 Pin description** **Table 2. Pin description** |**Symbol**|**Pin**|**Pin**|**Description**| |---|---|---|---| ||**SO24, SSOP24,**<br>**TSSOP24, DHVQFN24**|**HVQFN24**|| |INT|1<br>22<br>interrupt output (active LOW)||| |AD1|2<br>23<br>address input 1||| |AD2|3<br>24<br>address input 2||| |P00|4<br>1<br>quasi-bidirectional I/O 00||| |P01|5<br>2<br>quasi-bidirectional I/O 01||| |P02|6<br>3<br>quasi-bidirectional I/O 02||| |P03|7<br>4<br>quasi-bidirectional I/O 03||| |P04|8<br>5<br>quasi-bidirectional I/O 04||| |P05|9<br>6<br>quasi-bidirectional I/O 05||| |P06|10<br>7<br>quasi-bidirectional I/O 06||| |P07|11<br>8<br>quasi-bidirectional I/O 07||| |VSS|12<br>[1]<br>~~9~~<br>[1]<br>supply ground||| |P10|13<br>10<br>quasi-bidirectional I/O 10||| |P11|14<br>11<br>quasi-bidirectional I/O 11||| |P12|15<br>12<br>quasi-bidirectional I/O 12||| |P13|16<br>13<br>quasi-bidirectional I/O 13||| |P14|17<br>14<br>quasi-bidirectional I/O 14||| |P15|18<br>15<br>quasi-bidirectional I/O 15||| |P16|19<br>16<br>quasi-bidirectional I/O 16||| |P17|20<br>17<br>quasi-bidirectional I/O 17||| |AD0|21<br>18<br>address input 0||| |SCL|22<br>19<br>serial clock line input||| |SDA|23<br>20<br>serial data line input/output||| |VDD|24<br>21<br>supply voltage||| - [1] HVQFN and DHVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **5 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **7. Functional description** Refer to Figure 1 “Block diagram of PCA8575”. ## **7.1 Device address** Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA8575 is shown in Figure 9. Slave address pins AD2, AD1, and AD0 choose 1 of 8 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 3 “PCA8575 address map”. **Remark:** The General Call address (0000 0000b) and the Device ID address (1111 100Xb) are reserved and cannot be used as device address. Failure to follow this requirement will cause the PCA8575 not to acknowledge. **==> picture [262 x 74] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>A6 A5 A4 A3 A2 A1 A0 R/W<br>programmable<br>002aab636<br>Fig 9. PCA8575 address<br>**----- End of picture text -----**<br> read is selected, while a logic 0 selects a write operation. When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8575 is applied. ## **7.1.1 Address map** |**Table**|**3.**|**PCA8575**|**PCA8575**|**address map**||||| |---|---|---|---|---|---|---|---|---| |**A6**||**A5**|**A4**|**A3**|**A2**|**A1**|**A0**|**Address (hex)**| |0||1|0|0|0|0|0|20h| |0||1|0|0|0|0|1|21h| |0||1|0|0|0|1|0|22h| |0||1|0|0|0|1|1|23h| |0||1|0|0|1|0|0|24h| |0||1|0|0|1|0|1|25h| |0||1|0|0|1|1|0|26h| |0||1|0|0|1|1|1|27h| © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **6 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **8. I/O programming** ## **8.1 Quasi-bidirectional I/O architecture** The PCA8575’s 16 ports (see Figure 2) are entirely independent and can be used either as input or output ports. Input data is transferred from the ports to the microcontroller in the Read mode (see Figure 12). Output data is transmitted to the ports in the Write mode (see Figure 11). Every data transmission from the PCA8575 must consist of an even number of bytes, the first byte will be referred to as P07 to P00, and the second byte as P17 to P10. The third will be referred to as P07 to P00, and so on. This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data directions. At power-on the I/Os are HIGH. In this mode only a current source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the Write mode. **Remark:** If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will flow to VSS. ## **8.2 Writing to the port (Output mode)** bit of the byte containing the slave address to logic 0 the Write mode is entered. The PCA8575 acknowledges and the master sends the first data byte for P07 to P00. After the first data byte is acknowledged by the PCA8575, the second data byte P17 to P10 is sent by the master. Once again, the PCA8575 acknowledges the receipt of the data. Each 8-bit data is presented on the port lines after it has been acknowledged by the PCA8575. The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is overwritten. byte in every pair refers to Port 1 (P17 to P10). See Figure 10. |first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte|first byte<br>second byte| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |07|||||||00|A|17|||||||10|A| ||06|05|04|03|02|01||||16|15|14|13|12|11||| ||||||||||||||||||| |002aab634<br>P06 P05 P04 P03 P02 P01 P00<br>P07<br>P16 P15 P14 P13 P12 P11 P10<br>P17|||||||||||||||||| **Fig 10. Correlation between bits and ports** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **7 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **==> picture [463 x 283] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>slave address data to port 0 data to port 1<br>P P P P P P P P P P P P P P<br>SDA S A6 A5 A4 A3 A2 A1 A0 0 A 07 06 1 04 03 02 01 00 A 17 1 15 14 13 12 11 10 A<br>START condition R/W P05 P16 acknowledge<br>acknowledge acknowledge from slave<br>from slave from slave<br>write to port<br>tv(Q) tv(Q)<br>data output from port data A0 and B0 valid data A0 and B0 valid<br>P05 output voltage<br>P05 pull-up output current Itrt(pu)<br>IOH<br>P16 output voltage<br>P16 pull-up output current Itrt(pu)<br>IOH<br>INT<br>td(rst) 002aab632<br>Fig 11. Write mode (output)<br>**----- End of picture text -----**<br> ## **8.3 Reading from a port (Input mode)** All ports programmed as input should be set to logic 1. To read, the master (microcontroller) first addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered. The data bytes that follow on the SDA are the values on the ports. If the data on the input port changes faster than the master can read, this data may be lost. © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **8 of 30** **==> picture [615 x 235] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>P0x P1x P0x P1x<br>SDA<br>S 0 1 0 0 A2 A1 A0 1 A DATA 00 A DATA 11 A DATA 00 A DATA 12 1 P<br>START condition R/W acknowledge acknowledge acknowledge no acknowledge<br>from master from master from master from master<br>acknowledge<br>from slave<br>read from port 0<br>data into port 0 DATA 00<br>read from port 1<br>data into port 1 DATA 10 DATA 11 DATA 12<br>INT<br>tv(D) td(rst) 002aab810<br>**----- End of picture text -----**<br> Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). **Fig 12. Read input port register, scenario 1** **==> picture [615 x 235] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>P0x P1x P0x P1x<br>SDA<br>S 0 1 0 0 A2 A1 A0 1 A DATA 00 A DATA 10 A DATA 03 A DATA 12 1 P<br>START condition R/W acknowledge acknowledge acknowledge no acknowledge<br>from master from master from master from master<br>acknowledge<br>from slave<br>read from port 0<br>th(D) tsu(D)<br>data into port 0 DATA 00 DATA 01 DATA 02 DATA 03<br>th(D)<br>read from port 1<br>tsu(D)<br>data into port 1 DATA 10 DATA 11 DATA 12<br>INT<br>tv(D) td(rst) 002aab811<br>**----- End of picture text -----**<br> Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). **Fig 13. Read input port register, scenario 2** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **8.4 Power-on reset** When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA8575 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA8575 registers and I[2] C-bus/SMBus state machine will initialize to their default states. Thereafter VDD must be lowered below 0.2 V to reset the device. ## **8.5 Interrupt output (INT)** The PCA8575 provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see Figure 12, Figure 13, and Figure 14). This gives these chips a kind of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs. After time tv(D) the signal INT is valid. The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt. In the Write mode, the interrupt may become deactivated (HIGH) on the rising edge of the write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely deactivated (HIGH). The interrupt is reset in the Read mode on the rising edge of the read from port pulse. During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as an INT. **==> picture [337 x 77] intentionally omitted <==** **----- Start of picture text -----**<br> VDD device 1 device 2 device 8<br>PCA8575 PCA8575 PCA8575<br>MICROCOMPUTER<br>INT INT INT<br>INT<br>002aac676<br>**----- End of picture text -----**<br> **Fig 14. Application of multiple PCA8575s with interrupt** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **11 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **9. Characteristics of the I[2] C-bus** The I[2] C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ## **9.1 Bit transfer** One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 15). **==> picture [242 x 88] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>**----- End of picture text -----**<br> **Fig 15. Bit transfer** ## **9.1.1 START and STOP conditions** Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 16.) **==> picture [341 x 83] intentionally omitted <==** **----- Start of picture text -----**<br> SDA SDA<br>SCL SCL<br>S P<br>START condition STOP condition<br>mba608<br>**----- End of picture text -----**<br> **Fig 16.** ## **9.2** A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 17). © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **12 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **==> picture [433 x 109] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>MASTER SLAVE SLAVE MASTER MASTER I [2] C-BUS<br>TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/ MULTIPLEXER<br>RECEIVER RECEIVER RECEIVER<br>SLAVE<br>002aaa966<br>**----- End of picture text -----**<br> **Fig 17.** ## **9.3 Acknowledge** The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. **==> picture [297 x 117] intentionally omitted <==** **----- Start of picture text -----**<br> data output<br>by transmitter<br>not acknowledge<br>data output<br>by receiver<br>acknowledge<br>SCL from master<br>1 2 8 9<br>S<br>clock pulse for<br>START acknowledgement<br>condition 002aaa987<br>**----- End of picture text -----**<br> **Fig 18. Acknowledgement on the I[2] C-bus** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **13 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **10. Application design-in information** ## **10.1 Bidirectional I/O expander applications** In the 8-bit I/O expander application shown in Figure 19, P00 and P01 are inputs, and P02 to P07 are outputs. When used in this configuration, during a write, the input (P00 and P01) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to P07). During a read, the logic levels of the external devices driving the input ports (P00 and P01) and the previous written logic level to the output ports (P02 to P07) will be read. The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there is incoming data or a change of data on its ports without having to communicate via the I[2] C-bus. **==> picture [267 x 129] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>VDD<br>VDD<br>SDA P00 temperature sensor<br>CORE SCL P01 battery status<br>PROCESSOR INT P02 control for latch<br>P03 control for switch<br>P04 control for audio<br>AD0 P05 control for camera<br>AD1 P06 control for MP3<br>AD2 P07<br>002aab812<br>**----- End of picture text -----**<br> **Fig 19. Bidirectional I/O expander application** ## **10.2 High current-drive load applications** The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one octal) can be connected together to drive 200 mA. **==> picture [232 x 122] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>VDD VDD<br>SDA P00<br>CORE SCL P01<br>PROCESSOR INT P02<br>P03 LOAD<br>P04<br>AD0 P05<br>AD1 P06<br>AD2 P07<br>002aab813<br>**----- End of picture text -----**<br> **Fig 20. High current-drive load application** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **14 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **10.3 Differences between the PCA8575 and the PCF8575** The PCA8575 is a drop in replacement for the PCF8575 and can used without electrical or software modifications, but there is a difference in interrupt output release timing during the read operation. Write operations are identical. At the completion of each 8-bit write sequence the data is stored in its associated 8-bit write register at ACK or NACK. The first byte goes to P0n while the second goes to P1n. Subsequent writes without a STOP wrap around to P0n then P1n again. Any write will update both read registers and clear interrupts. Read operations are identical. Both devices update the byte register with the pin data as each 8-bit read is initiated, the very first read after an address cycle corresponds to ports P0n while the second (even byte) corresponds to P1n and subsequent reads without a STOP wrap around to P0n then P1n again. During read operations, the PCA8575 interrupt output will be cleared in a byte-wise fashion as each byte is read. Reading the first byte will clear any interrupts associated with the P0n pins. This first byte read operation will have no effect on interrupts associated with changes of state on the P1n pins. Interrupts associated with the P1n pins will be cleared when the second byte is read. Reading the second byte has no effect on interrupts associated with the changes of state on the P0x pins. The PCF8575 interrupt output will clear after reading both bytes of data regardless of whether data was changed in the first byte or the second byte or both bytes. ## **11. Limiting values** **Table 4. Limiting values** In accordance with the Absolute Maximum Rating System (IEC 60134). |**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**| |---|---|---|---|---|---| |VDD|supply voltage||−0.5|+6|V| |IDD|supply current||-|±100|mA| |ISS|ground supply current||-|±600|mA| |VI|input voltage||VSS−0.5|5.5|V| |II|input current||-|±20|mA| |IO|output current||-|±50<br>[1]|mA| |Ptot|total power dissipation||-|600|mW| |P/out|power dissipation per output||-|200|mW| |Tstg|storage temperature||−65|+150|°C| |Tamb|ambient temperature|operating|−40|+85|°C| [1] Total package (maximum) output current is 600 mA. © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **15 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **12. Static characteristics** **Table 5. Static characteristics** VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |**Supplies**|| |VDD<br>supply voltage|2.3<br>-<br>5.5<br>V| |IDD<br>supply current|Operating mode; no load;<br>VI= VDDor VSS; fSCL= 400 kHz<br>-<br>100<br>200<br>µA| |Istb<br>standby current|Standby mode; no load;<br>VI= VDDor VSS<br>-<br>2.5<br>10<br>µA| |VPOR<br>power-on reset voltage|[1] -<br>1.8<br>2.0<br>V| |**Input SCL; input/output SDA**|| |VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD V| |VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V| |IOL<br>LOW-level output current|VOL= 0.4 V<br>20<br>-<br>-<br>mA| |IL<br>leakage current|VI= VDDor VSS<br>−1<br>-<br>+1<br>µA| |Ci<br>input capacitance|VI= VSS<br>-<br>5<br>10<br>pF| |**I/Os; P00 to P07 and P10 to P17**|| |IOL<br>LOW-level output current<br>[2]|VOL= 0.5 V; VDD= 2.3 V<br>12<br>28<br>-<br>mA| ||VOL= 0.5 V; VDD= 3.0 V<br>17<br>35<br>-<br>mA| ||VOL= 0.5 V; VDD= 4.5 V<br>25<br>42<br>-<br>mA| |IOL(tot)<br>total LOW-level output curren~~t~~<br>[2]|VOL= 0.5 V; VDD= 4.5 V<br>-<br>-<br>400<br>mA| |IOH<br>HIGH-level output current|VOH= VSS<br>−30<br>−102<br>−300<br>µA| |Itrt(pu)<br>transient boosted pull-up current|VOH= VSS; see<br>Figure<br>11<br>−0.5<br>−1.0<br>-<br>mA| |Cio(off)<br>off-state input/output<br>capacitance|[3] -<br>9<br>10<br>pF| |**Interrupt**<br>**INT**|| |IOL<br>LOW-level output current|VOL= 0.4 V<br>6<br>-<br>-<br>mA| |Co<br>output capacitance|-<br>3<br>5<br>pF| |**Inputs AD0, AD1, AD2**|| |VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD V| |VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V| |ILI<br>input leakage current|−1<br>-<br>+1<br>µA| |Ci<br>input capacitance|-<br>3.5<br>5<br>pF| [1] The power-on reset circuit resets the I[2] C-bus logic with VDD < VPOR and set all I/Os to logic 1 (with current source to VDD). [2] Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits. [3] © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **16 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **13. Dynamic characteristics** ## **Table 6. Dynamic characteristics** VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 ° |**Symbol**<br>**Parameter**<br>**Conditions**|**Fast mode I2C-bus**|**Fast mode I2C-bus**|**Fast mode I2C-bus**|**Unit**| |---|---|---|---|---| ||**Min**|**Typ**|**Max**|| |fSCL<br>SCL clock frequency|0<br>-<br>400<br>kHz|||| |tBUF<br>bus free time between a STOP and START<br>condition|1.3<br>-<br>-<br>µs|||| |tHD;STA<br>hold time (repeated) START condition|0.6<br>-<br>-<br>µs|||| |tSU;STA<br>set-up time for a repeated START condition|0.6<br>-<br>-<br>µs|||| |tSU;STO<br>set-up time for STOP condition|0.6<br>-<br>-<br>µs|||| |tHD;DAT<br>data hold time|0<br>-<br>-<br>ns|||| |tVD;ACK<br>data valid acknowledge time<br>[1]|0.1<br>-<br>0.9<br>µs|||| |tVD;DAT<br>data valid time<br>[2]|50<br>-<br>-<br>ns|||| |tSU;DAT<br>data set-up time|100<br>-<br>-<br>ns|||| |tLOW<br>LOW period of the SCL clock|1.3<br>-<br>-<br>µs|||| |tHIGH<br>HIGH period of the SCL clock|0.6<br>-<br>-<br>µs|||| |tf<br>fall time of both SDA and SCL signals<br>[3]<br>[4]|20 + 0.1Cb<br>[5]<br>-<br>300<br>ns|||| |tr<br>rise time of both SDA and SCL signals|20 + 0.1Cb<br>[5]<br>-<br>300<br>ns|||| |tSP<br>pulse width of spikes that must be suppressed<br>by the input flter<br>[6]|-<br>-<br>50<br>ns|||| |**Port timing; CL**≤**100 pF (see**<br>**Figure**<br>**11 and**<br>**Figure**<br>**12)**||||| |tv(Q)<br>data output valid time|-<br>-<br>4<br>µs|||| |tsu(D)<br>data input set-up time|0<br>-<br>-<br>µs|||| |th(D)<br>data input hold time|4<br>-<br>-<br>µs|||| |**Interrupt timing; CL**≤**100 pF (see**<br>**Figure**<br>**11 and**<br>**Figure**<br>**12)**||||| |tv(D)<br>data input valid time|-<br>-<br>4<br>µs|||| |td(rst)<br>reset delay time|-<br>-<br>4<br>µs|||| [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region SCL’s falling edge. [4] The maximum tf f 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [5] Cb = total capacitance of one bus line in pF. [6] © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **17 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **==> picture [386 x 179] intentionally omitted <==** **----- Start of picture text -----**<br> START bit 7 STOP<br>protocol condition MSB bit 6 bit 0 acknowledge condition<br>(A6) (R/W) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH 1/fSCL<br>SCL<br>tBUF tf<br>tr<br>SDA<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab175<br>Rise and fall times refer to VIL and VIH.<br>**----- End of picture text -----**<br> **==> picture [131 x 11] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 21. I [2] C-bus timing diagram<br>**----- End of picture text -----**<br> © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **18 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **14. Package outline** ## **SO24: plastic small outline package; 24 leads; body width 7.5 mm** ## **SOT137-1** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 A<br>A1 (A )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 12 detail X<br>e w M<br>b p<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>0.3 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9<br>mm 2.65 0.1 2.25 0.25 0.36 0.23 15.2 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o<br>0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0o<br>inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004<br>0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016<br>Note<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT137-1 075E05 MS-013<br>03-02-19<br>**----- End of picture text -----**<br> **Fig 22. Package outline SOT137-1 (SO24)** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **19 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm** ## **SOT340-1** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 A1 (A )3 A<br>pin 1 index<br>θ<br>L p<br>L<br>1 12 detail X<br>w M<br>e bp<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>mm 2 0.210.05 1.801.65 0.25 0.380.25 0.200.09 8.48.0 5.45.2 0.65 7.97.6 1.25 1.030.63 0.90.7 0.2 0.13 0.1 0.80.4 80oo<br>Note<br>1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT340-1 MO-150<br>03-02-19<br>**----- End of picture text -----**<br> **Fig 23. Package outline SOT340-1 (SSOP24)** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **20 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 mm** **SOT556-1** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>A2 A<br>A1 (A )3<br>θ<br>L p<br>L<br>1 12 detail X<br>e w M<br>bp<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)<br>A<br>UNIT max. A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp v w y Z [(1)] θ<br>0.25 1.55 0.31 0.25 8.8 4.0 6.2 0.89 1.05 8o<br>mm 1.73 0.10 1.40 0.25 0.20 0.18 8.6 3.8 0.635 5.8 1 0.41 0.25 0.18 0.1 0.66 0o<br>0.0098 0.061 0.012 0.0098 0.344 0.157 0.244 0.035 0.040 8o<br>inches 0.068 0.0040 0.055 0.01 0.008 0.0075 0.337 0.150 0.025 0.228 0.041 0.016 0.01 0.007 0.004 0.026 0o<br>Note<br>1. Plastic or metal protrusions of 0.2 mm (0.008 inch) maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT556-1 MO-137<br>03-02-18<br>**----- End of picture text -----**<br> **Fig 24. Package outline SOT556-1 (SSOP24)** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **21 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm** ## **SOT355-1** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 (A )3 A<br>pin 1 index A1<br>θ<br>L p<br>L<br>1 12<br>detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp Q v w y Z (1) θ<br>0.15 0.95 0.30 0.2 7.9 4.5 6.6 0.75 0.4 0.5 8o<br>mm 1.1 0.05 0.80 0.25 0.19 0.1 7.7 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.2 0 o<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT355-1 MO-153<br>03-02-19<br>**----- End of picture text -----**<br> **Fig 25. Package outline SOT355-1 (TSSOP24)** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **22 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT815-1<br>**----- End of picture text -----**<br> **==> picture [478 x 559] intentionally omitted <==** **----- Start of picture text -----**<br> D B A<br>A<br>E A1<br>c<br>detail X<br>terminal 1<br>index area<br>C<br>terminal 1 e1<br>index area e b v M C A B y1 C y<br>w M C<br>2 11<br>L<br>12<br>1<br>Eh e2<br>24<br>13<br>23 14<br>Dh X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.30 5.6 4.25 3.6 2.25 0.5<br>mm 1 0.2 0.5 4.5 1.5 0.1 0.05 0.05 0.1<br>0.00 0.18 5.4 3.95 3.4 1.95 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br> SOT815-1 - - - - - - - - - 03-04-29<br>**----- End of picture text -----**<br> **Fig 26. Package outline SOT815-1 (DHVQFN24)** PCA8575_2 © NXP B.V. 2007. All rights reserved. **Product data sheet** **Rev. 02 — 21 March 2007** **23 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT616-1<br>**----- End of picture text -----**<br> **==> picture [478 x 559] intentionally omitted <==** **----- Start of picture text -----**<br> D B A<br>terminal 1<br>index area<br>A<br>A1<br>E c<br>detail X<br>e1 C<br>1/2 e<br>e b v M C A B y1 C y<br>7 12 w M C<br>L<br>13<br>6<br>e<br>Eh e2<br>1/2 e<br>1<br>18<br>terminal 1<br>index area 24 19<br>Dh X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.30 4.1 2.25 4.1 2.25 0.5<br>mm 1 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1<br>0.00 0.18 3.9 1.95 3.9 1.95 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>01-08-08<br> SOT616-1 - - - MO-220 - - -<br>02-10-22<br>**----- End of picture text -----**<br> **Fig 27. Package outline SOT616-1 (HVQFN24)** PCA8575_2 © NXP B.V. 2007. All rights reserved. **Product data sheet** **Rev. 02 — 21 March 2007** **24 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **15. Handling information** Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. ## **16. Soldering** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. ## **16.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **16.2** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. - - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus PbSn soldering ## **16.3 Wave soldering** Key characteristics in wave soldering are: © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **25 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** - transport, the solder wave parameters, and the time during which components are exposed to the wave - ## **16.4** - higher minimum peak temperatures (see Figure 28) than a PbSn process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 7 and 8 **Table 7. SnPb eutectic process (from J-STD-020C)** |**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|≥**350**| |< 2.5|235<br>220|| |≥2.5|220<br>220|| ## **Table 8. Lead-free process (from J-STD-020C)** |**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260<br>260<br>260||| |1.6 to 2.5|260<br>250<br>245||| |> 2.5|250<br>245<br>245||| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. soldering, see Figure 28. © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **26 of 30** **PCA8575** **NXP Semiconductors** ## **Remote 16-bit I/O expander for I[2] C-bus with interrupt** **==> picture [320 x 208] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>**----- End of picture text -----**<br> **Fig 28.** “Surface mount reflow soldering description”. ## **17. Abbreviations** **Table 9. Abbreviations** |**Acronym**|**Description**| |---|---| |CDM|Charged Device Model| |CMOS|Complementary Metal Oxide Semiconductor| |ESD|ElectroStatic Discharge| |GPIO|General Purpose Input/Output| |HBM|Human Body Model| |I/O|Input/Output| |I2C-bus|Inter-Integrated Circuit bus| |IC|Integrated Circuit| |ID|Identifcation| |LED|Light Emitting Diode| |LSB|Least Signifcant Bit| |MM|Machine Model| |MSB|Most Signifcant Bit| |PLC|Programmable Logic Controller| |RAID|Redundant Array of Independent Disks| |SMBus|System Management Bus| © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **27 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **18. Revision history** ## **Table 10. Revision history** |**Document ID**|**Release date**<br>**Data sheet status**|**Release date**<br>**Data sheet status**|**Release date**<br>**Data sheet status**|**Change notice**|**Supersedes**| |---|---|---|---|---|---| |PCA8575_2|20070321<br>Product data sheet|||-|PCA8575_1| |Modifcations:|**•**|T<br>ab<br>le 5“Static char<br>acter<br>istics”,sub-section “I/Os; P00 to P07 and P10 to P17”:|||| |||**–**|IOL(Typ) for VDD= 2.3 V changed from <tbd> to 28 mA||| |||**–**|IOL(Typ) for VDD= 3.0 V changed from <tbd> to 35 mA||| |||**–**|IOL(Typ) for VDD= 4.5 V changed from <tbd> to 42 mA||| |||**–**|IOH(Typ) changed from <tbd> to−102µA||| |||**–**|Symbol Ci, input capacitance changed to|Cio(off), off-state input/output capacitance;|| ||||changed Typ value from <tbd> to 9 pF||| |||**–**|removed Symbol Corow||| |PCA8575_1|20061130<br>Objective data sheet|||-|-| © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **28 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **19. Legal information** ## **19.1 Data sheet status** |**Document statu**|**s**<br>**[1]**<br>**[2]**<br>**Product status**<br>**[3]**<br>**Defnition**| |---|---| |Objective [short] data sheet<br>Development<br>This document contains data from the objective specifcation for product development.|| |Preliminary [short] data sheet<br>Qualifcation<br>This document contains data from the preliminary specifcation.|| |Product [short] data sheet<br>Production<br>This document contains the product specifcation.|| [1] Please consult the most recently issued document before initiating or completing a design. [2] [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **19.2** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. ## **19.3 Disclaimers** **General —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. **Limiting values —** the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. **Terms and conditions of sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. ## **19.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP B.V. ## **20. Contact information** For additional information, please visit: **http://www.nxp.com** **salesaddresses@nxp.com** © NXP B.V. 2007. All rights reserved. PCA8575_2 **Product data sheet** **Rev. 02 — 21 March 2007** **29 of 30** **PCA8575** **NXP Semiconductors** **Remote 16-bit I/O expander for I[2] C-bus with interrupt** ## **21. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**|**20**|**Contact information . . . . . . . . . . . . . . . . . . . . 29**| |---|---|---|---| |**2**|**Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1**|**21**|**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30**| |**3**|**Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1**||| |**4**|**Ordering information . . . . . . . . . . . . . . . . . . . . . 2**||| |**5**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2**||| |**6**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 3**||| |6.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3||| |6.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5||| |**7**|**Functional description . . . . . . . . . . . . . . . . . . . 6**||| |7.1|Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6||| |7.1.1|Address map. . . . . . . . . . . . . . . . . . . . . . . . . . . 6||| |**8**|**I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 7**||| |8.1|Quasi-bidirectional I/O architecture . . . . . . . . . 7||| |8.2|Writing to the port (Output mode). . . . . . . . . . . 7||| |8.3|Reading from a port (Input mode) . . . . . . . . . . 8||| |8.4|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11||| |8.5|Interrupt output (<br>INT) . . . . . . . . . . . . . . . . . . . 11||| |**9**|**Characteristics of the I2C-bus. . . . . . . . . . . . . 12**||| |9.1|Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12||| |9.1.1|START and STOP conditions . . . . . . . . . . . . . 12||| |9.2|System confguration . . . . . . . . . . . . . . . . . . . 12||| |9.3|Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13||| |**10**|**Application design-in information . . . . . . . . . 14**||| |10.1|Bidirectional I/O expander applications . . . . . 14||| |10.2|High current-drive load applications . . . . . . . . 14||| |10.3|Differences between the PCA8575 and the||| ||PCF8575. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15||| |**11**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15**||| |**12**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 16**||| |**13**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 17**||| |**14**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19**||| |**15**|**Handling information. . . . . . . . . . . . . . . . . . . . 25**||| |**16**|**Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25**||| |16.1<br>16.2|Introduction to soldering . . . . . . . . . . . . . . . . . 25<br>Wave and refow soldering . . . . . . . . . . . . . . . 25||| |16.3<br>16.4|Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25<br>Refow soldering . . . . . . . . . . . . . . . . . . . . . . . 26||| |**17**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27**||| |**18**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 28**||| |**19**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 29**||| |19.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29||| |19.2|Defnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29||| |19.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29||| |19.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29||| **==> picture [151 x 121] intentionally omitted <==** Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2007.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 21 March 2007 Document identifier: PCA8575_2**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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