PBSS4021SN,115
Bipolar Transistor Array, Dual NPN, 20 V, 7.5 A, 2.3 W, 300 hFE, SOIC
- Manufacturer: NEXPERIA
- Product type: Bipolar Junction Transistor Arrays - BJT
- No. of Pins: 8Pins
- DC Current Gain hFE: 300hFE
- Transistor Mounting: Surface Mount
- Transistor Polarity: Dual NPN
- DC Collector Current: 7.5A
- Power Dissipation Pd: 2.3W
- Power Dissipation NPN: 2.3W
- Transistor Case Style: SOIC
- Transition Frequency NPN: 115MHz
- Operating Temperature Max: 150°C
- DC Current Gain hFE Min NPN: 300hFE
- Continuous Collector Current NPN: 7.5A
- Collector Emitter Voltage Max NPN: 20V
- Collector Emitter Voltage V(br)ceo: 20V
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 0.353 € |
| Current stock | 10+ |
| Lead time | 30 days |
**==> picture [97 x 65] intentionally omitted <==** ## **PBSS4021SN** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor Rev. 2 — 11 October 2010 Product data sheet** ## **1. Product profile** ## **1.1 General description** NPN/NPN low VCEsat Breakthrough In Small Signal (BISS) transistor in a SOT96-1 (SO8) medium power Surface-Mounted Device (SMD) plastic package. ## **Table 1. Product overview** |**Type number**|**Package**|**Package**|**PNP/PNP**<br>**complement**|**NPN/PNP**<br>**complement**| |---|---|---|---|---| ||**NXP**|**Name**||| |PBSS4021SN|SOT96-1<br>SO8<br>PBSS4021SP<br>PBSS4021SPN|||| ## **1.2 Features and benefits** - Very low collector-emitter saturation voltage VCEsat - High collector current capability IC and ICM - High collector current gain (hFE) at high IC - High efficiency due to less heat generation - Smaller required Printed-Circuit Board (PCB) area than for conventional transistors ## **1.3 Applications** - Loadswitch - Battery-driven devices - Power management - Charging circuits - Power switches (e.g. motors, fans) ## **1.4 Quick reference data** ## **Table 2. Quick reference data** |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |VCEO|collector-emitter voltage|open base||-|-|20|V| |IC|collector current|||-|-|7.5|A| |ICM|peak collector current|single pulse;||-|-|15|A| |||tp≤1 ms|||||| |RCEsat|collector-emitter|IC= 5 A; IB= 0.5 A|[1]|-|25|35|mΩ| ||saturation resistance||||||| - [1] Pulse test: tp ≤ 300 μs; δ ≤ 0.02. **==> picture [172 x 101] intentionally omitted <==** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** ## **2. Pinning information** ## **Table 3. Pinning** |**Pin**|**Description**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Graphic**|**Graphic**|**symbol**|**symbol**|**symbol**|| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |1<br>2|emitter TR1<br>base TR1|8|||||||||5|||8|7|6|5|| |3|emitter TR2|||||||||||||||||| |4|base TR2|||||||||||||TR1||TR2||| |5|collector TR2|1|||||||||4|||1|2|3|4|| |6|collector TR2|||||||||||||||_006aaa966_||| |7|collector TR1|||||||||||||||||| |8|collector TR1|||||||||||||||||| ## **3. Ordering information** **Table 4. Ordering information** |**Type number**|**Package**|**Package**|**Package**| |---|---|---|---| ||**Name**|**Description**|**Version**| |PBSS4021SN|SO8<br>plastic small outline package; 8 leads; body width 3.9 mm SOT96-1||| ## **4. Marking** **Table 5. Marking codes** **Type number Marking code** PBSS4021SN 4021SN ## **5. Limiting values** **Table 6. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Min**<br>**Max**<br>**Unit**| |---|---| |**Per transistor**|| |VCBO<br>collector-base voltage<br>open emitter|-<br>20<br>V| |VCEO<br>collector-emitter voltage<br>open base|-<br>20<br>V| |VEBO<br>emitter-base voltage<br>open collector|-<br>5<br>V| |IC<br>collector current|-<br>7.5<br>A| |ICM<br>peak collector current<br>single pulse; tp≤1 ms|-<br>15<br>A| |IB<br>base current|-<br>1<br>A| |Ptot<br>total power dissipation<br>Tamb≤25°C|[1]<br>-<br>0.73<br>W<br>[2]<br>-<br>1<br>W<br>[3]<br>-<br>1.7<br>W| © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **2 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** **Table 6. Limiting values** _…continued_ _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Min**<br>**Max**<br>**Unit**| |---|---| |**Per device**|| |Ptot<br>total power dissipation<br>Tamb≤25°C|[1]<br>-<br>0.86<br>W| ||[2]<br>-<br>1.4<br>W| ||[3]<br>-<br>2.3<br>W| |Tj<br>junction temperature|-<br>150<br>°C| |Tamb<br>ambient temperature|−55<br>+150<br>°C| |Tstg<br>storage temperature|−65<br>+150<br>°C| - [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. - [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm[2] . - [3] Device mounted on a ceramic PCB, Al2O3, standard footprint. **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 006aac234<br>3.0<br>Ptot<br>(W) (1)<br>2.0<br>(2)<br>1.0 (3)<br>0.0<br>−75 −25 25 75 125 175<br>Tamb (°C)<br>**----- End of picture text -----**<br> - (1) Ceramic PCB, Al2O3, standard footprint - (2) FR4 PCB, mounting pad for collector 1 cm[2] - (3) FR4 PCB, standard footprint **Fig 1. Per device: Power derating curves** © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **3 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** ## **6. Thermal characteristics** |**Table 7.**<br>**Thermal characteristics**|| |---|---| |**Symbol**<br>**Parameter**<br>**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |**Per transistor**|| |Rth(j-a)<br>thermal resistance from<br>junction to ambient<br>in free air|[1]<br>-<br>-<br>170<br>K/W| ||[2]<br>-<br>-<br>125<br>K/W| ||[3]<br>-<br>-<br>75<br>K/W| |Rth(j-sp)<br>thermal resistance from<br>junction to solder point|-<br>-<br>40<br>K/W| |**Per device**|| |Rth(j-a)<br>thermal resistance from<br>junction to ambient<br>in free air|[1]<br>-<br>-<br>145<br>K/W| ||[2]<br>-<br>-<br>90<br>K/W| ||[3]<br>-<br>-<br>55<br>K/W| - [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. - [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm[2] . - [3] Device mounted on a ceramic PCB, Al2O3, standard footprint. **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 006aac235<br>10 [3]<br>Zth(j-a)<br>(K/W) duty cycle = 1<br>10 [2] 0.75<br>0.5<br>0.33<br>0.2<br>0.1<br>10 0.05<br>0.02<br>0.01<br>1<br>0<br>10 [−][1]<br>10 [−][5] 10 [−][4] 10 [−][3] 10 [−][2] 10 [−][1] 1 10 10 [2] 10 [3]<br>tp (s)<br>**----- End of picture text -----**<br> FR4 PCB, standard footprint **Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values** © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **4 of 15** **PBSS4021SN** **NXP Semiconductors** ## **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 006aac236<br>10 [3]<br>Zth(j-a)<br>(K/W)<br>duty cycle = 1<br>10 [2]<br>0.75<br>0.5<br>0.33<br>0.2<br>10 0.1<br>0.05<br>0.02<br>0.01<br>1<br>0<br>10 [−][1]<br>10 [−][5] 10 [−][4] 10 [−][3] 10 [−][2] 10 [−][1] 1 10 10 [2] 10 [3]<br>tp (s)<br>**----- End of picture text -----**<br> FR4 PCB, mounting pad for collector 1 cm[2] **Fig 3. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values** **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 006aac237<br>10 [2]<br>duty cycle = 1<br>0.75<br>Zth(j-a) 0.5<br>(K/W)<br>0.33<br>0.2<br>10<br>0.1<br>0.05<br>0.02<br>0.01<br>1<br>0<br>10 [−][1]<br>10 [−][5] 10 [−][4] 10 [−][3] 10 [−][2] 10 [−][1] 1 10 10 [2] 10 [3]<br>tp (s)<br>**----- End of picture text -----**<br> Ceramic PCB, Al2O3, standard footprint **Fig 4. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values** © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **5 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** ## **7. Characteristics** ## **Table 8. Characteristics** _Tamb = 25_ ° _C unless otherwise specified._ |**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---|---| |**Per transistor**||| |ICBO<br>collector-base<br>cut-off current|VCB= 20 V; IE= 0 A|-<br>-<br>100<br>nA| ||VCB= 20 V; IE= 0 A;<br>Tj= 150°C|-<br>-<br>50<br>μA| |ICES<br>collector-emitter<br>cut-off current|VCE= 16 V; VBE= 0 V|-<br>-<br>100<br>nA| |IEBO<br>emitter-base<br>cut-off current|VEB= 5 V; IC= 0 A|-<br>-<br>100<br>nA| |hFE<br>DC current gain|VCE= 2 V|[1]| ||IC= 500 mA|300<br>550<br>-| ||IC= 1 A|300<br>550<br>-| ||IC= 2 A|300<br>500<br>-| ||IC= 4 A|250<br>450<br>-| ||IC= 8 A|100<br>200<br>-| |VCEsat<br>collector-emitter<br>saturation voltage||[1]| ||IC= 1 A; IB= 50 mA|-<br>30<br>45<br>mV| ||IC= 1 A; IB= 10 mA|-<br>40<br>60<br>mV| ||IC= 2 A; IB= 40 mA|-<br>60<br>90<br>mV| ||IC= 4 A; IB= 200 mA|-<br>100<br>150<br>mV| ||IC= 4 A; IB= 40 mA|-<br>120<br>180<br>mV| ||IC= 7.5 A; IB= 375 mA|-<br>185<br>275<br>mV| |RCEsat<br>collector-emitter<br>saturation resistance|IC= 5 A; IB= 500 mA|[1]<br>-<br>25<br>35<br>mΩ| |VBEsat<br>base-emitter<br>saturation voltage||[1]| ||IC= 1 A; IB= 100 mA|-<br>0.87<br>1<br>V| ||IC= 4 A; IB= 400 mA|-<br>1.04<br>1.2<br>V| |VBEon<br>base-emitter<br>turn-on voltage|VCE= 2 V; IC= 2 A|[1]<br>-<br>0.76<br>0.85<br>V| |td<br>delay time|VCC= 12.5 V; IC= 1 A;<br>IBon= 0.05 A; IBoff=−0.05 A|-<br>40<br>-<br>ns| |tr<br>rise time||-<br>40<br>-<br>ns| |ton<br>turn-on time||-<br>80<br>-<br>ns| |ts<br>storage time||-<br>650<br>-<br>ns| |tf<br>fall time||-<br>75<br>-<br>ns| |toff<br>turn-off time||-<br>725<br>-<br>ns| |fT<br>transition frequency|VCE= 10 V; IC= 100 mA;<br>f = 100 MHz|-<br>115<br>-<br>MHz| |Cc<br>collector capacitance|VCB= 10 V; IE= ie= 0 A;<br>f = 1 MHz|-<br>85<br>-<br>pF| [1] Pulse test: tp ≤ 300 μs; δ ≤ 0.02. © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **6 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** **==> picture [497 x 581] intentionally omitted <==** **----- Start of picture text -----**<br> 006aac238 006aac239<br>800 16.0<br>IB (mA) = 70<br>(1)<br>hFE IC 63<br>(A) 56<br>49<br>600 12.0 42<br>(2)<br>35<br>28<br>21<br>400 8.0<br>14<br>(3)<br>200 4.0 7<br>0 0.0<br>10 [−][1] 1 10 10 [2] 10 [3] 10 [4] 10 [5] 0.0 1.0 2.0 3.0 4.0 5.0<br>IC (mA) VCE (V)<br>VCE = 2 V Tamb = 25 °C<br>(1) Tamb = 100 °C<br>(2) Tamb = 25 °C<br>(3) Tamb = −55 °C<br>Fig 5. DC current gain as a function of collector Fig 6. Collector current as a function of<br>current; typical values collector-emitter voltage; typical values<br>006aac240 006aac241<br>1.2 1.4<br>VBE VBEsat<br>(V) (V)<br>0.8 (1) 1.0<br>(1)<br>(2)<br>(2)<br>0.4 0.6<br>(3)<br>(3)<br>0.0 0.2<br>10 [−][1] 1 10 10 [2] 10 [3] 10 [4] 10 [5] 10 [−][1] 1 10 10 [2] 10 [3] 10 [4] 10 [5]<br>IC (mA) IC (mA)<br>VCE = 2 V IC/IB = 20<br>(1) Tamb = −55 °C (1) Tamb = −55 °C<br>(2) Tamb = 25 °C (2) Tamb = 25 °C<br>(3) Tamb = 100 °C (3) Tamb = 100 °C<br>Fig 7. Base-emitter voltage as a function of collector Fig 8. Base-emitter saturation voltage as a function<br>current; typical values of collector current; typical values<br>**----- End of picture text -----**<br> © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **7 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** **==> picture [233 x 499] intentionally omitted <==** **----- Start of picture text -----**<br> 006aac242<br>1<br>VCEsat<br>(V)<br>10 [−][1]<br>(2)<br>(3)<br>(1)<br>10 [−][2]<br>10 [−][3]<br>10 [−][1] 1 10 10 [2] 10 [3] 10 [4] 10 [5]<br>IC (mA)<br>IC/IB = 20<br>(1) Tamb = 100 °C<br>(2) Tamb = 25 °C<br>(3) Tamb = −55 °C<br>Fig 9. Collector-emitter saturation voltage as a<br>function of collector current; typical values<br>006aac244<br>10 [3]<br>RCEsat<br>(Ω)<br>10 [2]<br>10<br>1<br>10 [−][1] (1)<br>(2)<br>(3)<br>10 [−][2]<br>10 [−][1] 1 10 10 [2] 10 [3] 10 [4]<br>IC (mA)<br>IC/IB = 20<br>**----- End of picture text -----**<br> - **Fig 9. Collector-emitter saturation voltage as a function of collector current; typical values** - (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C - **Fig 11. Collector-emitter saturation resistance as a function of collector current; typical values** **==> picture [233 x 479] intentionally omitted <==** **----- Start of picture text -----**<br> 006aac243<br>1<br>VCEsat<br>(V)<br>10 [−][1]<br>(1)<br>10 [−][2]<br>(2)<br>(3)<br>10 [−][3]<br>10 [−][1] 1 10 10 [2] 10 [3] 10 [4] 10 [5]<br>IC (mA)<br>Tamb = 25 °C<br>(1) IC/IB = 100<br>(2) IC/IB = 50<br>(3) IC/IB = 10<br>Fig 10. Collector-emitter saturation voltage as a<br>function of collector current; typical values<br>006aac245<br>10 [3]<br>RCEsat<br>(Ω)<br>10 [2]<br>(1)<br>10<br>(2)<br>1<br>(3)<br>10 [−][1]<br>10 [−][2]<br>10 [−][1] 1 10 10 [2] 10 [3] 10 [4] 10 [5]<br>IC (mA)<br>**----- End of picture text -----**<br> - **Fig 10. Collector-emitter saturation voltage as a function of collector current; typical values** Tamb = 25 °C - (1) IC/IB = 100 - (2) IC/IB = 50 - (3) IC/IB = 10 **Fig 12. Collector-emitter saturation resistance as a function of collector current; typical values** © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **8 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** ## **8. Test information** **==> picture [397 x 504] intentionally omitted <==** **----- Start of picture text -----**<br> IB<br>90 % input pulse<br>(idealized waveform)<br>IBon (100 %)<br>10 %<br>IBoff<br>output pulse<br>IC (idealized waveform)<br>90 %<br>IC (100 %)<br>10 %<br>t<br>td tr ts tf<br>ton toff 006aaa003<br>Fig 13. BISS transistor switching time definition<br>VBB VCC<br>RB RC<br>(probe) Vo (probe)<br>oscilloscope oscilloscope<br>450 Ω 450 Ω<br>R2<br>VI DUT<br>R1<br>mlb826<br>VCC = 12.5 V; IC = 1 A; IBon = 0.05 A; IBoff = −0.05 A<br>Fig 14. Test circuit for switching times<br>**----- End of picture text -----**<br> © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **9 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** ## **9. Package outline** **==> picture [236 x 164] intentionally omitted <==** **----- Start of picture text -----**<br> 5.0<br>1.75<br>4.8<br>1.0<br>0.4<br>6.2 4.0<br>5.8 3.8<br>pin 1 index<br>0.49 0.25<br>1.27<br>0.36 0.19<br>Dimensions in mm 03-02-18<br>**----- End of picture text -----**<br> **Fig 15. Package outline SOT96-1 (SO8)** ## **10. Packing information** **Table 9. Packing methods** _The indicated -xxx are the last three digits of the 12NC ordering code.[[][1][]]_ |**Type number**<br>**Package**<br>**Description**|**Packing quantity**|**Packing quantity**| |---|---|---| ||**1000**|**2500**| |PBSS4021SN<br>SOT96-1<br>8 mm pitch, 12 mm tape and reel|-115<br>-118|| [1] For further information and the availability of packing methods, see Section 14. © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **10 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** ## **11. Soldering** **==> picture [397 x 524] intentionally omitted <==** **----- Start of picture text -----**<br> 5.50<br>0.60 (8×)<br>1.30<br>4.00 6.60 7.00<br>1.27 (6×)<br>solder lands<br>occupied area placement accuracy ± 0.25 Dimensions in mm sot096-1_fr<br>Fig 16. Reflow soldering footprint SOT96-1 (SO8)<br>1.20 (2×)<br>0.60 (6×) 0.3 (2×) enlarged solder land<br>1.30<br>4.00 6.60 7.00<br>1.27 (6×)<br>5.50<br>board direction<br>solder lands solder resist<br>occupied area placement accurracy ± 0.25 Dimensions in mm sot096-1_fw<br>Fig 17. Wave soldering footprint SOT96-1 (SO8)<br>**----- End of picture text -----**<br> © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **11 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** ## **12. Revision history** |**Table 10.**<br>**Revision**|**history**|||| |---|---|---|---|---| |**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |PBSS4021SN v.2|20101011|Product data sheet|-|PBSS4021SN v.1| |Modifications:|**•** Figure 1“<br>Per device: Power derating curves<br>”<br>:updated.|||| |||||| |PBSS4021SN v.1|20100714|Product data sheet|-|-| © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **12 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** ## **13. Legal information** ## **13.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **13.2 Definitions** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. 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In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Product data sheet Rev. 2 — 11 October 2010** **13 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** **Quick reference data —** The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. ## **13.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ## **14. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP B.V. 2010. All rights reserved. PBSS4021SN All information provided in this document is subject to legal disclaimers. **Rev. 2 — 11 October 2010** **Product data sheet** **14 of 15** **PBSS4021SN** **NXP Semiconductors** **20 V, 7.5 A NPN/NPN low VCEsat (BISS) transistor** ## **15. Contents** |**1**|**Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |1.1|General description . . . . . . . . . . . . . . . . . . . . . 1| |1.2|Features and benefits. . . . . . . . . . . . . . . . . . . . 1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1| |1.4|Quick reference data . . . . . . . . . . . . . . . . . . . . 1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 2**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 2**| |**4**|**Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2**| |**5**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2**| |**6**|**Thermal characteristics . . . . . . . . . . . . . . . . . . 4**| |**7**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6**| |**8**|**Test information. . . . . . . . . . . . . . . . . . . . . . . . . 9**| |**9**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10**| |**10**|**Packing information . . . . . . . . . . . . . . . . . . . . 10**| |**11**|**Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11**| |**12**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12**| |**13**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 13**| |13.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13| |13.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |13.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |13.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |**14**|**Contact information. . . . . . . . . . . . . . . . . . . . . 14**| |**15**|**Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2010.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 11 October 2010 Document identifier: PBSS4021SN**
Updated at February 9, 2023
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