NVTJD4001NT1G

## NTJD4001N, NVTJD4001N 

## MOSFET – Dual, N-Channel, Small Signal, SC-88 

## 30 V, 250 mA 

## **Features** 

- Low Gate Charge for Fast Switching 

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- Small Footprint − 30% Smaller than TSOP−6 

- ESD Protected Gate 

- AEC Q101 Qualified − NVTJD4001N 

- These Devices are Pb−Free and are RoHS Compliant 

## **Applications** 

~~ee~~ **V(BR)DSS RDS(on** ~~es~~ **) TYP ID Max** 1.0  @ 4.0 V 30 V 250 mA 1.5  @ 2.5 V ~~ES~~ 

- Low Side Load Switch 

- Li−Ion Battery Supplied Devices − Cell Phones, PDAs, DSC 

**SOT−363 SC−88 (6 LEADS)** 

- Buck Converters 

- Level Shifts 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise stated) 

**==> picture [277 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
a Parameter Symbol Value Units<br>Drain−to−Source Voltage VDSS 30 V<br>a<br>Gate−to−Source Voltage VGS ± 20 V<br>a<br>Continuous Drain  Steady TA = 25  ° C ID 250 mA<br>Current (Note 1) State TA = 85  ° C 180<br>a<br>Power Dissipation Steady TA = 25  ° C PD 272 mW<br>(Note 1) State<br>FT [ET] ee ee<br>Pulsed Drain Current t =10 s IDM 600 mA<br>a Operating Junction and Storage Temperature TJ, TSTG −55 to ° C<br>150<br>ee eee<br>Source Current (Body Diode) IS 250 mA<br>a<br>Lead Temperature for Soldering Purposes TL 260 ° C<br>(1/8” from case for 10 s)<br>ee ee<br>**----- End of picture text -----**<br>


**THERMAL RESISTANCE RATINGS** (Note 1) 

~~a~~ **Parameter Symbol Value Unit** Junction−to−Ambient − Steady State R JA 458 ° C/W ~~eea~~ Junction−to−Lead − Steady State R ~~ee~~ JL 252 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Surface mounted on FR4 board using min pad size (Cu area = 0.155 in sq [1 oz] including traces). 

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S1 1 6 D1<br>G1 2 5 G2<br>D2 3 4 S2<br>Top View<br>**----- End of picture text -----**<br>


**==> picture [157 x 161] intentionally omitted <==**

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MARKING DIAGRAM &<br>PIN ASSIGNMENT<br>D1 G2 S2<br>PF<br>6<br>1<br>AL TE TE M<br>SOT−363<br>CASE 419B a<br>STYLE 26<br>1<br>S1 TOT G1 D2<br>TE = Device Code<br>M = Date Code<br>= Pb−Free Package<br>(Note: Microdot may be in either location)<br>|<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

|**Device**|**Package**|**Shipping**†|
|---|---|---|
|NTJD4001NT1G|SOT−363<br>(Pb−Free)|3000 / Tape &<br>Reel|
|NVTJD4001NT1G|SOT−363<br>(Pb−Free)|3000 / Tape &<br>Reel|



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2015 **May, 2019− Rev. 7** 

**NTJD4001N/D** 

## **NTJD4001N, NVTJD4001N** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise stated) 

|**ELECTRICAL CHARACTERISTIC**|**S**(TJ= 25°C u|nless otherwise stated)|nless otherwise stated)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= 100�A||30|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ||||56||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V, VDS= 30 V||||1.0|�A|
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=±10 V||||±1.0|�A|
|**ON CHARACTERISTICS**(Note 2)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 100�A||0.8|1.2|1.5|V|
|Gate Threshold Temperature<br>Coefficient|VGS(TH)/TJ||||−3.2||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 4.0 V, ID= 10 mA|||1.0|1.5|�|
|||VGS= 2.5 V, ID= 10 mA|||1.5|2.5||
|Forward Transconductance|gFS|VDS= 3.0 V, ID= 10 mA|||80||mS|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1.0 MHz,<br>VDS= 5.0 V|||20|33|pF|
|Output Capacitance|COSS||||19|32||
|Reverse Transfer Capacitance|CRSS||||7.25|12||
|Total Gate Charge|QG(TOT)|VGS= 5.0 V, VDS= 24 V,<br>ID= 0.1 A|||0.9|1.3|nC|
|Threshold Gate Charge|QG(TH)||||0.2|||
|Gate−to−Source Charge|QGS||||0.3|||
|Gate−to−Drain Charge|QGD||||0.2|||
|**SWITCHING CHARACTERISTICS**(Note 3)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDD= 5.0 V,<br>ID= 10 mA, RG= 50�|||17||ns|
|Rise Time|tr||||23|||
|Turn−Off Delay Time|td(OFF)||||94|||
|Fall Time|tf||||82|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 10 mA|TJ= 25°C||0.65|0.7|V|
||||TJ= 125°C||0.45|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 8.0 A/�s,<br>IS= 10 mA|||12.4||ns|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

2. Pulse Test: pulse width ≤ 300 � s, duty cycle ≤ 2%. 

3. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NTJD4001N, NVTJD4001N** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

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0.2 0.1<br>VGS = 10 V to 3 V TJ = 25 ° C<br>0.18 VDS = 5 V<br>VGS = 2.75 V<br>0.16 0.08<br>2.5 V<br>0.14 2.25 V<br>0.12 0.06<br>0.1 TJ = 125 ° C<br>0.08 0.04<br>0.06 2 V 25 ° C<br>0.04 0.02<br>0.02 1.75 V TJ = −55 ° C<br>1.5 V<br>0 0<br>0 0.4 0.8 1.2 1.6 2 1 1.2 1.4 1.6 1.8 2 2.2<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>1.25 1.25<br>VGS = 10 V TJ = 25 ° C<br>TJ = 125 ° C<br>1.0 1.0<br>VGS = 4.5 V<br>0.75 0.75<br>TJ = 25 ° C VGS = 10 V<br>0.5 TJ = −55 ° C 0.5<br>0.25 0.25<br>0.005 0.055 0.105 0.155 0.205 0.005 0.055 0.105 0.155 0.205<br>ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance vs. Drain Current and Figure 4. On−Resistance vs. Drain Current and<br>Temperature Gate Voltage<br>2 10000<br>1.8 ID = 0.01 A VGS = 0 V<br>VGS = 10 V<br>1.6<br>1.4<br>1000<br>1.2<br>1<br>TJ = 150 ° C<br>0.8<br>100<br>0.6<br>0.4<br>TJ = 125 ° C<br>0.2<br>0 10<br>−50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>DRAIN CURRENT (AMPS) DRAIN CURRENT (AMPS)<br>ID,  ID,<br>) � ) �<br>DRAIN−TO−SOURCE RESISTANCE ( DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),  DS(on),<br>R R<br>, LEAKAGE (nA)<br>DRAIN−TO−SOURCE<br>IDSS<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


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**3** 

**NTJD4001N, NVTJD4001N** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

**==> picture [490 x 621] intentionally omitted <==**

**----- Start of picture text -----**<br>
50 5<br>VDS = 0 V VGS = 0 V TJ = 25 ° C QG<br>40 Ciss 4<br>30 Crss 3<br>QGS QGD<br>20 Ciss 2<br>Coss<br>10 1<br>Crss ID = 0.1 A<br>TJ = 25 ° C<br>0 0<br>10 5 0 5 10 15 20 25 0 0.2 0.4 0.6 0.8 1<br>VGS VDS QG, TOTAL GATE CHARGE (nC)<br>GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 8. Gate−to−Source Voltage vs. Total<br>Figure 7. Capacitance Variation Gate Charge<br>0.1<br>VGS = 0 V<br>TJ = 25 ° C<br>0.08<br>0.06<br>0.04<br>0.02<br>0<br>0.5 0.55 0.6 0.65 0.7 0.75<br>VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>Figure 9. Diode Forward Voltage vs. Current<br>1000<br>D = 0.5<br>0.2<br>100<br>0.1<br>0.05<br>0.02<br>10<br>0.01<br>SINGLE PULSE<br>1<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME t,(s)<br>C, CAPACITANCE (pF)<br>GATE−TO−SOURCE VOLTAGE (VOLTS)<br>GS,<br>V<br>, SOURCE CURRENT (AMPS)<br>IS<br>r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE<br>**----- End of picture text -----**<br>


**Figure 10. Thermal Response** 

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**4** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y 

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1<br>SCALE 2:1 2X DATE 11 DEC 2012<br>aaa H D<br>- D H NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>A 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,<br>D GAGE PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-<br>PLANE SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.<br>4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF<br>6 5 4 THE PLASTIC BODY AND DATUM H.<br>L2 L 5. DATUMS A AND B ARE DETERMINED AT DATUM H.<br>E E1 DETAIL A 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THELEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.<br>7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.<br>1 2 3<br>ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN<br>EXCESS OF DIMENSION b AT MAXIMUM  MATERIAL CONDI-<br>2X aaa C TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER<br>bbb H D 2X 3 TIPS RADIUS OF THE FOOT.<br>e MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>B l= 6X b : A −−− −−− 1.10 −−− −−− 0.043<br>ddd M C A-B D A1 0.00 −−− 0.10 0.000 −−− 0.004<br>TOP VIEW A2 0.70 0.90 1.00 0.027 0.035 0.039<br>b 0.15 0.20 0.25 0.006 0.008 0.010<br>C 0.08 0.15 0.22 0.003 0.006 0.009<br>A2 DETAIL A D 1.80 2.00 2.20 0.070 0.078 0.086<br>A E 2.00 2.10 2.20 0.078 0.082 0.086<br>E1 1.15 1.25 1.35 0.045 0.049 0.053<br>e 0.65 BSC 0.026 BSC<br>L 0.26 0.36 0.46 0.010 0.014 0.018<br>L2 0.15 BSC 0.006 BSC<br>aaa 0.15 0.006<br>bbb 0.30 0.012<br>6X ccc C ccc 0.10 0.004<br>(tll, A1 C  A SEATINGPLANE Ma c === ddd 0.10 0.004<br>SIDE VIEW END VIEW GENERIC<br>MARKING DIAGRAM*<br>RECOMMENDED 6<br>SOLDERING FOOTPRINT*<br>6X 6X XXXM<br>0.30 0.66<br>1<br>Ta os 2.50 XXX = Specific Device Code<br>M = Date Code*<br>= Pb−Free Package<br>0.65 yo (Note: Microdot may be in either location)<br>PITCH<br>**----- End of picture text -----**<br>


## DATE 11 DEC 2012 

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 

   - *Date Code orientation and/or position may vary depending upon manufacturing location. 

**==> picture [83 x 5] intentionally omitted <==**

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DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may not follow the Generic Marking. 

## **STYLES ON PAGE 2** 

**DOCUMENT NUMBER: 98ASB42985B** 

**DESCRIPTION: SC−88/SC70−6/SOT−363** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

**PAGE 1 OF 2** 

ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

## **SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y 

## DATE 11 DEC 2012 

|STYLE 1:|STYLE 2:|STYLE 3:|STYLE 4:|STYLE 5:|STYLE 6:|
|---|---|---|---|---|---|
|PIN 1. EMITTER 2|CANCELLED|CANCELLED|PIN 1. CATHODE|PIN 1. ANODE|PIN 1. ANODE 2|
|2. BASE 2|||2. CATHODE|2. ANODE|2. N/C|
|3. COLLECTOR 1|||3. COLLECTOR|3. COLLECTOR|3. CATHODE 1|
|4. EMITTER 1|||4. EMITTER|4. EMITTER|4. ANODE 1|
|5. BASE 1|||5. BASE|5. BASE|5. N/C|
|6. COLLECTOR 2|||6. ANODE|6. CATHODE|6. CATHODE 2|
|STYLE 7:|STYLE 8:|STYLE 9:|STYLE 10:|STYLE 11:|STYLE 12:|
|PIN 1. SOURCE 2|CANCELLED|PIN 1. EMITTER 2|PIN 1. SOURCE 2|PIN 1. CATHODE 2|PIN 1. ANODE 2|
|2. DRAIN 2||2. EMITTER 1|2. SOURCE 1|2. CATHODE 2|2. ANODE 2|
|3. GATE 1||3. COLLECTOR 1|3. GATE 1|3. ANODE 1|3. CATHODE 1|
|4. SOURCE 1||4. BASE 1|4. DRAIN 1|4. CATHODE 1|4. ANODE 1|
|5. DRAIN 1||5. BASE 2|5. DRAIN 2|5. CATHODE 1|5. ANODE 1|
|6. GATE 2||6. COLLECTOR 2|6. GATE 2|6. ANODE 2|6. CATHODE 2|
|STYLE 13:|STYLE 14:|STYLE 15:|STYLE 16:|STYLE 17:|STYLE 18:|
|PIN 1. ANODE|PIN 1. VREF|PIN 1. ANODE 1|PIN 1. BASE 1|PIN 1. BASE 1|PIN 1. VIN1|
|2. N/C|2. GND|2. ANODE 2|2. EMITTER 2|2. EMITTER 1|2. VCC|
|3. COLLECTOR|3. GND|3. ANODE 3|3. COLLECTOR 2|3. COLLECTOR 2|3. VOUT2|
|4. EMITTER|4. IOUT|4. CATHODE 3|4. BASE 2|4. BASE 2|4. VIN2|
|5. BASE|5. VEN|5. CATHODE 2|5. EMITTER 1|5. EMITTER 2|5. GND|
|6. CATHODE|6. VCC|6. CATHODE 1|6. COLLECTOR 1|6. COLLECTOR 1|6. VOUT1|
|STYLE 19:|STYLE 20:|STYLE 21:|STYLE 22:|STYLE 23:|STYLE 24:|
|PIN 1. I OUT|PIN 1. COLLECTOR|PIN 1. ANODE 1|PIN 1. D1 (i)|PIN 1. Vn|PIN 1. CATHODE|
|2. GND|2. COLLECTOR|2. N/C|2. GND|2. CH1|2. ANODE|
|3. GND|3. BASE|3. ANODE 2|3. D2 (i)|3. Vp|3. CATHODE|
|4. V CC|4. EMITTER|4. CATHODE 2|4. D2 (c)|4. N/C|4. CATHODE|
|5. V EN|5. COLLECTOR|5. N/C|5. VBUS|5. CH2|5. CATHODE|
|6. V REF|6. COLLECTOR|6. CATHODE 1|6. D1 (c)|6. N/C|6. CATHODE|
|STYLE 25:|STYLE 26:|STYLE 27:|STYLE 28:|STYLE 29:|STYLE 30:|
|PIN 1. BASE 1|PIN 1. SOURCE 1|PIN 1. BASE 2|PIN 1. DRAIN|PIN 1. ANODE|PIN 1. SOURCE 1|
|2. CATHODE|2. GATE 1|2. BASE 1|2. DRAIN|2. ANODE|2. DRAIN 2|
|3. COLLECTOR 2|3. DRAIN 2|3. COLLECTOR 1|3. GATE|3. COLLECTOR|3. DRAIN 2|
|4. BASE 2|4. SOURCE 2|4. EMITTER 1|4. SOURCE|4. EMITTER|4. SOURCE 2|
|5. EMITTER|5. GATE 2|5. EMITTER 2|5. DRAIN|5. BASE/ANODE|5. GATE 1|
|6. COLLECTOR 1|6. DRAIN 1|6. COLLECTOR 2|6. DRAIN|6. CATHODE|6. DRAIN 1|



Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. 

|**DOCUMENT NUMBER:**|**98ASB42985B**|Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.|Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.|
|---|---|---|---|
|**DESCRIPTION:**|**SC−88/SC70−6/SOT−363**||**PAGE 2 OF 2**|



ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

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© Semiconductor Components Industries, LLC, 2019 

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