NVTFS5C673NLWFTAG

NVTFS5C673NL 

## Power MOSFET 

## **60 V, 9.8 m 50 A, Single N−Channel** 

## **Features** 

- Small Footprint (3.3 x 3.3 mm) for Compact Design 

- Low R to Minimize Conduction Losses DS(on) 

- Low Capacitance to Minimize Driver Losses 

**www.onsemi.com** 

- NVTFS5C673NLWF − Wettable Flanks Product 

- AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

**==> picture [190 x 48] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS RDS(on) MAX ID MAX<br>9.8 m  @ 10 V<br>60 V 50 A<br>15 m  @ 4.5 V<br>ie<br>**----- End of picture text -----**<br>


|**Parameter**<br>**Symbol**<br>**Value**<br>**Unit**<br>Drain−to−Source Voltage<br>VDSS<br>60<br>V<br>Gate−to−Source Voltage<br>VGS<br>±20<br>V<br>Continuous Drain Cur-<br>rent R JC<br>(Notes 1, 2, 3, 4)<br>Steady<br>State<br>TC= 25°C<br>ID<br>50<br>A<br>TC= 100°C<br>35<br>Power Dissipation<br>R JC(Notes 1, 2, 3)<br>TC= 25°C<br>PD<br>46<br>W<br>TC= 100°C<br>23<br>Continuous Drain Cur-<br>rent R JA<br>(Notes 1 & 3, 4)<br>Steady<br>State<br>TA= 25°C<br>ID<br>13<br>A<br>TA= 100°C<br>9<br>Power Dissipation<br>R JA(Notes 1, 3)<br>TA= 25°C<br>PD<br>3.1<br>W<br>TA= 100°C<br>1.6<br>Pulsed Drain Current<br>TA= 25°C, tp= 10 s<br>IDM<br>290<br>A<br>Operating Junction and Storage Temperature<br>TJ, Tstg<br>−55 to<br>+175<br>°C<br>Source Current (Body Diode)<br>IS<br>52<br>A<br>Single Pulse Drain−to−Source Avalanche<br>Energy (IL(pk)= 2.3 A)<br>EAS<br>88<br>mJ<br>Lead Temperature for Soldering Purposes<br>(1/8″from case for 10 s)<br>TL<br>260<br>°C<br>Stresses exceeding those listed in the Maximum Ratings table may damage the<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~re~~<br>~~po~~<br>~~pe~~<br>~~ee ee~~<br>~~pO~~<br>~~||~~<br>~~ee~~<br>~~pe~~<br>~~ee~~<br>~~ee~~<br>~~ee oe ee~~<br>~~ee ee ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee ee~~<br>~~ee eee~~|**WDFN8**<br>**( 8FL)**<br>**CASE 511AB**<br>**MARKING DIAGRAM**<br>(Note: Microdot may be in either location)<br>1<br>XXXX<br>= Specific Device Code<br>A<br>= Assembly Location<br>Y<br>= Year<br>WW<br>= Work Week<br>= Pb−Free Package<br>1<br>XXXX<br>AYWW<br>D<br>D<br>D<br>D<br>S<br>S<br>S<br>G<br>**N−Channel**<br>D (5 − 8)<br>S (1, 2, 3)<br>G (4)<br>~~ee~~<br>"<br>||
|---|---|
|device. If any of these limits are exceeded, device functionality should not be||
|assumed, damage may occur and reliability may be affected.|**ORDERING INFORMATION**|



## **THERMAL RESISTANCE MAXIMUM RATINGS** (Note 1) 

See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 

~~ee~~ **Parameter Symbol Value Unit** Junction−to−Case − Steady State (Note 3) R JC 3.2 ° C/W ~~eeEe~~ Junction−to−Ambient − Steady State (Note 3) R ~~ee~~ JA ~~ee~~ 48 ~~ee~~ 1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Psi ( wy ) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 

3. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

4. Continuous DC current rating. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: **NVTFS5C673NL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2017 **March, 2018 − Rev. 2** 

## **NVTFS5C673NL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|60|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||28||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 60 V|TJ= 25°C|||10|�A|
||||TJ= 125°C|||250||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA|
|**ON CHARACTERISTICS**(Note 5)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 35�A||1.2||2.0|V|
|Threshold Temperature Coefficient|VGS(TH)/TJ||||−4.5||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 25 A||8.1|9.8|m�|
|||VGS= 4.5 V|ID= 25 A||12|15||
|Forward Transconductance|gFS|VDS=15 V, ID= 25 A|||37||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 25 V|||880||pF|
|Output Capacitance|COSS||||450|||
|Reverse Transfer Capacitance|CRSS||||11|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 48 V; ID= 25 A|||4.5||nC|
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 48 V; ID= 25 A|||9.5||nC|
|Threshold Gate Charge|QG(TH)|VGS= 10 V, VDS= 48 V; ID= 25 A|||1.0||nC|
|Gate−to−Source Charge|QGS||||2.0|||
|Gate−to−Drain Charge|QGD||||0.8|||
|Plateau Voltage|VGP||||2.9||V|
|**SWITCHING CHARACTERISTICS**(Note 6)||||||||
|Turn−On Delay Time|td(ON)|VGS= 10 V, VDS= 48 V,<br>ID= 25 A, RG= 2.5�|||6.0||ns|
|Rise Time|tr||||25|||
|Turn−Off Delay Time|td(OFF)||||16|||
|Fall Time|tf||||2.0|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 25 A|TJ= 25°C||0.9|1.2|V|
||||TJ= 125°C||0.8|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIs/dt = 100 A/�s,<br>IS= 25 A|||28||ns|
|Charge Time|ta||||14|||
|Discharge Time|tb||||14|||
|Reverse Recovery Charge|QRR||||18||nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

6. Switching characteristics are independent of operating junction temperatures. 

**www.onsemi.com** 

**2** 

**NVTFS5C673NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [242 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
40<br>VGS = 3.6 V to 10 V<br>35<br>3.2 V<br>30<br>25 3.0 V<br>20<br>2.8 V<br>15<br>10 2.6 V<br>5 2.4 V<br>0<br>0 0.5 1.0 1.5 2.0 2.5<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**==> picture [150 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics** 

**==> picture [239 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
40<br>VDS = 3 V<br>35<br>30<br>25<br>20<br>15<br>TJ = 125 ° C<br>10 TJ = 25 ° C<br>5<br>0 TJ = −55 ° C<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0<br>VGS, GATE−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 2. Transfer Characteristics** 

**==> picture [490 x 423] intentionally omitted <==**

**----- Start of picture text -----**<br>
40 20<br>TJ = 25 ° C<br>35 TIDJ = 25= 25 A ° C 18<br>30 16<br>25 14<br>VGS = 4.5 V<br>20 12<br>15 10<br>VGS = 10 V<br>10 8<br>5 6<br>3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 70 80 90 100<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.25 100,000<br>2.00 VIDGS= 25 A = 10 V 10,000 T J  = 175 ° C<br>1.75 TJ = 125 ° C<br>1000<br>1.50<br>TJ = 85 ° C<br>1.25<br>100<br>1.00<br>10<br>0.75<br>0.50 1<br>−50 −25 0 25 50 75 100 125 150 175 10 20 30 40 50 60<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>IDSS<br>, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**www.onsemi.com** 

**3** 

**NVTFS5C673NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [243 x 592] intentionally omitted <==**

**----- Start of picture text -----**<br>
10,000<br>VGS = 0 V<br>TJ = 25 ° C<br>1000 Ciss f = 1 MHz<br>Coss<br>100<br>C rss<br>10<br>1<br>0 10 20 30 40 50 60<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 7. Capacitance Variation<br>100<br>tr<br>10 td(off)<br>td(on)<br>1 tf<br>VDS = 48 V<br>I D  = 25 A<br>V GS  = 10 V<br>0.1<br>1 10 100<br>RG, GATE RESISTANCE ( � )<br>Figure 9. Resistive Switching Time Variation<br>vs. Gate Resistance<br>1000<br>100<br>1 ms<br>10<br>500  � s<br>1 V GS ≤  10 V<br>Single Pulse<br>TC = 25 ° C 10 ms<br>0.1 RDS(on) Limit<br>Thermal Limit<br>Package Limit dc<br>0.01<br>0.1 1 10 100<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>C, CAPACITANCE (pF)<br>t, TIME (ns)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**==> picture [241 x 593] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>QT<br>9<br>8<br>7<br>6<br>5<br>4 Q gd<br>Qgs<br>3<br>2 T J = 25 ° C<br>VDS = 48 V<br>1 I D  = 25 A<br>0<br>0 1 2 3 4 5 6 7 8 9 10<br>Qg, TOTAL GATE CHARGE (nC)<br>Figure 8. Gate−to−Source vs. Total Charge<br>100<br>VGS = 0 V<br>10<br>1<br>TJ = 125 ° C TJ = 25 ° C TJ = −55 ° C<br>0.1<br>0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0<br>VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>Figure 10. Diode Forward Voltage vs. Current<br>100<br>10<br>TJ(initial) = 25 ° C<br>TJ(initial) = 100 ° C<br>1<br>0.1<br>1E−5 1E−4 1E−3 1E−2<br>TAV, TIME IN AVALANCHE (s)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>, SOURCE CURRENT (A)<br>IS<br>, DRAIN CURRENT (A)<br>IPEAK<br>**----- End of picture text -----**<br>


**Figure 12. Maximum Drain Current vs. Time in Avalanche** 

**www.onsemi.com** 

**4** 

**NVTFS5C673NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [491 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>Duty Cycle = 50%<br>20%<br>10<br>10%<br>5%<br>2%<br>1<br>1%<br>0.1<br>Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>C/W)<br>°<br>R(t) (<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Response** 

## **DEVICE ORDERING INFORMATION** 

|**Device**|**Marking**|**Package**|**Shipping**†|
|---|---|---|---|
|NVTFS5C673NLTAG|673L|WDFN8<br>(Pb−Free)|1500 / Tape & Reel|
|NVTFS5C673NLWFTAG|73LW|WDFN8<br>(Pb−Free, Wettable Flanks)|1500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

**www.onsemi.com** 

**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **WDFN8 3.3x3.3, 0.65P** 

**==> picture [31 x 26] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>**----- End of picture text -----**<br>


**==> picture [54 x 18] intentionally omitted <==**

**----- Start of picture text -----**<br>
CASE 511AB<br>ISSUE D<br>**----- End of picture text -----**<br>


## DATE 23 APR 2012 

**==> picture [42 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCALE 2:1<br>**----- End of picture text -----**<br>


**==> picture [274 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
2X<br>0.20 C<br>D A<br>D1 B 2X<br>8 7 6 5 0.20 C<br>4X<br>E1 E �<br>1 2 3 4 c A1<br>TOP VIEW<br>0.10 C<br>A 6X C<br>0.10 C e SEATING<br>PLANE<br>SIDE VIEW DETAIL A DETAIL A<br>**----- End of picture text -----**<br>


- NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 

3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 

|**DIM**|**MILLIMETERS**|**MILLIMETERS**|**MILLIMETERS**|**INCHES**|**INCHES**|**INCHES**|
|---|---|---|---|---|---|---|
||**MIN**|**NOM**|**MAX**|**MIN**|**NOM**|**MAX**|
|**A**|0.70|0.75|0.80|0.028|0.030|0.031|
|**A1**<br>**b**|0.00<br>023|−−−<br>030|0.05<br>040|0.000<br>0009|−−−<br>0012|0.002<br>0016|
|**c**|.<br>0.15|.<br>0.20|.<br>0.25|.<br>0.006|.<br>0.008|.<br>0.010|
|**D**<br>|3.30 BSC|||0.130 BSC|||
|**D1**<br>**D2**|2.95<br>1.98|3.05<br>2.11|3.15<br>2.24|0.116<br>0.078|0.120<br>0.083|0.124<br>0.088|
|**E**|3.30 BSC|||0.130 BSC|||
|**E1**|295|305|315|0116|0120|0124|
|**E2**|.<br>1.47|.<br>1.60|.<br>1.73|.<br>0.058|.<br>0.063|.<br>0.068|
|**E3**|0.23|0.30|0.40|0.009|0.012|0.016|
|**e**<br><br>|0.65 BSC<br><br><br><br><br><br>|||0.026 BSC<br><br><br><br><br><br>|||
|**G**<br>**K**|0.30<br>0.65|0.41<br>0.80|0.51<br>0.95|0.012<br>0.026|0.016<br>0.032|0.020<br>0.037|
|**L**|0.30|0.43|0.56|0.012|0.017|0.022|
|**L1**|006|013|020|0002|0005|0008|
|**M**<br>|1.40<br>.|1.50<br>.|1.60<br>.|0.055<br>.|0.059<br>.|0.063<br>.|
|**�**|0<br>�|−−−|12�|0<br>�|−−−|12�|



**==> picture [156 x 117] intentionally omitted <==**

**----- Start of picture text -----**<br>
8X b<br>0.10 C A B<br>0.05 C<br>4X L e/2<br>1 4<br>K<br>E2<br>E3 M<br>8 5<br>L1<br>G D2<br>BOTTOM VIEW<br>**----- End of picture text -----**<br>


## **SOLDERING FOOTPRINT*** 

**==> picture [179 x 144] intentionally omitted <==**

**----- Start of picture text -----**<br>
8X<br>0.42 0.65 4X<br>PITCH 0.66<br>PACKAGE<br>OUTLINE<br>3.60<br>2.30<br>0.75 0.57<br>0.47 2.37<br>3.46<br>DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>


## **GENERIC** 

## **MARKING DIAGRAM*** 

**==> picture [43 x 38] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>XXXXX<br>AYWW �<br>�<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

XXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week � = Pb−Free Package 

*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. 

**DOCUMENT NUMBER: 98AON30561E** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed **STATUS: ON SEMICONDUCTOR STANDARD** versions are uncontrolled except when stamped “CONTROLLED COPY” in red. ~~**NEW STANDARD: REF TO JEDEC MO−240**~~ © Semiconductor Components Industries, LLC, 2002 **http://onsemi.com** Case Outline Number: **October, 2002 − Rev. 0DESC IPTION: WDFN8 3.3X3.3, 0.65P 1 PAGE 1 OF 2XXX** 

|~~_— ©~~|~~_— ©~~|**DOCUMENT NUMBER:**<br>**98AON30561E**<br>**PAGE 2 OF 2**<br>~~——~~|**DOCUMENT NUMBER:**<br>**98AON30561E**<br>**PAGE 2 OF 2**<br>~~——~~|
|---|---|---|---|
|**ISSUE**|**REVISION**||**DATE**|
|O|RELEASED FOR PRODUCTION. REQ. BY B. MOSHER.||30 MAY 2008|
|A|ADDED GENERIC MARKING INFORMATION. REQ. BY B. MOSHER.||07 AUG 2008|
|B|CHANGED MAX DIMENSION “B” FROM 0.41MM TO 0.40MM. REQ. BY  NK THEN.||20 JAN 2009|
|C|ADDED DIMENSION E3. REQ. BY N. ZAINAL.||04 NOV 2011|
|D|CORRECTED DIMENSION K VALUES. REQ. BY D. TRUHITTE.||23 APR 2012|



> **ON Semiconductor** and          are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

Case Outline Number: **511AB** 

© Semiconductor Components Industries, LLC, 2012 **April, 2012 − Rev. D** 

ON Semiconductor and      are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

## **LITERATURE FULFILLMENT** : 

Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA **Phone** : 303−675−2175 or 800−344−3860 Toll Free USA/Canada **Fax** : 303−675−2176 or 800−344−3867 Toll Free USA/Canada **Email** : orderlit@onsemi.com 

**N. American Technical Support** : 800−282−9855 Toll Free **ON Semiconductor Website** : **www.onsemi.com** USA/Canada 

**Order Literature** : http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative 

**Europe, Middle East and Africa Technical Support:** Phone: 421 33 790 2910 

◊