NVTFS5124PLTAG

## NVTFS5124PL MOSFET – Power, Single P-Channel -60 V, -6 A, 260 m Q 

## P-Channel -60 V, -6 A, 260 m 

## **Features** 

- Small Footprint (3.3 x 3.3 mm) for Compact Design 

- Low R to Minimize Conduction Losses DS(on) 

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- Low QG and Capacitance to Minimize Driver Losses 

- NVTFS5124PLWF − Wettable Flanks Product 

- AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant 

|**V(BR)DSS**|**RDS(on) MAX**|**ID MAX**|
|---|---|---|
|−60 V|260 m @ −10 V|−6 A|
||380 m @ −4.5 V||



**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

||||~~ee~~|~~es~~||
|---|---|---|---|---|---|
|**Parameter**<br>~~es~~|||**Symbol**<br>~~es~~<br>~~ee~~<br>~~es~~|**Value**<br>~~es~~<br>~~es~~|**Unit**<br>~~es~~|
|Drain−to−Source Voltage<br>~~es~~|||VDSS<br>~~ee ~~<br>~~es~~<br>~~es~~<br>~~ee~~|−60<br> ~~es~~<br>~~es~~<br>~~es~~|V<br>~~es~~|
|Gate−to−Source Voltage<br>~~es~~|||VGS<br>~~es~~<br>~~es~~<br>~~ee~~|±20<br>~~es~~<br>~~es~~|V<br>~~es~~|
|Continuous Drain Cur-<br>rent R<br>J−mb(Notes 1,<br>2, 3, 4)|Steady<br>State<br>~~|~~|Tmb= 25°C<br>~~—~~|ID<br>~~ee~~<br>~~—~~|−6.0<br>~~es~~<br>~~—~~|A<br>~~—~~|
|||Tmb= 100°C<br>~~—~~<br>~~|~~||−4.0<br>~~—~~<br>~~||~~||
|Power Dissipation<br>R<br>J−mb(Notes 1, 2, 3)<br>~~|~~||Tmb= 25°C<br>~~—~~|PD<br>~~—~~<br>~~Ee;~~|18<br>~~—~~|W<br>~~—~~<br>~~|~~|
|||Tmb= 100°C<br>~~—~~<br>~~|~~<br>~~Ee;~~||9.0<br>~~—~~<br>~~|~~<br>~~|~~||
|Continuous Drain Cur-<br>rent R JA(Notes 1, 3,<br>4)<br>~~oo|~~<br>~~a~~|Steady<br>State<br>~~| ~~<br>~~ee~~<br>~~|~~|TA= 25°C<br>~~Ee;~~<br>~~|~~<br>|ID<br>~~Ee;~~<br>~~||~~<br>~~ee~~|−2.4<br>~~|~~<br>~~||~~<br>|A<br>~~|~~<br>~~ee~~|
|||TA= 100°C<br>~~Ee;~~<br>~~|~~<br>~~ee~~||−1.7<br>~~|~~<br>~~||~~<br>~~ee~~||
|Power Dissipation<br>R JA(Notes 1, 3)<br>~~|~~<br>~~a~~||TA= 25°C<br> ~~Ee;~~<br>~~|~~<br>~~ee~~|PD<br>~~Ee;~~<br>~~||~~<br>~~ee~~<br>~~Pe~~|3.0<br>~~|~~<br>~~||~~<br>~~ee~~|W<br>~~|~~<br>~~ee~~|
|||TA= 100°C<br>~~|~~<br>~~ee~~<br>~~|~~||1.5<br>~~||~~<br>~~ee~~<br>~~Pe~~||
|Pulsed Drain Current<br>~~a~~|TA= 25°C, tp= 10 s<br>~~|~~<br> ~~ee ee~~<br>~~|~~||IDM<br>~~||~~<br>~~ee~~<br>~~Pe~~|−24<br>~~||~~<br>~~ee~~<br>~~Pe~~|A<br>~~ee~~|
|Operating Junction and Storage Temperature|||TJ, Tstg<br>~~es~~|−55 to<br>+175<br>~~es~~|°C|
|Source Current (Body Diode)<br>~~es~~<br>~~TT~~|||IS<br>~~es~~<br>~~es~~<br>~~TT~~|−18<br>~~es~~<br>~~es~~<br>~~TT~~|A<br>~~es~~|
|Single Pulse Drain−to−Source Avalanche<br>Energy (TJ= 25°C, VDD= −50 V, VGS= −10 V,<br>IL(pk)= −13 A, L = 0.1 mH, RG= 25 )<br>~~ee~~<br>~~TT~~|||EAS<br>~~es ~~<br>~~ee~~<br>~~TT~~|8.5<br> ~~es~~<br>~~ee~~<br>~~TT~~|mJ<br>~~ee~~|
|Lead Temperature for Soldering Purposes<br>(1/8″from case for 10 s)<br>~~TT~~|||TL<br>~~TT~~|260<br>~~TT~~|°C|



## **P−Channel MOSFET** 

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D (5−8)<br>G (4)<br>S (1,2,3)<br>**----- End of picture text -----**<br>


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MARKING DIAGRAM<br>1<br>1 S D<br>@ WDFN8 S XXXX D<br>( 8FL) S AYWW D<br>CASE 511AB G D<br>" | i<br>XXXX = Specific Device Code<br>A = Assembly Location<br>Y = Year<br>WW = Work Week<br>= Pb−Free Package<br>(Note: Microdot may be in either location)<br>**----- End of picture text -----**<br>


## **MARKING DIAGRAM** 

## **ORDERING INFORMATION** 

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 

See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 

## **THERMAL RESISTANCE MAXIMUM RATINGS** (Note 1) 

~~ee~~ **Parameter Symbol** ~~ee~~ **Value** ~~ee~~ **Unit** Junction−to−Mounting Board (top) − Steady R J−mb 8.4 ° C/W State (Note 2 and 3) ~~eo~~ Junction−to−Ambient − Steady State (Note 3) R JA 49.2 ~~pa~~ 

1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Psi ( Ww ) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 

3. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

4. Continuous DC current rating. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: **NVTFS5124PL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2013 **August, 2019 − Rev. 2** 

## **NVTFS5124PL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTIC**|**S **(TJ= 25°C u|nless otherwise noted)|nless otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|−250�A|−60|||V|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= −60 V|TJ= 25°C|||−1.0|�A|
||||TJ= 125°C|||−10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=�20 V||||�100|nA|
|**ON CHARACTERISTICS**(Note 5)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= −250�A||−1.5||−2.5|V|
|Drain−to−Source On Resistance|RDS(on)|VGS= −10 V, ID= −3 A|||200|260|m�|
|||VGS= −4.5 V, ID= −3 A|||290|380||
|Forward Transconductance|gFS|VDS= −15 V, ID= −5 A||4|||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|Ciss|VGS = 0 V, f = 1.0 MHz,<br>VDS = −25 V|||250||pF|
|Output Capacitance|Coss||||27|||
|Reverse Transfer Capacitance|Crss||||17|||
|Total Gate Charge|QG(TOT)|VGS = −4.5 V, VDS = −48 V,<br>ID = −3 A|||3.5||nC|
|Threshold Gate Charge|QG(TH)||||0.4|||
|Gate−to−Source Charge|QGS||||1.2|||
|Gate−to−Drain Charge|QGD||||1.9|||
|Total Gate Charge|QG(TOT)|VGS = −10 V, VDS = −48 V,<br>ID = −3 A|||6|||
|**SWITCHING CHARACTERISTICS**(Note 6)||||||||
|Turn−On Delay Time|td(on)|VGS= −4.5 V, VDS= −48 V,<br>ID= −3 A, RG= 2.5�|||7||ns|
|Rise Time|tr||||14|||
|Turn−Off Delay Time|td(off)||||13|||
|Fall Time|tf||||10|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= −3 A|TJ= 25°C||−0.87|−1.0|V|
||||TJ= 125°C||−0.74|||
|Reverse Recovery Time|tRR|VGS= 0 V,<br>dIS/dt = 100 A/�s,<br>IS= −3 A|||17||ns|
|Charge Time|ta||||14|||
|Discharge Time|tb||||3|||
|Reverse Recovery Charge|QRR||||19||nC|



5. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 

6. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NVTFS5124PL** 

## **TYPICAL CHARACTERISTICS** 

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8 8<br>TJ = 25 ° C VDS ≥  −10 V<br>−4.5 V<br>−10 V<br>6 6<br>−4.0 V<br>4 4<br>−3.5 V<br>2 2 TJ = 25 ° C<br>VGS = −3 V<br>TJ = 125 ° C TJ = −55 ° C<br>0 0<br>0 1 2 3 4 5 1 2 3 4 5 6<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (V) −VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.50 0.50<br>ID = −3 A TJ = 25 ° C<br>T J  = 25 ° C<br>0.40 0.40<br>V GS  = −4.5 V<br>0.30 0.30<br>0.20 0.20 VGS = −10 V<br>0.10 0.10<br>2 4 6 8 10 2 4 6 8 10 12 14<br>−VGS, GATE−TO−SOURCE VOLTAGE (V) −ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>D D<br>−I −I<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>**----- End of picture text -----**<br>


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2.2 10000<br>2.0 VGS = −10 V VGS = 0 V<br>ID = −3 A<br>1.8<br>1.6 1000 TJ = 150 ° C<br>1.4<br>1.2<br>TJ = 125 ° C<br>1.0 100<br>0.8<br>0.6<br>0.4 10<br>−50 −25 0 25 50 75 100 125 150 175 10 20 30 40 50 60<br>TJ, JUNCTION TEMPERATURE ( ° C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>, LEAKAGE (nA)<br>, DRAIN−TO−SOURCE<br>DSS<br>−I<br>DS(on)<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


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**3** 

**NVTFS5124PL** 

## **TYPICAL CHARACTERISTICS** 

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10<br>VGS = 0 V QT<br>300 TJ = 25 ° C 8<br>Ciss<br>6<br>200<br>4 Qgs Qgd<br>100<br>2 VDS = −48 V<br>Coss ID = −3 A<br>0 Crss 0 TJ = 25 ° C<br>0 10 20 30 40 50 60 0 2 4 6<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)<br>Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total<br>Charge<br>1000.0 30<br>VIDDD = −3 A = −48 V VT JGS = = 0 V 25 ° C<br>VGS = −10 V<br>100.0 20<br>td(off)<br>10.0 tr 10<br>tf<br>td(on)<br>1.0 0<br>1 10 100 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3<br>RG, GATE RESISTANCE ( � ) −VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>(V)<br>C, CAPACITANCE (pF)<br>, GATE−TO−SOURCE VOLTAGE<br>GS<br>−V<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>S<br>−I<br>**----- End of picture text -----**<br>


**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** 

**Figure 11. Diode Forward Voltage vs. Current** 

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1000 10<br>VGS = −10 V ID = −13 A<br>Single Pulse<br>100 TC = 25 ° C 8<br>100  � s<br>1 ms<br>6<br>10 10 ms 10  � s<br>4<br>dc<br>1<br>RDS(on) Limit 2<br>Thermal Limit<br>Package Limit<br>0.1 0<br>0.1 1 10 100 25 50 75 100 125 150 175<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>, DRAIN CURRENT (A)<br>D<br>−I , SINGLE PULSE DRAIN−TO−<br>AS<br>E<br>SOURCE AVALANCHE ENERGY (mJ)<br>**----- End of picture text -----**<br>


**Figure 10. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature** 

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**4** 

**NVTFS5124PL** 

## **TYPICAL CHARACTERISTICS** 

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100<br>Duty Cycle = 0.5<br>0.2<br>10<br>0.1<br>0.05<br>0.02<br>1<br>0.01<br>Single Pulse<br>0.1<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>Figure 13. Thermal Response<br>C/W)<br>°<br> (<br>JA(t)<br>�<br>R<br>**----- End of picture text -----**<br>


## **DEVICE ORDERING INFORMATION** 

|**Device**|**Marking**|**Package**|**Shipping**†|
|---|---|---|---|
|NVTFS5124PLTAG|5124|WDFN8<br>(Pb−Free)|1500 / Tape & Reel|
|NVTFS5124PLWFTAG|24LW|WDFN8<br>(Pb−Free)|1500 / Tape & Reel|
|NVTFS5124PLTWG|5124|WDFN8<br>(Pb−Free)|5000 / Tape & Reel|
|NVTFS5124PLWFTWG|24LW|WDFN8<br>(Pb−Free)|5000 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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WDFN8 3.3x3.3, 0.65P<br>CASE 511AB<br>ISSUE D<br>**----- End of picture text -----**<br>


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DATE 23 APR 2012<br>**----- End of picture text -----**<br>


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SCALE 2:1<br>2X<br>0.20 C NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>o D S A 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH<br>D1 B 2X PROTRUSIONS OR GATE BURRS.<br>8 7 6 5 0.20 C DIM MINMILLIMETERSNOM MAX MIN INCHESNOM MAX<br>A 0.70 0.75 0.80 0.028 0.030 0.031<br>4X A1 0.00 −−− 0.05 0.000 −−− 0.002<br>E1 E b 0.23 0.30 0.40 0.009 0.012 0.016<br>c 0.15 0.20 0.25 0.006 0.008 0.010<br>D 3.30 BSC 0.130 BSC<br>1 2 3 4 c D1 2.95 3.05 3.15 0.116 0.120 0.124<br>me “Ap A1 —BSEEES D2 1.98 2.11 2.24 0.078 0.083 0.088<br>TOP VIEW E 3.30 BSC 0.130 BSC<br>E1 2.95 3.05 3.15 0.116 0.120 0.124<br>0.10 C E2 1.47 1.60 1.73 0.058 0.063 0.068<br>E3 0.23 0.30 0.40 0.009 0.012 0.016<br>ly es<br>0.10 C an? A Mh 6Xe , SEATINGPLANEC See GKe 0.300.65 0.65 BSC0.410.80 0.510.95 0.0120.026 0.026 BSC0.0160.032 0.0200.037<br>L 0.30 0.43 0.56 0.012 0.017 0.022<br>SIDE VIEW DETAIL A DETAIL A L1 0.06 0.13 0.20 0.002 0.005 0.008<br>M 1.40 1.50 1.60 0.055 0.059 0.063<br>0  −−− 12  0  −−− 12<br>8X b<br>0.10 C A B<br>SOLDERING FOOTPRINT*<br>0.05 C<br>8X<br>4X L e/2 0.42 0.65 4X<br>1 4 PITCH 0.66<br>PACKAGE<br>s o rain K OUTLINE wir<br>E2<br>E3 M<br>FT hal NrBEES1<br>8 5<br>L1 3.60<br>G D2<br>Fi BOTTOM VIEW 0.75 P| 0.57 2.30<br>:<br>GENERIC<br>MARKING DIAGRAM* 0.47 a 2.37 a<br>1 3.46<br>XXXXX DIMENSION: MILLIMETERS<br>AYWW<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>XXXXX = Specific Device Code Mounting Techniques Reference Manual, SOLDERRM/D.<br>A = Assembly Location<br>Y = Year<br>WW = Work Week<br>= Pb−Free Package<br>**----- End of picture text -----**<br>


*This information is generic. Please refer to device data sheet for actual part marking. 

Pb−Free indicator, “G” or microdot “ ”, may or may not be present. 

**DOCUMENT NUMBER: 98AON30561E DESCRIPTION: WDFN8 3.3X3.3, 0.65P** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

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