NVTFS5116PLWFTAG

## NVTFS5116PL Power MOSFET **−60 V, −14 A, 52 m** Q 

## **−60 V, −14 A, 52 m Single P−Channel** 

## **Features** 

- Small Footprint (3.3 x 3.3 mm) for Compact Design 

- Low R to Minimize Conduction Losses DS(on) 

- Low Capacitance to Minimize Driver Losses 

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- NVTFS5116PLWF − Wettable Flanks Product 

- AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

~~po~~ **Parameter Symbol Value Unit** Drain−to−Source Voltage VDSS −60 V ~~ee~~ Gate−to−Source Voltage V ~~es~~ GS ± 20 V ~~ee~~ Continuous Drain CurTmb = 25 ° C ID −14 A rent R2, 3, 4) J−mb[ (Notes 1,] Steady Tmb = 100 ° C −10 Power Dissipation State Tmb = 25 ° C ~~ee~~ PD 21 W R J−mb[ (Notes 1, 2, 3)] Tmb = 100 ° C 10 ~~=.=es=ee~~ Continuous Drain Cur- ~~a~~ TA = 25 ° C ~~s=eee~~ ID ~~ee~~ −6 A ~~eo~~ rent R3, 4) JA (Notes 1 & Steady TA = 100 ° C −4 Power Dissipation State ~~a~~ TA = 25 ° C ~~ee~~ PD ~~eee~~ 3.2 W R JA (Notes 1, 3) TA = 100 ° C 1.6 ~~ee~~ Pulsed Drain Current TA = 25 ° C, tp = 10 s IDM −126 A ~~po~~ Operating Junction and Storage Temperature ~~a~~ TJ ~~ee~~ , Tstg ~~ee~~ −55 to ° C +175 ~~**e**~~ Source Current (Body Diode) ~~e ee~~ IS −17 A Single Pulse Drain−to−Source Avalanche ~~eee~~ EAS ~~ee~~ 45 mJ Energy (TJ = 25 ° C, VDD = 50 V, VGS = 10 V, ~~re~~ IL(pk) = 30 A, L = 0.1 mH, RG = 25 ) Lead Temperature for Soldering Purposes TL 260 ° C (1/8 ″ from case for 10 s) ~~po~~ 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL RESISTANCE MAXIMUM RATINGS** (Note 1) 

**V(BR)DSS RDS(on) MAX ID MAX** 52 m @ −10 V −60 V −14 A 72 m @ −4.5 V ~~ef~~ 

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P−Channel MOSFET<br>D (5−8)<br>G (4)<br>= S (1,2,3)<br>MARKING DIAGRAM<br>1<br>2}<br>1 S D<br>WDFN8 S = XXXX D<br>( " 8FL) S AYWW D<br>CASE 511AB G D<br>:<br>XXXX = Specific Device Code<br>A = Assembly Location<br>Y = Year<br>WW = Work Week<br>= Pb−Free Package<br>ee<br>(Note: Microdot may be in either location)<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 

~~po~~ **Parameter Symbol Value Unit** Junction−to−Mounting Board (top) − Steady R J−mb 7.2 ° C/W State (Note 2 and 3) 1. ~~poee~~ Junction−to−Ambient − Steady State (Note 3)The entire application environment impacts the thermal resistance values shown, ~~ee~~ R JA 47 they are not constants and are only valid for the particular conditions noted. 

2. Psi ( wy ) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 

3. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

4. Continuous DC current rating. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: **NVTFS5116PL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2014 **June, 2014 − Rev. 3** 

## **NVTFS5116PL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTIC**|**S **(TJ= 25°C u|nless otherwise noted)|nless otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|−60|||V|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 60 V|TJ= 25°C|||−1.0|�A|
||||TJ= 125°C|||−10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=�20 V||||�100|nA|
|**ON CHARACTERISTICS**(Note 5)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= −250�A||−1||−3|V|
|Drain−to−Source On Resistance|RDS(on)|VGS= −10 V, ID= −7 A|||37|52|m�|
|||VGS= −4.5 V, ID= −7 A|||51|72||
|Forward Transconductance|gFS|VDS= 15 V, ID= −5 A|||11||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|Ciss|VGS= 0 V, f = 1.0 MHz,<br>VDS= −25 V|||1258||pF|
|Output Capacitance|Coss||||127|||
|Reverse Transfer Capacitance|Crss||||84|||
|Total Gate Charge|QG(TOT)|VGS = −4.5 V, VDS = −48 V,<br>ID = −7 A|||14||nC|
|Threshold Gate Charge|QG(TH)||||1||nC|
|Gate−to−Source Charge|QGS||||4|||
|Gate−to−Drain Charge|QGD||||8|||
|Total Gate Charge|QG(TOT)|VGS = −10 V, VDS = −48 V,<br>ID = −7 A|||25||nC|
|**SWITCHING CHARACTERISTICS**(Note 6)||||||||
|Turn−On Delay Time|td(on)|VGS= −4.5 V, VDS= −48 V,<br>ID= −7 A|||14||ns|
|Rise Time|tr||||68|||
|Turn−Off Delay Time|td(off)||||24|||
|Fall Time|tf||||36|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= −7 A|TJ= 25°C||−0.79|−1.20|V|
||||TJ= 125°C||−0.64|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt<br>IS= −7|= 100 A/�s,<br>A||21||ns|
|Charge Time|ta||||16|||
|Discharge Time|tb||||5|||
|Reverse Recovery Charge|QRR||||24||nC|



5. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 

6. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NVTFS5116PL** 

## **TYPICAL CHARACTERISTICS** 

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50 40<br>TJ = 25 ° C VGS = −7 V VDS ≥  −10 V<br>40 −5.0 V −4.6 V<br>−10 V 30<br>−4.3 V<br>30<br>−4 V 20<br>20<br>−3.7 V TJ = 25 ° C<br>10<br>10 −3.4 V<br>−3.1 V TJ = 125 ° C T J  = −55 ° C<br>−2.8 V<br>0 0<br>0 1 2 3 4 5 2 3 4 5 6<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (V) −VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.075 0.080<br>ID = −7 A<br>TJ = 25 ° C<br>0.070<br>0.065<br>VGS = −4.5 V<br>0.060<br>0.055<br>0.050<br>0.045 VGS = −10 V<br>0.040<br>0.035 0.030<br>3 4 5 6 7 8 9 10 5 10 15 20 25 30 35 40<br>−VGS, GATE−TO−SOURCE VOLTAGE (V) −ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.2 100000<br>2.0 ID = −7 A VGS = 0 V<br>VGS = −10 V<br>1.8<br>1.6 10000<br>1.4 TJ = 150 ° C<br>1.2<br>1.0 1000 TJ = 125 ° C<br>0.8<br>0.6<br>0.4 100<br>50 25 0 25 50 75 100 125 150 175 10 20 30 40 50 60<br>TJ, JUNCTION TEMPERATURE ( ° C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>D D<br>−I −I<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>, DRAIN−TO−SOURCE<br>DSS<br>−I<br>DS(on)<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


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**3** 

**NVTFS5116PL** 

## **TYPICAL CHARACTERISTICS** 

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1800 10<br>1600 VGS = 0 V QT<br>TJ = 25 ° C 8<br>1400 Ciss<br>1200<br>6<br>1000<br>800 4 Qgs Qgd<br>600<br>400 2 VDS = −48 V<br>ID = −7 A<br>200 Coss T J  = 25 ° C<br>0 Crss 0<br>0 10 20 30 40 50 60 0 5 10 15 20 25<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)<br>Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total<br>Charge<br>1000 40<br>VDD = −48 V VGS = 0 V<br>ID = −7 A T J  = 25 ° C<br>VGS = −4.5 V 30<br>100 tf tr<br>20<br>td(off)<br>10 td(on)<br>10<br>1.0 0<br>1 10 100 0.5 0.6 0.7 0.8 0.9 1.0<br>RG, GATE RESISTANCE ( � ) −VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current<br>vs. Gate Resistance<br>1000 45<br>VGS = −10 V ID = −30 A<br>100 Single PulseTC = 25 ° C 100  � s 10  � s<br>1 ms 30<br>10 10 ms<br>15<br>1<br>RDS(on) Limit<br>Thermal Limit dc<br>Package Limit<br>0.1 0<br>0.1 1 10 100 25 50 75 100 125 150 175<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs.<br>Safe Operating Area Starting Junction Temperature<br>(V)<br>C, CAPACITANCE (pF)<br>, GATE−TO−SOURCE VOLTAGE<br>GS<br>−V<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>S<br>−I<br>, DRAIN CURRENT (A)<br>D<br>−I , SINGLE PULSE DRAIN−TO−<br>AS<br>E<br>SOURCE AVALANCHE ENERGY (mJ)<br>**----- End of picture text -----**<br>


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**4** 

**NVTFS5116PL** 

## **TYPICAL CHARACTERISTICS** 

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100<br>Duty Cycle = 0.5<br>10 0.2<br>0.1<br>0.05<br>0.02<br>1<br>0.01<br>0.1<br>Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 100<br>PULSE TIME (sec)<br>Figure 13. Thermal Response<br>C/W)<br>°<br> (<br>JA(t)<br>�<br>R<br>**----- End of picture text -----**<br>


## **DEVICE ORDERING INFORMATION** 

|**Device**|**Marking**|**Package**|**Shipping**†|
|---|---|---|---|
|NVTFS5116PLTAG|5116|WDFN8<br>(Pb−Free)|1500 / Tape & Reel|
|NVTFS5116PLWFTAG|16LW|WDFN8<br>(Pb−Free)|1500 / Tape & Reel|
|NVTFS5116PLTWG|5116|WDFN8<br>(Pb−Free)|5000 / Tape & Reel|
|NVTFS5116PLWFTWG|16LW|WDFN8<br>(Pb−Free)|5000 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**5** 

**NVTFS5116PL** 

## **PACKAGE DIMENSIONS** 

**WDFN8 3.3x3.3, 0.65P** CASE 511AB ISSUE D 

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2X<br>S mal 0.20 C NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>D A 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH<br>LJ D1 au n B 2X PROTRUSIONS OR GATE BURRS.<br>8 7 6 5 0.20 C DIM MINMILLIMETERSNOM MAX MIN INCHESNOM MAX<br>A 0.70 0.75 0.80 0.028 0.030 0.031<br>4X A1 0.00 −−− 0.05 0.000 −−− 0.002<br>ane E1 E <= b 0.23 0.30 0.40 0.009 0.012 0.016<br>c 0.15 0.20 0.25 0.006 0.008 0.010<br>D 3.30 BSC 0.130 BSC<br>1 2 3 4 c D1 2.95 3.05 3.15 0.116 0.120 0.124<br>i A1 e======= D2 1.98 2.11 2.24 0.078 0.083 0.088<br>TOP VIEW E 3.30 BSC 0.130 BSC<br>E1 2.95 3.05 3.15 0.116 0.120 0.124<br>0.10 C E2 1.47 1.60 1.73 0.058 0.063 0.068<br>4 0 O R D === E3 0.23 0.30 0.40 0.009 0.012 0.016<br>i 0.10 C Re A <i 6Xe SEATINGPLANEC =2======= GKe 0.300.65 0.65 BSC0.410.80 0.510.95 0.0120.026 0.026 BSC0.0160.032 0.0200.037<br>L 0.30 0.43 0.56 0.012 0.017 0.022<br>SIDE VIEW DETAIL A DETAIL A L1 0.06 0.13 0.20 0.002 0.005 0.008<br>. SS M 1.40 1.50  SSS 1.60 0.055 0.059 0.063<br>0  −−− 12  0  −−− 12<br>8X b<br>0.10 C A B<br>SOLDERING FOOTPRINT*<br>0.05 C<br>8X<br>4X L e/2 0.42 0.65 4X<br>1 4 PITCH 0.66<br>PACKAGE<br>K OUTLINE<br>a E2 a at<br>E3 M<br>8 5<br>L1 3.60<br>G So D2 SEE<br>BOTTOM VIEW 0.75 0.57 2.30<br>el<br>0.47<br>2.37<br>3.46<br>DIMENSION: MILLIMETERS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


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**NVTFS5116PL/D** 

**6**