NVMFS5C670NLWFAFT1G

NVMFS5C670NL 

## Power MOSFET 

## **60 V, 6.1 m 71 A, Single N−Channel** 

## **Features** 

- Small Footprint (5x6 mm) for Compact Design 

- Low R to Minimize Conduction Losses DS(on) 

- Low QG and Capacitance to Minimize Driver Losses 

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- NVMFS5C670NLWF − Wettable Flank Option for Enhanced Optical Inspection 

- AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) ~~ee~~ **Parameter Symbol** ~~es~~ **Value** ~~ee~~ **Unit** Drain−to−Source Voltage VDSS 60 V ~~eeee Ge~~ Gate−to−Source Voltage VGS ± 20 V Continuous Drain TC = 25 ° C ID 71 A ~~EE~~ Current R(Notes 1, 3)JC Steady TC = 100 ° C 50 Power Dissipation State TC = 25 ° C PD 61 W R JC (Note 1) TC = 100 ° C 31 ~~——) FE~~ Continuous Drain TA = 25 ° C ID 17 A ~~2~~ Current R(Notes 1, 2, 3)JA Steady TA = 100 ° C 12 Power Dissipation State TA = 25 ° C PD 3.6 W R JA (Notes 1 & 2) TA = 100 ° C 1.8 ~~PEPer~~ Pulsed Drain Current TA = 25 ° C, tp = 10 s IDM 440 A ~~See~~ Operating Junction and Storage Temperature TJ, Tstg −55 to ° C + 175 ~~eeee ee~~ Source Current (Body Diode) IS 68 A Single Pulse Drain−to−Source Avalanche EAS 166 mJ ~~ee~~ Energy (IL(pk) = 3.6 A) ~~ee ee~~ Lead Temperature for Soldering Purposes TL 260 ° C (1/8 ″ from case for 10 s) ~~Pd~~ 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

~~ee~~ **Parameter** ~~Gs~~ **Symbol Value** ~~es~~ **Unit** Junction−to−Case − Steady State R JC 2.4 ° C/W Junction−to−Ambient − Steady State (Note 2) R JA 41 

1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

|**V(BR)DSS**|**RDS(ON) MAX**|**ID MAX**|
|---|---|---|
|60 V<br>~~oe~~|6.1 m @ 10 V<br>~~oe~~|71 A<br>~~oe~~|
||8.8 m @ 4.5 V<br>~~oe~~||



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D (5,6)<br>G (4)<br>re S (1,2,3)<br>N−CHANNEL MOSFET<br>MARKING<br>DIAGRAM<br>D<br>1<br>eee<br>S D<br>DFN5 S XXXXXX<br>(SO−8FL) S AYWZZ<br>CASE 488AA G D<br>STYLE 1 D<br>XXXXXX = 5C670L<br>XXXXXX = (NVMFS5C670NL) or<br>XXXXXX = 670LWF<br>XXXXXX = (NVMFS5C670NLWF)<br>A = Assembly Location<br>Y = Year<br>W = Work Week<br>ZZ = Lot Traceability<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

See detailed ordering, marking and shipping information on page 5 of this data sheet. 

2. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: **NVMFS5C670NL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2016 **February, 2017 − Rev. 2** 

## **NVMFS5C670NL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|60|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||27||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 60 V|TJ= 25°C|||10|�A|
||||TJ= 125°C|||250||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA|
|**ON CHARACTERISTICS**(Note 4)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 53�A||1.2||2.0|V|
|Threshold Temperature Coefficient|VGS(TH)/TJ||||−4.7||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 35 A||5.1|6.1|m�|
|||VGS= 4.5 V|ID= 35 A||7.0|8.8||
|Forward Transconductance|gFS|VDS= 15 V, ID= 35 A|||82||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 25 V|||1400||pF|
|Output Capacitance|COSS||||690|||
|Reverse Transfer Capacitance|CRSS||||15|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 48 V; ID= 35 A|||9.0||nC|
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 48 V; ID= 35 A|||20||nC|
|Threshold Gate Charge|QG(TH)|VGS= 10 V, VDS= 48 V; ID= 35 A|||2.5||nC|
|Gate−to−Source Charge|QGS||||4.5|||
|Gate−to−Drain Charge|QGD||||2.0|||
|Plateau Voltage|VGP||||3.1||V|
|**SWITCHING CHARACTERISTICS**(Note 5)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 48 V,<br>ID= 35 A, RG= 2.5�|||11||ns|
|Rise Time|tr||||60|||
|Turn−Off Delay Time|td(OFF)||||15|||
|Fall Time|tf||||4|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 35 A|TJ= 25°C||0.9|1.2|V|
||||TJ= 125°C||0.8|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt= 100 A/�s,<br>IS= 35 A|||34||ns|
|Charge Time|ta||||17|||
|Discharge Time|tb||||17|||
|Reverse Recovery Charge|QRR||||19||nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

4. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

5. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NVMFS5C670NL** 

## **TYPICAL CHARACTERISTICS** 

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140<br>6.5 V to 4.5 V<br>10 V<br>120<br>3.8 V<br>100<br>80<br>3.4 V<br>60<br>40 3.0 V<br>20<br>2.6 V<br>0<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics** 

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140<br>VDS = 5 V<br>120<br>100<br>80<br>60<br>TJ = 25 ° C<br>40<br>20<br>TJ = 125 ° C TJ = −55 ° C<br>0<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


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VGS, GATE−TO−SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 2. Transfer Characteristics** 

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15 10<br>14 T J  = 25 ° C TJ = 25 ° C<br>13 ID = 35 A 9<br>12<br>8<br>11 VGS = 4.5 V<br>10 7<br>9<br>6<br>8<br>7 VGS = 10 V<br>5<br>6<br>5 4<br>3.5 4.5 5.5 6.5 7.5 8.5 9.5 5 15 25 35 45 55 65 75<br>VGS, GATE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m<br>DS(on) DS(on)<br>R R<br>**----- End of picture text -----**<br>


**Figure 3. On−Resistance vs. Gate−to−Source Voltage** 

**Figure 4. On−Resistance vs. Drain Current and Gate Voltage** 

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100000<br>2.0 V GS  = 10 V TJ = 175 ° C<br>I D  = 35 A<br>1.8<br>10000<br>1.6<br>TJ = 125 ° C<br>1.4<br>1000<br>1.2 TJ = 85 ° C<br>1.0 100<br>0.8<br>0.6 10<br>−50 −25 0 25 50 75 100 125 150 175 10 20 30 40 50 60<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, LEAKAGE (nA)<br>, NORMALIZED DRAIN−TO− IDSS<br>SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**Figure 6. Drain−to−Source Leakage Current vs. Voltage** 

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**3** 

**NVMFS5C670NL** 

## **TYPICAL CHARACTERISTICS** 

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10000<br>CISS<br>1000<br>COSS<br>100<br>CRSS<br>10<br>VGS = 0 V<br>TJ = 25 ° C<br>f = 1 MHz<br>1<br>0 10 20 30 40 50 60<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

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10<br>9 QT<br>8<br>7<br>6<br>5<br>QGD<br>4<br>QGS<br>3<br>2 V DS  = 48 V<br>TJ = 25 ° C<br>1<br>I D  = 35 A<br>0<br>0 2 4 6 8 10 12 14 16 18 20<br>QG, TOTAL GATE CHARGE (nC)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge** 

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1000<br>TJ = 125 ° C<br>100<br>tr 10<br>td(on) TJ = 25 ° C<br>td(off) T J  = −55 ° C<br>10<br>VGS = 4.5 V<br>VDS = 48 V<br>tf I D  = 35 A<br>1 1<br>1 10 100 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0<br>RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current<br>vs. Gate Resistance<br>1000 100<br>TC = 25 ° C<br>VGS ≤  10 V<br>Single Pulse<br>100<br>10<br>500  � s TJ = 25 ° C<br>10 TJ = 100 ° C<br>10 ms 1<br>1<br>RDS(on) Limit 1 ms<br>Thermal Limit<br>Package Limit<br>0.1 0.1<br>0.1 1 10 100 1E−5 1E−4 1E−3 1E−2<br>VDS (V) TIME IN AVALANCHE (s)<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>IS<br>, DRAIN CURRENT (A)<br>, DRAIN CURRENT (A)<br>ID<br>IPEAK<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. Maximum Drain Current vs. Time in Avalanche** 

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**NVMFS5C670NL** 

## **TYPICAL CHARACTERISTICS** 

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100<br>50% Duty Cycle<br>10 20%<br>10%<br>5%<br>1 2%<br>1%<br>0.1<br>Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>Figure 13. Thermal Characteristics<br>DEVICE ORDERING INFORMATION<br>Device Marking Package Shipping [†]<br>NVMFS5C670NLT1G 5C670L DFN5 1500 / Tape & Reel<br>(Pb−Free)<br>NVMFS5C670NLWFT1G 670LWF DFN5 1500 / Tape & Reel<br>(Pb−Free, Wettable Flanks)<br>NVMFS5C670NLT3G 5C670L DFN5 5000 / Tape & Reel<br>(Pb−Free)<br>NVMFS5C670NLWFT3G 670LWF DFN5 5000 / Tape & Reel<br>(Pb−Free, Wettable Flanks)<br>NVMFS5C670NLAFT1G 5C670L DFN5 1500 / Tape & Reel<br>(Pb−Free)<br>NVMFS5C670NLWFAFT1G 670LWF DFN5 1500 / Tape & Reel<br>(Pb−Free, Wettable Flanks)<br>C/W)<br>°<br>R(t) (<br>**----- End of picture text -----**<br>


†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**5** 

**NVMFS5C670NL** 

## **PACKAGE DIMENSIONS** 

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DFN5 5x6, 1.27P<br>(SO−8FL)<br>2 X CASE 488AA NOTES:<br>ISSUE M 1. DIMENSIONING AND TOLERANCING PER<br>0.20 C ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>D < A a 3. DIMENSION D1 AND E1 DO NOT INCLUDE<br>MOLD FLASH PROTRUSIONS OR GATE<br>2 B 2 X BURRS.<br>D1 MILLIMETERS<br>0.20 C<br>DIM MIN NOM MAX<br>fet =—= A 0.90 1.00 1.10<br>A1 0.00 −−− 0.05<br>E1 4 X b 0.33 0.41 0.51<br>c 0.23 0.28 0.33<br>E D 5.00 5.15 5.30<br>2 D1 4.70 4.90 5.10<br>c D2 3.80 4.00 4.20<br>A1 E 6.00 6.15 6.30<br>E1 5.70 5.90 6.10<br>1 2 3 4 E2 3.45 3.65 3.85<br>e 1.27 BSC<br>TOP VIEW G 0.51 0.575 0.71<br>C K 1.20 1.35 1.50<br>SEATING L 0.51 0.575 0.71<br>0.10 C DETAIL A PLANE L1 0.125 REF<br>M 3.00 3.40 3.80<br>~. | A ——— 0  −−− 12<br>0.10 C RECOMMENDED STYLE 1:<br>SOLDERING FOOTPRINT* PIN 1. SOURCE<br>= SIDE VIEW DETAIL A 2X ==  2. 3. SOURCESOURCE<br>0.495 4.560  4. GATE<br>2X  5. DRAIN<br>8X b 1.530<br>0.10 C A B 1<br>e/2<br>0.05 c<br>L e<br>1 4 3.200<br>4.530<br>K<br>E2 2X 1.330<br>PIN 5 M 0.905<br>(EXPOSED PAD) L1 1<br>Etf o o 4 oe<br>0.965<br>G D2 4X<br>1.000 1.270<br>PO BOTTOM VIEW S E S 4X 888 0.750 PITCH<br>DIMENSIONS: MILLIMETERS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


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**NVMFS5C670NL/D/D** 

**6**