NVMFS5C645NLWFAFT1G

## NVMFS5C645NL Power MOSFET **60 V, 4.0 m 100 A, Single N−Channel** | 

## **Features** 

- Small Footprint (5x6 mm) for Compact Design 

- Low R to Minimize Conduction Losses DS(on) 

- Low QG and Capacitance to Minimize Driver Losses 

- NVMFS5C645NLWF − Wettable Flank Option for Enhanced Optical Inspection 

- AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant 

**www.onsemi.com** 

**V(BR)DSS RDS(ON) MAX ID MAX** 4.0 m @ 10 V 60 V 100 A 5.7 m @ 4.5 V ~~Fe~~ 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

**==> picture [480 x 282] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|es|Parameter|Symbol|Value|Unit|D (5)|
|Drain−to−Source Voltage|VDSS|60|V|
|Gate−to−Source Voltage|VGS|±|20|V|
|Continuous Drain|TC = 25|°|C|ID|100|A|
|po|Current R(Notes 1, 3)JC|Steady|||TC = 100|°|C|||71|G (4)|
|a|Power DissipationR|JC (Note 1)|State|TTCC = 100 = 25|°°|CC|Gs|PD|7940|W|N−CHANNEL MOSFET|re|S (1,2,3)|
|Continuous Drain|TA = 25|°|C|ID|22|A|
|Current R(Notes 1, 2, 3)JA|Steady|TA = 100|°|C|15|MARKING|
|Power Dissipation|State|TA = 25|°|C|PD|3.7|W|DIAGRAM|
|R|JA (Notes 1 & 2)|TA = 100|°|C|1.8|1|S|D|D|
|ep|Pulsed Drain Current|TA = 25|°|C, tp = 10 s|IDM|820|A|DFN5|S|5C645L|
|Operating Junction and Storage Temperature|TJ, Tstg|−55 to|°|C|CASE 488AA(SO−8FL)|GS|AYWZZ|D|
|+175|
|ee|STYLE 1|oe|D|
|Source Current (Body Diode)|IS|100|A|
|esGs|5C645L|= Specific Device Code|
|Single Pulse Drain−to−Source Avalanche|EAS|185|mJ|A|= Assembly Location|
|ee|Energy (IL(pk) = 5 A)|Y|= Year|
|Lead Temperature for Soldering Purposes|TL|260|°|C|W|= Work Week|
|(1/8|″|from case for 10 s)|ZZ|= Lot Traceability|
|eeee|eee|

**----- End of picture text -----**<br>


Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **ORDERING INFORMATION** 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

**==> picture [277 x 43] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|a|Parameter|Ge|Symbol|Value|Unit|
|Junction−to−Case − Steady State|R|JC|1.9|°|C/W|
|Junction−to−Ambient − Steady State (Note 2)|R|JA|41|

**----- End of picture text -----**<br>


See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 

1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: **NVMFS5C645NL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2016 **June, 2019 − Rev. 4** 

## **NVMFS5C645NL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|60|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||15.5||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 48 V|TJ= 25°C|||10|�A|
||||TJ= 125°C|||250||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA|
|**ON CHARACTERISTICS**(Note 4)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 80�A||1.2||2.0|V|
|Threshold Temperature Coefficient|VGS(TH)/TJ||||−4.9||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 50 A||3.3|4.0|m�|
|||VGS= 4.5 V|ID= 50 A||4.6|5.7||
|Forward Transconductance|gFS|VDS= 15 V, ID= 50 A|||105||S|
|**CHARGES, CAPACITANCES & GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 50 V|||2200||pF|
|Output Capacitance|COSS||||900|||
|Reverse Transfer Capacitance|CRSS||||17|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 30 V; ID= 50 A|||16||nC|
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 30 V; ID= 50 A|||34|||
|Threshold Gate Charge|QG(TH)|VGS= 4.5 V, VDS= 30 V; ID= 50 A|||1.5|||
|Gate−to−Source Charge|QGS||||5.6|||
|Gate−to−Drain Charge|QGD||||5.1|||
|Plateau Voltage|VGP||||2.8||V|
|**SWITCHING CHARACTERISTICS**(Note 5)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 30 V,<br>ID= 50 A, RG= 2.5�|||10||ns|
|Rise Time|tr||||15|||
|Turn−Off Delay Time|td(OFF)||||24|||
|Fall Time|tf||||5.0|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 50 A|TJ= 25°C||0.88|1.2|V|
||||TJ= 125°C||0.78|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 100 A/�s,<br>IS= 50 A|||41||ns|
|Charge Time|ta||||21|||
|Discharge Time|tb||||20|||
|Reverse Recovery Charge|QRR||||32||nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

5. Switching characteristics are independent of operating junction temperatures. 

**www.onsemi.com** 

**2** 

**NVMFS5C645NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [490 x 589] intentionally omitted <==**

**----- Start of picture text -----**<br>
140 10 V to 3.8 V 140 TJ = 125 ° C<br>4.5 V 3.6 V TJ = 25 ° C<br>120 120<br>TJ = −55 ° C<br>100 3.4 V 100<br>80 3.2 V 80<br>60 60<br>3.0 V<br>40 2.8 V 40<br>20 20<br>0 0<br>0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>10 8<br>9 TJ = 25 ° C TJ = 25 ° C<br>ID = 50 A 7<br>8<br>6<br>7<br>VGS = 4.5 V<br>5<br>6<br>4<br>5 VGS = 10 V<br>3<br>4<br>3 2<br>3 4 5 6 7 8 9 10 10 30 50 70 90 110 130 150<br>VGS, GATE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.5 100,000<br>2.0 VGS = 10 V TJ = 125 ° C<br>ID = 50 A 10,000<br>1.5 TJ = 85 ° C<br>1000<br>1.0<br>100<br>0.5<br>0 10<br>−50 −25 0 25 50 75 100 125 150 175 5 15 25 35 45 55<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>, NORMALIZED DRAIN−TO− IDSS<br>SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**==> picture [187 x 20] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6. Drain−to−Source Leakage Current<br>vs. Voltage<br>**----- End of picture text -----**<br>


**www.onsemi.com** 

**3** 

**NVMFS5C645NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [491 x 591] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 30<br>2400 CISS QT<br>25<br>8<br>2000<br>20<br>1600 VGS = 0 V 6<br>C OSS TJ = 25 ° C<br>f = 1 MHz 15<br>1200<br>4 QGS QGD<br>800 V DS  = 30 V 10<br>TJ = 25 ° C<br>400 2 I D  = 25 A 5<br>C RSS<br>0 0 0<br>0 10 20 30 40 50 60 0 4 8 12 16 20 24 28 32<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)<br>Figure 7. Capacitance Variation Figure 8. Gate−to−Source and<br>Drain−to−Source Voltage vs. Total Charge<br>1000<br>VGS = 4.5 V 45<br>100 VI DDD  = 25 A = 30 V t d(off) t f 4035 TJ = 125 ° C<br>tr 30<br>25 TJ = 25 ° C<br>td(on) 20<br>10 15 TJ = −55 ° C<br>10<br>5<br>1 0<br>1 10 100 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0<br>RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current<br>vs. Gate Resistance<br>1000 100<br>TC = 25 ° C<br>0.01 ms<br>VGS ≤  10 V<br>0.1 ms<br>100 10<br>TJ(initial) = 25 ° C<br>1 ms<br>TJ(initial) = 100 ° C<br>10 ms<br>10 1<br>RDS(on) Limit<br>Thermal Limit<br>Package Limit<br>1 0.1<br>0.1 1 10 100 1E−04 1E−03 1E−02<br>VDS (V) TIME IN AVALANCHE (s)<br>C, CAPACITANCE (pF)<br>, GATE−TO−SOURCE VOLTAGE (V) , DRAIN−TO−SOURCE VOLTAGE (V)<br>GS DS<br>V V<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>IS<br> (A)<br> (A)<br>IDS IPEAK<br>**----- End of picture text -----**<br>


**Figure 11. Safe Operating Area** 

**Figure 12. IPEAK vs. Time in Avalanche** 

**www.onsemi.com** 

**4** 

**NVMFS5C645NL** 

**==> picture [490 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>50% Duty Cycle<br>20%<br>10<br>10%<br>5%<br>2%<br>1 NVMFS5C646NL 650 mm [2] , 2 oz., Cu Single Layer Pad<br>1%<br>0.1<br>Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>C/W)<br>°<br>(t) (<br>JA<br>�<br>R<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Characteristics** 

## **DEVICE ORDERING INFORMATION** 

|**Device**|**Marking**|**Package**|**Shipping**†|
|---|---|---|---|
|NVMFS5C645NLT1G|5C645L|DFN5<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFS5C645NLWFT1G|645LWF|DFN5<br>(Pb−Free, Wettable Flanks)|1500 / Tape & Reel|
|NVMFS5C645NLT3G|5C645L|DFN5<br>(Pb−Free)|5000 / Tape & Reel|
|NVMFS5C645NLWFT3G|645LWF|DFN5<br>(Pb−Free, Wettable Flanks)|5000 / Tape & Reel|
|NVMFS5C645NLAFT1G|5C645L|DFN5<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFS5C645NLWFAFT1G|645LWF|DFN5<br>(Pb−Free, Wettable Flanks)|1500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

**www.onsemi.com** 

**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [482 x 619] intentionally omitted <==**

**----- Start of picture text -----**<br>
DFN5 5x6, 1.27P<br>(SO−8FL)<br>CASE 488AA<br>+<br>1 ISSUE N<br>SCALE 2:1 DATE 25 JUN 2018<br>2 X NOTES:<br>1. DIMENSIONING AND TOLERANCING PER<br>0.20 C ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>D = A o 3. DIMENSION D1 AND E1 DO NOT INCLUDE<br>MOLD FLASH PROTRUSIONS OR GATE<br>2 B 2 X BURRS.<br>D1 MILLIMETERS<br>0.20 C<br>DIM MIN NOM MAX<br>fet = A 0.90 1.00 1.10<br>A1 0.00 −−− 0.05<br>E1 4 X b 0.33 0.41 0.51<br>c 0.23 0.28 0.33<br>E D 5.00 5.15 5.30<br>2 D1 4.70 4.90 5.10<br>c D2 3.80 4.00 4.20<br>A1 E 6.00 6.15 6.30<br>E1 5.70 5.90 6.10<br>1 2 3 4 E2 3.45 3.65 3.85<br>e 1.27 BSC<br>TOP VIEW G 0.51 0.575 0.71<br>C K 1.20 1.35 1.50<br>SEATING L 0.51 0.575 0.71<br>0.10 C DETAIL A PLANE L1 0.125 REF<br>M 3.00 3.40 3.80<br>~. | A —— 0  −−− 12<br>0.10 C GENERIC<br>Sy SIDE VIEW SS MARKING DIAGRAM*<br>DETAIL A<br>1<br>8X b XXXXXX<br>0.10 C A B e/2 AYWZZ<br>0.05 c<br>L e<br>1 4 XXXXXX = Specific Device Code<br>P o {IF S<br>K A = Assembly Location<br>Y = Year<br>RECOMMENDED W = Work Week<br>E2 SOLDERING FOOTPRINT* ZZ = Lot Traceability<br>(EXPOSED PAD)PIN 5 L1 M 0.4952X 4.560 *This information is generic. Please refer to<br>2X device data sheet for actual part marking.<br>a<br>1.530 Pb−Free indicator, “G” or microdot “ ”,<br>G = D2 2X may not follow the Generic Marking.may or may not be present. Some products<br>BOTTOM VIEW 0.475<br>an 7a 3.200 |<br>4.530<br>| |<br>STYLE 1: STYLE 2: 2X 1.330<br>PIN 1. 2. SOURCESOURCE PIN 1. 2. ANODEANODE 0.905<br> 3. SOURCE  3. ANODE 1<br> 4. GATE  4. NO CONNECT<br> 5. DRAIN  5. CATHODE 0.965<br>“ 4X g o l a<br>1.000 1.270<br>4X 0.750 one PITCH<br>DIMENSIONS: MILLIMETERS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98AON14036D Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: DFN5 5x6, 1.27P (SO−8FL) PAGE 1 OF 1<br>**----- End of picture text -----**<br>


ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2018 

ON Semiconductor and      are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

**LITERATURE FULFILLMENT** : **TECHNICAL SUPPORT Email Requests to:** orderlit@onsemi.com **North American Technical Support:** Voice Mail: 1 800−282−9855 Toll Free USA/Canada **ON Semiconductor Website:** www.onsemi.com Phone: 011 421 33 790 2910 

◊ 

**www.onsemi.com** 

**Europe, Middle East and Africa Technical Support:** Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative 

**1**