NVMFD5C650NLWFT1G

## NVMFD5C650NL 

## MOSFET – Power, Dual 

## N-Channel 60 V, 4.2 m 111 A 

## **Features** 

- Small Footprint (5x6 mm) for Compact Design 

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- Low R to Minimize Conduction Losses DS(on) 

- Low QG and Capacitance to Minimize Driver Losses 

- NVMFD5C650NLWF − Wettable Flank Option for Enhanced Optical Inspection 

- AEC−Q101 Qualified and PPAP Capable 

|**V(BR)DSS**|**RDS(ON) MAX**|**ID MAX**|
|---|---|---|
|60 V|4.2 m @ 10 V<br>5.8 m @ 4.5 V|111 A|



- These Devices are Pb−Free and are RoHS Compliant 

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MAXIMUM RATINGS  (TJ = 25 ° C unless otherwise noted) Dual N−Channel<br>D1 D2<br>Parameter Symbol Value Unit<br>Drain−to−Source Voltage VDSS 60 V<br>Gate−to−Source Voltage VGS ± 20 V<br>Continuous Drain TC = 25 ° C ID 111 A G1 G2<br>Current R(Notes 1, 2, 3)JC Steady TC = 100 ° C 88<br>Power Dissipation State TC = 25 ° C PD 125 W S1 : S2<br>R JC (Notes 1, 2) TC = 100 ° C 62<br>Continuous Drain TA = 25 ° C ID 21 A MARKING<br>Current R(Notes 1, 2, 3)JA Steady TA = 100 ° C 15 DIAGRAM D1 D1<br>Power Dissipation State TA = 25 ° C PD 3.5 W S1 D1<br>R JA (Notes 1 & 2) TA = 100 ° C 1.8 DFN8 5x6 1 G1 XXXXXX D1<br>pe Pulsed Drain Current TA = 25 ° C, tp = 10 s IDM 502 A (SO8FL) G2S2 AYWZZ D2D2<br>CASE 506BT<br>Operating Junction and Storage Temperature TJ, Tstg −55 to ° C D2 D2<br>+ 175<br>A = Assembly Location<br>—— Source Current (Body Diode) IS 91 A Y = Year<br>Single Pulse Drain−to−Source Avalanche  EAS 186 mJ W = Work Week<br>Energy (TJ = 25 ° C, IL(pk) = 6 A) ZZ = Lot Traceability<br>Lead Temperature for Soldering Purposes TL 260 ° C<br>(1/8 ″  from case for 10 s)<br>Stresses exceeding those listed in the Maximum Ratings table may damage the<br>device. If any of these limits are exceeded, device functionality should not be ee oo ORDERING INFORMATION<br>assumed, damage may occur and reliability may be affected. See detailed ordering, marking and shipping information in the<br>**----- End of picture text -----**<br>


See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

|**Parameter**|**Symbol**|**Value**|**Unit**|
|---|---|---|---|
|Junction−to−Case − Steady State|R JC|1.37|°C/W|
|Junction−to−Ambient − SteadyState(Note 2)|R JA|46.9||



1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: **NVMFD5C650NL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2015 **July, 2019 − Rev. P3** 

## **NVMFD5C650NL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|60|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||27.1||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 60 V|TJ= 25°C|||10|�A|
||||TJ= 125°C|||100||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA|
|**ON CHARACTERISTICS**(Note 4)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 98�A||1.2||2.2|V|
|Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||−5.0||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 20 A||3.5|4.2|m�|
|||VGS= 4.5 V|ID= 20 A||4.6|5.8||
|Forward Transconductance|gFS|VDS= 15 V, ID= 50 A|||120||S|
|**CHARGES, CAPACITANCES & GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 25 V|||2546||pF|
|Output Capacitance|COSS||||1258|||
|Reverse Transfer Capacitance|CRSS||||17|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 48 V; ID= 50 A|||16||nC|
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 48 V; ID= 50 A|||37|||
|Threshold Gate Charge|QG(TH)|VGS= 4.5 V, VDS= 48 V; ID= 50 A|||4.3|||
|Gate−to−Source Charge|QGS||||8.3|||
|Gate−to−Drain Charge|QGD||||3.1|||
|Plateau Voltage|VGP||||3.3||V|
|**SWITCHING CHARACTERISTICS**(Note 5)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 48 V,<br>ID= 5 A, RG= 1.0�|||13||ns|
|Rise Time|tr||||24|||
|Turn−Off Delay Time|td(OFF)||||37|||
|Fall Time|tf||||13|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 20 A|TJ= 25°C||0.9|1.2|V|
||||TJ= 125°C||0.8|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 50 A/�s,<br>IS= 50 A|||44||ns|
|Charge Time|ta||||22|||
|Discharge Time|tb||||22|||
|Reverse Recovery Charge|QRR||||35||nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

5. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NVMFD5C650NL** 

## **TYPICAL CHARACTERISTICS** 

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140<br>10 to 4.5 V<br>3.6 V<br>120<br>3.4 V<br>100<br>80 3.2 V<br>60<br>3.0 V<br>40<br>2.8 V<br>20<br>VGS = 2.6 V<br>0<br>0 0.5 1.0 1.5 2.0 2.5<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


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140<br>VDS = 10 V<br>120<br>100<br>80<br>60<br>40 T J  = 25 ° C<br>20<br>0 TJ = 125 ° C TJ = −55 ° C<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0<br>VGS, GATE−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


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VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics** 

**Figure 2. Transfer Characteristics** 

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10 8<br>TJ = 25 ° C<br>9 TIDJ = 25 = 20 A ° C 7<br>8 6 VGS = 4.5 V<br>7 5<br>VGS = 10 V<br>6 4<br>5 3<br>4 2<br>3 4 5 6 7 8 9 10 10 20 30 40 50 60 70 80 90 100<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.0 100K<br>I D  = 20 A TJ = 175 ° C<br>1.8 VGS = 10 V 10K TJ = 150 ° C<br>1.6 TJ = 125 ° C<br>1K<br>1.4<br>TJ = 85 ° C<br>1.2<br>100<br>1.0 T J = 25 ° C<br>10<br>0.8<br>0.6 1<br>−50 −25 0 25 50 75 100 125 150 175 5 15 25 35 45 55<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>IDSS<br>, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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**3** 

**NVMFD5C650NL** 

## **TYPICAL CHARACTERISTICS** 

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10K 10<br>Ciss 9<br>8<br>1K<br>7<br>Coss 6<br>100 5 Q gd<br>4 Qgs<br>3<br>10 TJ = 25 ° C Crss 2 V DS = 48 V<br>VGS = 0 V ID = 50 A<br>f = 1 MHz 1 T J  = 25 ° C<br>1 0<br>0 10 20 30 40 50 60 0 5 10 15 20 25 30 35 40<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)<br>Figure 7. Capacitance Variation Figure 8. Gate−to−Source vs. Total Charge<br>1K<br>VGS = 4.5 V VGS = 0 V<br>VDS = 48 V<br>ID = 50 A td(off) 10<br>tf<br>100<br>tr<br>t d(on) 1<br>10<br>TJ = 125 ° C TJ = 25 ° C TJ = −55 ° C<br>1 0.1<br>1 10 100 0.3 0.4 0.5 0.6 0.7 0.8 0.9<br>RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current<br>vs. Gate Resistance<br>1000 100<br>100 TJ(initial) = 25 ° C<br>10<br>10 TC = 25 ° C TJ(initial) = 100 ° C<br>VGS ≤  10 V 10  � s<br>Single Pulse 1<br>1 0.5 ms<br>RDS(on) Limit 1 ms<br>Thermal Limit<br>10 ms<br>Package Limit<br>0.1 0.1<br>0.1 1 10 100 1000 0.00001 0.0001 0.001 0.01<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s)<br>C, CAPACITANCE (pF)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>IS<br> (A)<br>IPEAK<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. Maximum Drain Current vs. Time in Avalanche** 

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**4** 

**NVMFD5C650NL** 

## **TYPICAL CHARACTERISTICS** 

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100<br>50% Duty Cycle<br>10 20%<br>10%<br>5%<br>1 2%<br>1%<br>0.1<br>Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>Figure 13. Thermal Response<br>C/W)<br>°<br>R(t) (<br>**----- End of picture text -----**<br>


## **DEVICE ORDERING INFORMATION** 

|**Device**|**Marking**|**Package**|**Shipping**†|
|---|---|---|---|
|NVMFD5C650NLT1G|5C650L|DFN8<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFD5C650NLWFT1G|650LWF|DFN8<br>(Pb−Free, Wettable Flanks)|1500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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**DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)** CASE 506BT ISSUE F 

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DATE 23 NOV 2021<br>**----- End of picture text -----**<br>


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1 DATE 23 NOV 2021<br>SCALE 2:1 2X NOTES:<br>0.20 C 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>D A 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED<br>BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.<br>8 7 D16 5 B 2X 0.20 C 4.5. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELLAS THE TERMINALS.DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS.<br>6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED<br>AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST<br>POINT ON THE PACKAGE BODY.<br>7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.<br>PIN ONE E1 E MILLIMETERS<br>IDENTIFIER ÉÉ DIM MIN NOM MAX<br>NOTE 7 A 0.90 −−− 1.10<br>ÉÉ 4Xh A1b 0.33−−− 0.42−−− 0.050.51<br>ÉÉ 1 2 3 4 b1 0.33 0.42 0.51<br>c 0.20 −−− 0.33<br>TOP VIEW c A1 D 5.15 BSC<br>D1 4.70 4.90 5.10<br>0.10 C D2 3.90 4.10 4.30<br>A D3 1.50 1.70 1.90<br>DETAIL B E 6.15 BSC<br>0.10 C ALTERNATE E1 5.70 5.90 6.10<br>NOTE 4 SIDE VIEW C [SEATING] PLANE DETAIL A CONSTRUCTION E2e 3.90 1.27 BSC4.15 4.40<br>DETAIL A NOTE 6 G 0.45 0.55 0.65<br>h −−− −−− 12    �<br>D2 K 0.51 −−− −−−<br>D3 K1 0.56 −−− −−−<br>L 0.48 0.61 0.71<br>e 4X L M 3.25 3.50 3.75<br>1 4 K N 1.80 2.00 2.20<br>DETAIL B SOLDERING FOOTPRINT*<br>4.56<br>M N 4Xb1 E2 0.758X 2.082X 0.562X<br>8 5<br>4X G 8X b<br>K1 0.10 C A B 4X<br>4.84 1.40 6.59<br>BOTTOM VIEW 0.05 C NOTE 3 2.30<br>3.70<br>GENERIC<br>MARKING DIAGRAM*<br>0.70<br>1<br>XXXXXX<br>AYWZZ 4X 1.00 1.27<br>PITCH<br>5.55<br>XXXXXX = Specific Device Code DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>


7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. 

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1<br>XXXXXX<br>AYWZZ<br>XXXXXX = Specific Device Code<br>A = Assembly Location<br>Y = Year<br>W = Work Week<br>ZZ = Lot Traceability<br>**----- End of picture text -----**<br>


   - *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

## **DOCUMENT NUMBER: 98AON50417E** 

**DESCRIPTION: DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)** 

**PAGE 1 OF 1** 

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