NVMFD5C478NLWFT1G

**DATA SHEET www.onsemi.com** 

## MOSFET – Power, Dual N-Channel 40 V, 14.5 m **�** , 29 A 

|**V(BR)DSS**|**RDS(on) MAX**|**ID MAX**|
|---|---|---|
|40 V|14.5 m�@ 10 V<br>25 m�@ 4.5 V|29 A|



## NVMFD5C478NL 

## **Features** 

- Small Footprint (5 x 6 mm) for Compact Design 

- Low R to Minimize Conduction Losses DS(on) 

- Low Capacitance to Minimize Driver Losses 

- NVMFD5C478NLWF − Wettable Flanks Product 

- AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant 

## **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

|**MAXIMUM RATINGS**(TJ= 25°|**MAXIMUM RATINGS**(TJ= 25°|C unless otherw|ise noted)|||
|---|---|---|---|---|---|
|**Parameter**|||**Symbol**|**Value**|**Unit**|
|Drain−to−Source Voltage|||VDSS|40|V|
|Gate−to−Source Voltage|||VGS|±20|V|
|Continuous Drain<br>Current R�JC<br>(Notes 1, 2, 3, 4)|Steady<br>State|TC= 25°C|ID|29|A|
|||TC= 100°C||20.6||
|Power Dissipation<br>R�JC(Notes 1, 2, 3)||TC= 25°C|PD|23|W|
|||TC= 100°C||12||
|Continuous Drain<br>Current R�JA<br>(Notes 1 & 3, 4)|Steady<br>State|TA= 25°C|ID|10.5|A|
|||TA= 100°C||7.5||
|Power Dissipation<br>R�JA(Notes 1, 3)||TA= 25°C|PD|3.1|W|
|||TA= 100°C||1.5||
|Pulsed Drain Current|TA= 25°C, tp= 10�s||IDM|98|A|
|Operating Junction and Storage Temperature|||TJ, Tstg|−55 to<br>+175|°C|
|Source Current (Body Diode)|||IS|19|A|
|Single Pulse Drain−to−Source Avalanche<br>Energy (IL(pk)= 1.4 A)|||EAS|48|mJ|
|Lead Temperature for Soldering Purposes<br>(1/8″from case for 10 s)|||TL|260|°C|



**==> picture [192 x 193] intentionally omitted <==**

**----- Start of picture text -----**<br>
Dual−Channel<br>D1 D2<br>G1 G2<br>S1 S2<br>MARKING AND PIN<br>CONNECTION DIAGRAM<br>D1 D1<br>S1 D1<br>1 G1 XXXXXX D1<br>DFN8, 5x6 S2 AYWZZ D2<br>(S08FL) G2 D2<br>CASE 506BT D2 D2<br>**----- End of picture text -----**<br>


XXXXXX = 5C478L (NVMFD5C478NL) or 478LWF (NVMFD5C478NLWF) A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability 

## **ORDERING INFORMATION** 

See detailed ordering, marking and shipping information on page 5 of this data sheet. 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL RESISTANCE MAXIMUM RATINGS** (Note 1) 

|**Parameter**|**Symbol**|**Value**|**Unit**|
|---|---|---|---|
|Junction−to−Case − Steady State (Note 3)|R�JC|6.4|°C/W|
|Junction−to−Ambient − Steady State (Note 3)|R�JA|48.8||



1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Psi ( � ) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 

3. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

4. Continuous DC current rating. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: **NVMFD5C478NL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2017 **July, 2019 − Rev. 1** 

## **NVMFD5C478NL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTIC**|**S **(TJ= 25°C u|nless otherwise noted)|nless otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|40|||V|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 40 V|TJ= 25°C|||10|�A|
||||TJ= 125°C|||250||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA|
|**ON CHARACTERISTICS**(Note 5)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 20�A||1.2||2.2|V|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V, ID= 7.5 A|||12.1|14.5|m�|
|||VGS= 4.5 V, ID= 7.5 A|||20|25||
|Forward Transconductance|gFS|VDS= 15 V, ID= 15 A|||25||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|Ciss|VGS= 0 V, f = 1.0 MHz,<br>VDS= 25 V|||420||pF|
|Output Capacitance|Coss||||185|||
|Reverse Transfer Capacitance|Crss||||9|||
|Total Gate Charge|QG(TOT)|VGS = 10 V, VDS = 32 V, ID = 7.5 A|||8.1||nC|
|Threshold Gate Charge|QG(TH)||||1.0||nC|
|Gate−to−Source Charge|QGS||||1.7|||
|Gate−to−Drain Charge|QGD||||1.2|||
|Total Gate Charge|QG(TOT)|VGS = 4.5 V, VDS = 32 V, ID = 7.5 A|||3.9||nC|
|**SWITCHING CHARACTERISTICS**(Note 6)||||||||
|Turn−On Delay Time|td(on)|VGS= 10 V, VDS= 32 V,<br>ID= 7.5 A, RG= 1�|||6||ns|
|Rise Time|tr||||14|||
|Turn−Off Delay Time|td(off)||||18|||
|Fall Time|tf||||3.5|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 7.5 A|TJ= 25°C||0.84|1.2|V|
||||TJ= 125°C||0.72|||
|Reverse Recovery Time|tRR|VGS= 0 V, dlS/dt = 100 A/�s,<br>IS= 7.5 A|||17||ns|
|Charge Time|ta||||7.0|||
|Discharge Time|tb||||10|||
|Reverse Recovery Charge|QRR||||6||nC|



5. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 

6. Switching characteristics are independent of operating junction temperatures. 

**www.onsemi.com** 

**2** 

**NVMFD5C478NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [491 x 620] intentionally omitted <==**

**----- Start of picture text -----**<br>
40 40<br>6.0 V to 10 V VDS = 10 V<br>35 4.5 V 35<br>30 30<br>25 25<br>4.0 V<br>20 20<br>3.8 V<br>15 15<br>3.6 V<br>10 3.4 V 10 T J  = 25 ° C<br>5 5<br>TJ = 125 ° C TJ = −55 ° C<br>0 0<br>0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 1 2 3 4 5 6<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>50 30<br>45 T J = 25 ° C TJ = 25 ° C<br>40 ID = 5 A 25 V GS  = 4.5 V<br>35<br>20<br>30<br>25 15<br>VGS = 10 V<br>20<br>10<br>15<br>10<br>5<br>5<br>0 0<br>3 4 5 6 7 8 9 10 5 10 15 20 25 30<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>1.9 10K<br>VGS = 10 V<br>1.7 I D  = 7.5 A TJ = 150 ° C<br>1.5 1K TJ = 125 ° C<br>1.3<br>1.1 100 TJ = 85 ° C<br>0.9<br>0.7 10<br>−50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25 30 35 40<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>, NORMALIZED DRAIN−TO− IDSS<br>SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**www.onsemi.com** 

**3** 

**NVMFD5C478NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [241 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>CISS<br>100 COSS<br>10<br>CRSS<br>VGS = 0 V<br>T J = 25 ° C<br>f = 1 MHz<br>1<br>0 5 10 15 20 25 30 35 40<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

**==> picture [236 x 157] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>td(off)<br>tr<br>10<br>td(on)<br>t f<br>VGS = 10 V<br>VDS = 32 V<br>1<br>1 10<br>t, TIME (ns)<br>**----- End of picture text -----**<br>


**==> picture [104 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
RG, GATE RESISTANCE ( � )<br>**----- End of picture text -----**<br>


**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** 

**==> picture [242 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>TC = 25 ° C<br>VGS ≤  10 V<br>Single Pulse<br>100<br>10  � s<br>10<br>0.5 ms<br>1 1 ms<br>RDS(on) Limit<br>Thermal Limit 10 ms<br>Package Limit<br>0.1<br>0.1 1 10 100 1000<br>VDS, DRAIN−TO−SOURCE VOLTAGE(V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**==> picture [236 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>9<br>8<br>7<br>6<br>5<br>4 Q GS QGD<br>3<br>2 VDS = 32 V<br>ID = 7.5 A<br>1 T J  = 25 ° C<br>0<br>0 1 2 3 4 5 6 7 8 9<br>QG, TOTAL GATE CHARGE (nC)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 8. Gate−to−Source Voltage vs. Total Charge** 

**==> picture [239 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
8.2<br>VGS = 0 V<br>6.2<br>4.2<br>TJ = 125 ° C TJ = 25 ° C TJ = −55 ° C<br>2.2<br>0.2<br>0.5 0.6 0.7 0.8 0.9 1.0<br>, SOURCE CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**==> picture [151 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 10. Diode Forward Voltage vs. Current** 

**==> picture [239 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>10 TJ (initial) = 25 ° C<br>1 TJ (initial) = 100 ° C<br>0.1<br>0.00001 0.0001 0.001 0.01<br>TIME IN AVALANCHE (s)<br>, (A)<br>IPEAK<br>**----- End of picture text -----**<br>


**Figure 12. IPEAK vs. Time in Avalanche** 

**www.onsemi.com** 

**4** 

**NVMFD5C478NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [490 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>50% Duty Cycle<br>20%<br>10<br>10%<br>5%<br>2%<br>1<br>1%<br>0.1 Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>C/W)<br>°<br> (<br>JA<br>�<br>R<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Characteristics** 

## **DEVICE ORDERING INFORMATION** 

|**Device**|**Marking**|**Package**|**Shipping**†|
|---|---|---|---|
|NVMFD5C478NLT1G|5C478L|DFN8<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFD5C478NLWFT1G|478LWF|DFN8<br>(Pb−Free)|1500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

**www.onsemi.com** 

**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [51 x 34] intentionally omitted <==**

**DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)** CASE 506BT ISSUE F 

DATE 23 NOV 2021 

**==> picture [477 x 500] intentionally omitted <==**

**----- Start of picture text -----**<br>
1 DATE 23 NOV 2021<br>SCALE 2:1 2X NOTES:<br>0.20 C 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>D A 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED<br>BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.<br>8 7 D16 5 B 2X 0.20 C 4.5. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELLAS THE TERMINALS.DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS.<br>6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED<br>AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST<br>POINT ON THE PACKAGE BODY.<br>7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.<br>PIN ONE E1 E MILLIMETERS<br>IDENTIFIER<br>ÉÉ DIM MIN NOM MAX<br>NOTE 7 A 0.90 −−− 1.10<br>ÉÉ 4Xh A1b 0.33−−− 0.42−−− 0.050.51<br>1 2 3 4 b1 0.33 0.42 0.51<br>ÉÉ c 0.20 −−− 0.33<br>TOP VIEW c A1 D 5.15 BSC<br>D1 4.70 4.90 5.10<br>0.10 C D2 3.90 4.10 4.30<br>A D3 1.50 1.70 1.90<br>DETAIL B E 6.15 BSC<br>0.10 C ALTERNATE E1 5.70 5.90 6.10<br>NOTE 4 SIDE VIEW C [SEATING] PLANE DETAIL A CONSTRUCTION E2e 3.90 1.27 BSC4.15 4.40<br>DETAIL A NOTE 6 G 0.45 0.55 0.65<br>h −−− −−− 12    �<br>D2 K 0.51 −−− −−−<br>D3 K1 0.56 −−− −−−<br>L 0.48 0.61 0.71<br>e 4X L M 3.25 3.50 3.75<br>1 4 K N 1.80 2.00 2.20<br>DETAIL B SOLDERING FOOTPRINT*<br>4.56<br>M N 4Xb1 E2 0.758X 2.082X 0.562X<br>8 5<br>4X G 8X b<br>K1 0.10 C A B 4X<br>4.84 1.40 6.59<br>BOTTOM VIEW 0.05 C NOTE 3 2.30<br>3.70<br>GENERIC<br>MARKING DIAGRAM*<br>0.70<br>1<br>XXXXXX<br>AYWZZ 4X 1.00 1.27<br>PITCH<br>XXXXXX = Specific Device Code 5.55<br>A = Assembly Location DIMENSION: MILLIMETERS<br>Y = Year<br>*For additional information on our Pb−Free strategy and soldering<br>W = Work Week details, please download the  onsemi  Soldering and Mounting<br>ZZ = Lot Traceability Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. 

**==> picture [207 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.56<br>2X 2X<br>8X 2.082X 0.562X<br>0.758X<br>4X<br>4.84 1.40 6.59<br>2.30<br>3.70<br>0.70<br>4X 1.00 1.27<br>PITCH<br>5.55<br>DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>


   - *For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

## **DOCUMENT NUMBER: 98AON50417E** 

**DESCRIPTION: DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)** 

**PAGE 1 OF 1** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2011 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

**TECHNICAL PUBLICATIONS** : **ONLINE SUPPORT** : www.onsemi.com/support **Technical Library:** www.onsemi.com/design/resources/technical−documentation **For additional information, please contact your local Sales Representative at onsemi Website:** www.onsemi.com www.onsemi.com/support/sales 

**==> picture [232 x 43] intentionally omitted <==**

