NVMFD5C462NLT1G

## NVMFD5C462NL 

## Power MOSFET 

## **40 V, 4.7 m 84 A, Dual N−Channel** 

## **Features** 

- Small Footprint (5x6 mm) for Compact Design 

- Low R to Minimize Conduction Losses DS(on) 

- Low QG and Capacitance to Minimize Driver Losses 

## **www.onsemi.com** 

- NVMFD5C462NLWF − Wettable Flank Option for Enhanced Optical Inspection 

- AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant 

|**V(BR)DSS**|**RDS(ON) MAX**|**ID MAX**|
|---|---|---|
|40 V|4.7 m @ 10 V<br>7.7 m @ 4.5 V|84 A|



**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

> **Parameter** ~~_~~ **Symbol Value Unit** Drain−to−Source Voltage VDSS 40 V Gate−to−Source Voltage VGS ± 20 V Continuous Drain TC = 25 ° C ID 84 A Current R(Notes 1, 2, 3)JC Steady TC = 100 ° C 52 Power Dissipation State TC = 25 ° C PD 50 W R JC (Notes 1, 2) TC = 100 ° C 25 Continuous Drain TA = 25 ° C ID 18 A Current R(Notes 1, 2, 3)JA Steady TA = 100 ° C 15 Power Dissipation State TA = 25 ° C PD 3.0 W R JA (Notes 1 & 2) TA = 100 ° C 2.1 ~~F~~ ~~**e** r e~~ Pulsed Drain Current TA = 25 ° C, tp = 10 s ~~e~~ IDM 311 A Operating Junction and Storage Temperature TJ, Tstg −55 to ° C + 175 Source Current (Body Diode) IS 56 A ~~a~~ Single Pulse Drain−to−Source Avalanche EAS 174 mJ Energy (TJ = 25 ° C, IL(pk) = 5 A) Lead Temperature for Soldering Purposes TL 260 ° C (1/8 ″ from case for 10 s) ~~—F~~ Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ~~FE~~ 

## **THERMAL RESISTANCE MAXIMUM RATINGS** 

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Dual N−Channel<br>D1 D2<br>G1 G2<br>S1 S2<br>MARKING<br>DIAGRAM<br>D1 D1<br>S1 e ee D1<br>1<br>G1 XXXXXX D1<br>DFN8 5x6<br>S2 AYWZZ D2<br>(SO8FL)<br>G2 D2<br>CASE 506BT<br>D2 D2<br>A = Assembly Location<br>Y = Year<br>W = Work Week<br>ZZ = Lot Traceability<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

See detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. 

|**Parameter**|**Symbol**|**Value**|**Unit**|
|---|---|---|---|
|Junction−to−Case − Steady State|R JC|2.25|°C/W|
|Junction−to−Ambient − Steady State (Note 2)|R JA|47.3||



1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: **NVMFD5C462NL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2015 **August, 2017 − Rev. P3** 

## **NVMFD5C462NL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|40|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||29||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 40 V|TJ= 25°C|||10|�A|
||||TJ= 125°C|||100||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA|
|**ON CHARACTERISTICS**(Note 4)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 40�A||1.2||2.2|V|
|Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||−5.0||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 10 A||3.9|4.7|m�|
|||VGS= 4.5 V|ID= 10 A||6.4|7.7||
|Forward Transconductance|gFS|VDS= 15 V, ID= 10 A|||70||S|
|**CHARGES, CAPACITANCES & GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 25 V|||1300||pF|
|Output Capacitance|COSS||||530|||
|Reverse Transfer Capacitance|CRSS||||22|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 32 V; ID= 25 A|||11||nC|
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 32 V; ID= 25 A|||23|||
|Threshold Gate Charge|QG(TH)|VGS= 4.5 V, VDS= 32 V; ID= 10 A|||3.4|||
|Gate−to−Source Charge|QGS||||4.7|||
|Gate−to−Drain Charge|QGD||||3|||
|Plateau Voltage|VGP||||3.4||V|
|**SWITCHING CHARACTERISTICS**(Note 5)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 32 V,<br>ID= 5 A, RG= 1.0�|||11||ns|
|Rise Time|tr||||16|||
|Turn−Off Delay Time|td(OFF)||||19|||
|Fall Time|tf||||6|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 10 A|TJ= 25°C||0.86|1.2|V|
||||TJ= 125°C||0.75|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 25 A/�s,<br>IS= 5 A|||29||ns|
|Charge Time|ta||||14|||
|Discharge Time|tb||||14|||
|Reverse Recovery Charge|QRR||||12||nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

5. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NVMFD5C462NL** 

## **TYPICAL CHARACTERISTICS** 

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91<br>10 to 6.5 V 4.5 V<br>84<br>77 3.8 V<br>70<br>63<br>3.6 V<br>56<br>49<br>3.4 V<br>42<br>35<br>28 V GS = 3.2 V<br>21<br>14<br>7<br>0<br>0 0.5 1.0 1.5 2.0 2.5 3.0<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


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100<br>90 VDS = 10 V<br>80<br>70<br>60<br>50<br>40<br>30 TJ = 25 ° C<br>20<br>100 TJ = 125 ° C TJ = −55 ° C<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5<br>VGS, GATE−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics** 

**Figure 2. Transfer Characteristics** 

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50 9<br>45 I D  = 10 A TJ = 25 ° C<br>40 T J  = 25 ° C 8<br>35 VGS = 4.5 V<br>7<br>30<br>25 6<br>20<br>5<br>15<br>10 VGS = 10 V<br>4<br>5<br>0 3<br>3 4 5 6 7 8 9 10 5 10 15 20 25 30 35 40 45 50 55<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.1 100K<br>1.9 VIDGS = 10 A = 10 V 10K TTJJ = 150= 175 °° CC<br>1.7 1K TJ = 125 ° C<br>1.5 °<br>100 TJ = 85 C<br>1.3<br>10<br>1.1 TJ = 25 ° C<br>1<br>0.9<br>0.1<br>0.7<br>0.01<br>−50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25 30 35 40<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>IDSS<br>, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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**3** 

**NVMFD5C462NL** 

## **TYPICAL CHARACTERISTICS** 

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10K<br>C iss<br>1K<br>Coss<br>100<br>10 TJ = 25 ° C Crss<br>VGS = 0 V<br>f = 1 MHz<br>1<br>0 5 10 15 20 25 30 35 40<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 7. Capacitance Variation<br>100<br>td(off)<br>tr<br>10 td(on)<br>tf<br>V GS  = 4.5 V<br>VDS = 32 V<br>ID = 25 A<br>1<br>1 10 100<br>RG, GATE RESISTANCE ( � )<br>C, CAPACITANCE (pF)<br>t, TIME (ns)<br>**----- End of picture text -----**<br>


**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** 

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10<br>9<br>8<br>7<br>6<br>5<br>4 Q gs Q gd<br>3<br>2 V DS  = 32 V<br>ID = 25 A<br>1 T J  = 25 ° C<br>0<br>0 5 10 15 20 25<br>Qg, TOTAL GATE CHARGE (nC)<br>Figure 8. Gate−to−Source vs. Total Charge<br>10<br>V GS  = 0 V<br>TJ = 25 ° C<br>TJ = 125 ° C<br>1 TJ = −55 ° C<br>0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5<br>VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>, SOURCE CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 10. Diode Forward Voltage vs. Current** 

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1000 100<br>100<br>TJ(initial) = 25 ° C<br>10 TVCGS= 25 ≤  10 V ° C 10 TJ(initial) = 100 ° C<br>Single Pulse 10  � s<br>1<br>RDS(on) Limit 0.5 ms<br>Thermal Limit 1 ms<br>Package Limit 10 ms<br>0.1 1<br>0.1 1 10 100 1000 0.00001 0.0001 0.001 0.01<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) TIME IN AVALANCHE (s)<br> (A)<br>IPEAK<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. Maximum Drain Current vs. Time in Avalanche** 

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**4** 

**NVMFD5C462NL** 

## **TYPICAL CHARACTERISTICS** 

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100<br>50% Duty Cycle<br>10 20%<br>10%<br>5%<br>2%<br>1<br>1%<br>0.1<br>Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>C/W)<br>°<br>R(t) (<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Response** 

## **DEVICE ORDERING INFORMATION** 

|**Device**|**Marking**|**Package**|**Shipping**†|
|---|---|---|---|
|NVMFD5C462NLT1G|5C462L|DFN8<br>(Pb−Free)|1500 / Tape & Reel|
|NVMFD5C462NLWFT1G|462LWF|DFN8<br>(Pb−Free, Wettable Flanks)|1500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**5** 

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NVMFD5C462NL<br>PACKAGE DIMENSIONS<br>DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)<br>CASE 506BT<br>ISSUE E<br>2X<br>NOTES:<br>0.20 C 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>D A 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED<br>BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.<br>8 7 D16 5 B 2X 0.20 C 4.5. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELLAS THE TERMINALS.DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS.<br>6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED<br>AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST<br>POINT ON THE PACKAGE BODY.<br>o T pec 7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.<br>PIN ONE E1 E 4X MILLIMETERS<br>IDENTIFIER h DIM MIN MAX MAX<br>NOTE 7 ÉÉ A 0.90 −−− 1.10<br>A1 −−− −−− 0.05<br>ÉÉ c A1 b 0.33 0.42 0.51<br>1 2 3 4 b1 0.33 0.42 0.51<br>ON 4+, BEE c 0.20 −−− 0.33<br>TOP VIEW D 5.15 BSC<br>DETAIL B D1 4.70 4.90 5.10<br>0.10 C ALTERNATE D2 3.90 4.10 4.30<br>A DETAIL A CONSTRUCTION D3 1.50 1.70 1.90<br>E 6.15 BSC<br>0.10 C SOLDERING FOOTPRINT* E1 5.70 5.90 6.10<br>NOTE 4 SIDE VIEW C [SEATING] PLANE 4.56 E2e 3.90 1.27 BSC4.15 4.40<br>DETAIL A NOTE 6 G 0.45 0.55 0.65<br>D3D2 0.758X 2.082X 0.562X K1Kh 0.510.56−−− −−−−−−−−− 12 −−−−−−<br>L 0.48 0.61 0.71<br>e 4X L M 3.25 3.50 3.75<br>1 4 K N 1.80 2.00 2.20<br>4X<br>DETAIL B 4.84 1.40 6.59<br>2.30<br>! 4X i 3.70<br>N b1<br>M E2<br>O n 8 e) 5 e 0.70 e ]<br>4X G 8X b<br>K1 0.10 C A B<br>4X 1.00 1.27<br>BOTTOM VIEW 0.05 C NOTE 3 PITCH<br>5.55<br>a s l Pr jong |<br>DIMENSION: MILLIMETERS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>ON Semiconductor and      are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.<br>ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent<br>coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.<br>ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability<br>arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.<br>Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,<br>regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or<br>specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer<br>application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not<br>designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification<br>in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized<br>application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and<br>expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such<br>claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This<br>literature is subject to all applicable copyright laws and is not for resale in any manner.<br>**----- End of picture text -----**<br>


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## **LITERATURE FULFILLMENT** : 

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**NVMFD5C462NL/D**