NVMFD5877NLT1G

NVMFD5877NL 

## Power MOSFET **60 V, 39 m 17 A, Dual N−Channel, Logic Level, Dual SO8FL** 

## **Features** 

- Low R to Minimize Conduction Losses DS(on) 

- Low Capacitance to Minimize Driver Losses 

- NVMFD5877NLWF − Wettable Flanks Option for Enhanced Optical Inspection 

- AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free, Halogen Free and are RoHS Compliant 

**http://onsemi.com V(BR)DSS RDS(on) MAX ID MAX** ~~———_~~ 39 m @ 10 V 60 V 17 A 60 m @ 4.5 V 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

**Dual N−Channel** 

**Parameter Symbol Value Unit** Drain−to−Source Voltage VDSS 60 V D1 D2 Gate−to−Source Voltage VGS 20 V Continuous Drain CurTmb = 25 ° C ID 17 A rent R2, 3, 4) J−mb[ (Notes 1,] Steady Tmb = 100 ° C 12 G1 G2 Power Dissipation State Tmb = 25 ° C PD 23 W R J−mb[ (Notes 1, 2, 3)] Tmb = 100 ° C 12 S1 S2 ~~Ee -~~ Continuous Drain CurTA = 25 ° C ID 6 A **MARKING DIAGRAM** rent R3, 4) JA (Notes 1 & Steady TA = 100 ° C 5 D1 D1 Power Dissipation State TA = 25 ° C PD 3.2 W 1 G1S1 5877xx D1D1 R JA (Notes 1, 3) TA = 100 ° C 1.6 **DFN8 5x6** S2 AYWZZ D2 ~~ee~~ Pulsed Drain Current TA = 25 ° C, tp = 10 s IDM 74 A * **CASE 506BT(SO8FL)** G2 D2 D2 D2 Operating Junction and Storage Temperature TJ, Tstg −55 to ° C +175 5877NL = Specific Device Code for NVMFD5877NL Source Current (Body Diode) IS 19 A 5877LW = Specific Device Code ~~ee ee~~ Single Pulse Drain− (IL(pk) = 14.5 A, L = EAS 10.5 mJ for NVMFD5877NLWF to−Source Avalanche 0.1 mH) A = Assembly Location Energy (TJ = 25 ° C, Y = Year VDD = 24 V, VGS = (IL(pk) = 6.3 A, L = 40 W = Work Week ~~eee~~ 10 V, RG = 25 ) 2 mH) ZZ = Lot Traceability Lead Temperature for Soldering Purposes TL 260 ° C (1/8 ″ from case for 10 s) ~~ee~~ 

**ORDERING INFORMATION** 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

device. If any of these limits are exceeded, device functionality should not be **Device Package Shipping**[†] assumed, damage may occur and reliability may be affected. **THERMAL RESISTANCE MAXIMUM RATINGS** (Note 1) NVMFD5877NLT1G DFN8 1500 / Tape & (Pb−Free) Reel **Parameter Symbol Value Unit** NVMFD5877NLWFT1G DFN8 1500 / Tape & Junction−to−Mounting Board (top) − Steady R J−mb 6.5 ° C/W (Pb−Free) Reel State (Note 2, 3) NVMFD5877NLT3G DFN8 5000 / Tape & Junction−to−Ambient − Steady State (Note 3) R JA 47 (Pb−Free) Reel The entire application environment impacts the thermal resistance values shown, NVMFD5877NLWFT3G DFN8 5000 / Tape & they are not constants and are only valid for the particular conditions noted. (Pb−Free) Reel Psi ( ) is used as required per JESD51−12 for packages in which ~~==~~ substantially less than 100% of the heat flows to single case surface. †For information on tape and reel specifications, Surface−mounted on FR4 board using a 650 mm[[2]] , 2 oz. Cu pad. including part orientation and tape sizes, please Maximum current for pulses as long as 1 second is higher but is dependent refer to our Tape and Reel Packaging Specification on pulse duration and duty cycle. Brochure, BRD8011/D. 

## **THERMAL RESISTANCE MAXIMUM RATINGS** (Note 1) 

1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Psi ( ) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 

3. Surface−mounted on FR4 board using a 650 mm[[2]] , 2 oz. Cu pad. 

4. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2014 **September, 2014 − Rev. 9** 

**NVMFD5877NL/D** 

## **NVMFD5877NL** 

**ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTIC**|**S**(TJ= 25°C|unless otherwise specified)|unless otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= 250�A||60|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ||||53||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 60 V|TJ= 25°C|||1.0|�A|
||||TJ= 125°C|||10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=|±20 V|||±100|nA|
|**ON CHARACTERISTICS**(Note 5)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.0||3.0|V|
|Negative Threshold Temperature<br>Coefficient|VGS(TH)/TJ||||3.5||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 7.5 A||31|39|m�|
|||VGS= 4.5 V|ID= 7.5 A||42|60||
|Forward Transconductance|gFS|VDS = 15 V, ID = 5.0 A|||7.0||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|Ciss|VGS = 0 V, f = 1.0 MHz, VDS = 25 V|||540||pF|
|Output Capacitance|Coss||||55|||
|Reverse Transfer Capacitance|Crss||||36|||
|Total Gate Charge|QG(TOT)|VGS = 4.5 V, VDS = 48 V,<br>ID = 5.0 A|||5.9||nC|
|Threshold Gate Charge|QG(TH)||||0.62|||
|Gate−to−Source Charge|QGS||||1.64|||
|Gate−to−Drain Charge|QGD||||2.80|||
|Total Gate Charge|QG(TOT)|VGS = 10 V, VDS = 48V, ID = 5.0A|||11|20|nC|
|**SWITCHING CHARACTERISTICS**(Note 6)||||||||
|Turn−On Delay Time|td(on)|VGS= 4.5 V, VDS <br>ID= 5.0 A, RG=|= 48 V,<br>2.5�||8.1||ns|
|Rise Time|tr||||15.8|||
|Turn−Off Delay Time|td(off)||||11.8|||
|Fall Time|tf||||3.9|||
|Turn−On Delay Time|td(on)|VGS= 10 V, VDS=<br>ID= 5.0 A, RG=|48 V,<br>2.5�||4.9||ns|
|Rise Time|tr||||6.4|||
|Turn−Off Delay Time|td(off)||||14.5|||
|Fall Time|tf||||2.4|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 5.0 A|TJ= 25°C||0.8|1.2|V|
||||TJ= 125°C||0.7|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt= 100 A/�s,<br>IS= 5.0 A|||14.5||ns|
|Charge Time|ta||||11.5|||
|Discharge Time|tb||||3.1|||
|Reverse Recovery Charge|QRR||||11||nC|
|**PACKAGE PARASITIC VALUES**||||||||
|Source Inductance|LS|TA= 25°C|||0.93||nH|
|Drain Inductance|LD||||0.005|||
|Gate Inductance|LG||||1.84|||
|Gate Resistance|RG||||1.5||�|



5. Pulse Test: pulse width = 300 � s, duty cycle � 2%. 

6. Switching characteristics are independent of operating junction temperatures. 

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**NVMFD5877NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [493 x 627] intentionally omitted <==**

**----- Start of picture text -----**<br>
40 30<br>36 VGS = 10 V 5 V TJ = 25 ° C VDS ≥  10 V<br>32 4.5 V<br>28<br>20<br>24<br>20 4.0 V<br>16 TJ = 25 ° C<br>10<br>12<br>8 3.5 V<br>4 3.0 V TJ = 125 ° C TJ = −55 ° C<br>0 0<br>0 1 2 3 4 5 1 2 3 4 5<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.065 0.065<br>0.060 TIDJ = 25 = 10 A ° C 0.060 TJ = 25 ° C<br>0.055 0.055<br>0.050 0.050<br>VGS = 4.5 V<br>0.045 0.045<br>0.040 0.040<br>0.035 0.035<br>VGS = 10 V<br>0.030 0.030<br>0.025 0.025<br>3 4 5 6 7 8 9 10 5 8 10 13 15 18 20 23 25<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.1 1E−04<br>ID = 7.5 A VGS = 0 V<br>1.9 1E−05<br>VGS = 10 V<br>TJ = 150 ° C<br>1.7 1E−06<br>1.5 1E−07 TJ = 125 ° C<br>1.3 1E−08<br>1.1 1E−09<br>0.9 1E−10 TJ = 25 ° C<br>0.7 1E−11<br>0.5 1E−12<br>−50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25 30 35 40 45 50 55 60<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature vs. Voltage<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (A)<br>IDSS<br>, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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**NVMFD5877NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [491 x 178] intentionally omitted <==**

**----- Start of picture text -----**<br>
800 10<br>VGS = 0 V 9 QT<br>700 Ciss TJ = 25 ° C 8<br>600<br>7<br>500<br>6<br>400 5<br>4 Qgs Qgd<br>300<br>200 3 TJ = 25 ° C<br>Coss 2 VDD = 48 V<br>100 1 ID = 5 A<br>0 Crss 0<br>0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 9 10 11<br>DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)<br>C, CAPACITANCE (pF)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

**Figure 8. Gate−to−Source vs. Gate Charge** 

**==> picture [492 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000 40<br>VDD = 48 V VGS = 0 V<br>VIDGS = 5 A = 10 V TJ = 25 ° C<br>30<br>100<br>td(off)<br>tf<br>20<br>tr<br>10 td(on)<br>10<br>1 0<br>1 10 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0<br>RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** 

**Figure 10. Diode Forward Voltage** 

**==> picture [249 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>10 � s<br>100  � s<br>10<br>1  m s<br>VGS = 20 V 10 ms<br>1 Single Pulse<br>TC = 25 ° C<br>RDS(on) Limit dc<br>Thermal Limit<br>Package Limit<br>0.1<br>0.1 1 10 100<br>VDS, DRAIN VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

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**NVMFD5877NL** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [492 x 193] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>Duty Cycle = 0.5<br>0.2<br>10<br>0.1<br>0.05<br>0.02<br>1<br>0.01<br>Device Mounted on 650 mm [2]<br>0.1 Single Pulse 2 oz Cu PCB<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>Figure 12. Thermal Response<br>C/W)<br>°<br> (<br>JA(t)<br>�<br>R<br>**----- End of picture text -----**<br>


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**NVMFD5877NL** 

## **PACKAGE DIMENSIONS** 

**DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)** CASE 506BT ISSUE E 

**==> picture [491 x 385] intentionally omitted <==**

**----- Start of picture text -----**<br>
2X<br>NOTES:<br>0.20 C 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>D A 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED<br>BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.<br>8 7 D16 5 B 2X 0.20 C 4.5. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELLAS THE TERMINALS.DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS.<br>6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED<br>AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST<br>POINT ON THE PACKAGE BODY.<br>Pa 7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.<br>PIN ONE E1 E 4X MILLIMETERS<br>IDENTIFIER ÉÉ h DIM MIN MAX MAX<br>NOTE 7 A 0.90 −−− 1.10<br>ÉÉ A1 −−− −−− 0.05<br>cls c , A1 b 0.33 0.42 0.51<br>ÉÉ 1 2 3 4 b1 0.33 0.42 0.51<br>= === c 0.20 −−− 0.33<br>TOP VIEW D 5.15 BSC<br>DETAIL B D1 4.70 4.90 5.10<br>0.10 C ALTERNATE D2 3.90 4.10 4.30<br>A DETAIL A CONSTRUCTION D3 1.50 1.70 1.90<br>E 6.15 BSC<br>0.10 C SOLDERING FOOTPRINT* E1 5.70 5.90 6.10<br>NOTE 4 SIDE VIEW C [SEATING] PLANE 4.56 E2e 3.90 1.27 BSC4.15 4.40<br>DETAIL A NOTE 6 G 0.45 0.55 0.65<br>aN D3D2 0.758X 2.082X 0.562X === K1Kh 0.510.56−−− −−−−−−−−− 12 −−−−−−<br>L 0.48 0.61 0.71<br>e 4X L M 3.25 3.50 3.75<br>1 4 K N 1.80 2.00 2.20<br>4X<br>DETAIL B 4.84 1.40 6.59<br>2.30<br>4X 3.70<br>M N b1 E2 -<br>Ah p| t— SS<br>ee 8 5  ee 0.70<br>4X G 8X b<br>K1 0.10 C A B<br>4X 1.00 1.27<br>BOTTOM VIEW 0.05 C NOTE 3 PITCH<br>5.55<br>DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

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