NVMFD5852NLWFT1G

NVMFD5852NL 

## Power MOSFET **40 V, 6.9 m 44 A, Dual N−Channel Logic Level, Dual SO−8FL** 

## **Features** 

- Small Footprint (5x6 mm) for Compact Designs 

## **http://onsemi.com** 

- Low R to Minimize Conduction Losses DS(on) 

- Low Capacitance to Minimize Driver Losses 

**V(BR)DSS RDS(on) MAX ID MAX** 6.9 m @ 10 V 40 V 44 A 12.0 m @ 4.5 V ~~eee~~ 

- NVMFD5852NLWF − Wettable Flanks Option for Enhanced Optical Inspection 

- AEC−Q101 Qualified and PPAP Capable 

- This is a Pb−Free Device 

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Dual N−Channel<br>D1 D2<br>G1 G2<br>S1 S2<br>MARKING DIAGRAM<br>D1 D1<br>1 S1 D1<br>DFN8 5x6 ; G1 — 5852xx D1<br>(SO8FL) S2 AYWZZ D2<br>CASE 506BT G2 D2<br>D2 D2<br>5852NL = Specific Device Code<br>for NVMFD5852NL<br>5852LW = Specific Device Code<br>for NVMFD5852NLWF<br>A = Assembly Location<br>Y = Year<br>W = Work Week<br>ZZ = Lot Traceability<br>**----- End of picture text -----**<br>


**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

**Parameter Symbol Value Unit** Drain−to−Source Voltage VDSS 40 V ~~—A~~ Gate−to−Source Voltage VGS 20 V Continuous Drain CurTmb = 25 ° C ID 44 A rent R2, 3, 4) J−mb[ (Notes 1,] Steady Tmb = 100 ° C 31 Power Dissipation State Tmb = 25 ° C PD 27 W R J−mb[ (Notes 1, 2, 3)] Tmb = 100 ° C 13 ~~PT Ee~~ Continuous Drain CurTA = 25 ° C ID 15 A rent R& 4) JA (Notes 1, 3 Steady TA = 100 ° C 10.6 ~~J~~ Power Dissipation State ~~—~~ TA = 25 ° C PD 3.2 W R JA (Notes 1 & 3) TA = 100 ° C 1.6 ~~Po)~~ Pulsed Drain Current TA = 25 ° ~~ES~~ C, tp = 10 s IDM 329 A Operating Junction and Storage Temperature TJ, Tstg −55 to ° C 175 ~~ee eee~~ Source Current (Body Diode) IS 40 A ~~eses Gs~~ Single Pulse Drain−to−Source Avalanche EAS 80 mJ Energy (TJ = 25 ° C, VGS = 10 V, IL(pk) = 40 A, L = 0.1 mH, RG = 25 ) ~~ow~~ Lead Temperature for Soldering Purposes TL 260 ° C (1/8 ″ from case for 10 s) ~~Pe~~ 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be **ORDERING INFORMATION** assumed, damage may occur and reliability may be affected. **THERMAL RESISTANCE MAXIMUM RATINGS** (Note 1) **Device Package** ~~es~~ **Parameter Symbol Value Unit** NVMFD5852NLT1G DFN8 (Pb−Free) Junction−to−Mounting Board (top) − Steady R J−mb 5.6 State (Notes 2, 3) ° C/W NVMFD5852NLWFT1G DFN8 Junction−to−Ambient − Steady State (Note 3) ~~Gs~~ R JA ~~Gs~~ 47 ~~—~~ (Pb−Free) 

**THERMAL RESISTANCE MAXIMUM RATINGS** (Note 1) **Device Package Shipping**[†] ~~es~~ **Parameter Symbol Value Unit** NVMFD5852NLT1G DFN8 1500 / Tape & (Pb−Free) Reel Junction−to−Mounting Board (top) − Steady R J−mb 5.6 State (Notes 2, 3) ° C/W NVMFD5852NLWFT1G DFN8 1500 / Tape & Junction−to−Ambient − Steady State (Note 3) ~~Gs~~ R JA ~~Gs~~ 47 ~~—~~ (Pb−Free) Reel The entire application environment impacts the thermal resistance values shown, †For information on tape and reel specifications, they are not constants and are only valid for the particular conditions noted. including part orientation and tape sizes, please Psi ( ) is used as required per JESD51−12 for packages in which refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Psi ( ) is used as required per JESD51−12 for packages in which substantially less than 100% of the heat flows to single case surface. 

3. Surface−mounted on FR4 board using a 650 mm[2] , 2 oz. Cu pad. 

4. Maximum current for pulses as long as 1 second are higher but are dependent on pulse duration and duty cycle. 

Publication Order Number: **NVMFD5852NL/D** 

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© Semiconductor Components Industries, LLC, 2014 **September, 2014 − Rev. 6** 

## **NVMFD5852NL** 

**ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTIC**|**S**(TJ= 25°C|unless otherwise specified)|unless otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= 250�A||40|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ||||37.3||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 40 V|TJ= 25°C|||1.0|�A|
||||TJ= 125°C|||100||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=|±20 V|||±100|nA|
|**ON CHARACTERISTICS**(Note 5)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.4||2.4|V|
|Negative Threshold Temperature<br>Coefficient|VGS(TH)/TJ||||6.3||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V, ID= 20 A|||5.3|6.9|m�|
|||VGS= 4.5 V, ID= 20 A|||8.7|12||
|Forward Transconductance|gFS|VDS = 5 V, ID = 5 A|||24||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|Ciss|VGS = 0 V, f = 1.0 MHz, VDS = 25 V|||1800||pF|
|Output Capacitance|Coss||||240|||
|Reverse Transfer Capacitance|Crss||||180|||
|Total Gate Charge|QG(TOT)|VGS = 4.5 V, VDS = 32 V,<br>ID = 20 A|||20||nC|
|Threshold Gate Charge|QG(TH)||||1.5|||
|Gate−to−Source Charge|QGS||||5.5|||
|Gate−to−Drain Charge|QGD||||10.9|||
|Total Gate Charge|QG(TOT)|VGS = 10 V, VDS = 32V, ID = 20 A|||36||nC|
|**SWITCHING CHARACTERISTICS**(Note 6)||||||||
|Turn−On Delay Time|td(on)|VGS= 4.5 V, VDS <br>ID= 20 A, RG=|= 32 V,<br>2.5�||12||ns|
|Rise Time|tr||||52|||
|Turn−Off Delay Time|td(off)||||21|||
|Fall Time|tf||||13|||
|Turn−On Delay Time|td(on)|VGS= 10 V, VDS=<br>ID= 20 A, RG=|32 V,<br>2.5�||12||ns|
|Rise Time|tr||||8.0|||
|Turn−Off Delay Time|td(off)||||27|||
|Fall Time|tf||||5.0|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 20 A|TJ= 25°C||0.84|1.1|V|
||||TJ= 125°C||0.69|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt= 100 A/�s,<br>IS= 20 A|||22.3||ns|
|Charge Time|ta||||12.8|||
|Discharge Time|tb||||9.4|||
|Reverse Recovery Charge|QRR||||15.2||nC|



5. Pulse Test: pulse width = 300 � s, duty cycle � 2%. 

6. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NVMFD5852NL** 

## **TYPICAL CHARACTERISTICS** 

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150 150<br>10 V 7.0 V<br>5.0 V VDS ≥  10 V<br>125 125<br>TJ = 25 ° C<br>100 4.4 V 100<br>75 75<br>4.0 V<br>50 50 T J  = 25 ° C<br>3.6 V<br>25 3.4 V 25<br>TJ = 125 ° C TJ = −55 ° C<br>3.0 V<br>0 0<br>0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.020 0.0200<br>0.018 ID = 20 A 0.0175 T J  = 25 ° C<br>0.016 T J  = 25 ° C<br>0.0150<br>0.014 VGS = 4.5 V<br>0.0125<br>0.012<br>0.0100<br>0.010<br>0.0075<br>0.008 VGS = 10 V<br>0.0050<br>0.006<br>0.004 0.0025<br>0.002 0<br>2 3 4 5 6 7 8 9 10 0 25 50 75 100 125 150<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. VGS Figure 4. On−Resistance vs. Drain Current and<br>Gate Voltage<br>2.2 100,000<br>2.0 ID = 20 A VGS = 0 V<br>VGS = 10 V<br>1.8<br>10,000<br>1.6 TJ = 150 ° C<br>1.4<br>1.2 TJ = 125 ° C<br>1,000<br>1.0<br>0.8<br>0.6 100<br>−50 −25 0 25 50 75 100 125 150 175 5 10 15 20 25 30 35 40<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>, DRAIN−TO−SOURCE<br>IDSS<br>DS(on)<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

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Figure 6. Drain−to−Source Leakage Current<br>vs. Voltage<br>**----- End of picture text -----**<br>


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**NVMFD5852NL** 

## **TYPICAL CHARACTERISTICS** 

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2500 10<br>VGS = 0 V QT<br>2000 C iss TJ = 25 ° C 8<br>1500 6<br>1000 4 Qgs Q gd<br>Coss TJ = 25 ° C<br>500 2 V DS  = 32 V<br>ID = 20 A<br>Crss<br>0 0<br>0 10 20 30 40 0 5 10 15 20 25 30 35 40<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)<br>Figure 7. Capacitance Variation Figure 8. Gate−to−Source and<br>Drain−to−Source Voltage vs. Total Charge<br>1000 100<br>VI D DS = 20 A = 32 V VGS = 0 V<br>VGS = 4.5 V 75<br>tr<br>tf<br>100 td(off) 50<br>t d(on) TJ = 25 ° C<br>25<br>10 0<br>1 10 100 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05<br>RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>C, CAPACITANCE (pF)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** 

**Figure 10. Diode Forward Voltage vs. Current** 

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100<br>10  � s<br>10<br>100  � s<br>1 ms<br>VGS = 10 V<br>1 Single Pulse<br>TC = 25 ° C<br>R DS(on)  Limit 10 ms<br>Thermal Limit<br>Package Limit dc<br>0.1<br>0.1 1 10 100<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


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VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

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**NVMFD5852NL** 

## **TYPICAL CHARACTERISTICS** 

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100<br>Duty Cycle = 50%<br>10 20%<br>10%<br>5%<br>2%<br>1<br>1%<br>0.1<br>Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME (sec)<br>C/W)<br>°<br> (<br>JA<br>�<br>R<br>**----- End of picture text -----**<br>


**Figure 12. Thermal Response** 

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**5** 

**NVMFD5852NL** 

## **PACKAGE DIMENSIONS** 

**DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)** CASE 506BT ISSUE E 

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2X<br>NOTES:<br>0.20 C 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>D A 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED<br>BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.<br>8 7 D16 5 B 2X 0.20 C 4.5. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELLAS THE TERMINALS.DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS.<br>6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED<br>AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST<br>POINT ON THE PACKAGE BODY.<br>Pea 7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.<br>PIN ONE E1 E 4X MILLIMETERS<br>IDENTIFIER h DIM MIN MAX MAX<br>NOTE 7 A 0.90 −−− 1.10<br>ÉÉ A1 −−− −−− 0.05<br>ÉÉ 1 2 3 4 c A1 b1b 0.330.33 0.420.42 0.510.51<br>c 0.20 −−− 0.33<br>TOP VIEW D 5.15 BSC<br>DETAIL B D1 4.70 4.90 5.10<br>0.10 C ALTERNATE D2 3.90 4.10 4.30<br>A DETAIL A CONSTRUCTION D3 1.50 1.70 1.90<br>E 6.15 BSC<br>0.10 C SOLDERING FOOTPRINT* E1 5.70 5.90 6.10<br>NOTE 4 aN SIDE VIEW C [SEATING] PLANE 4.56 == E2e 3.90 1.27 BSC4.15 4.40<br>DETAIL A NOTE 6 2X 2X G 0.45 0.55 0.65<br>D2 0.758X 2.08 0.56 Kh 0.51−−− −−−−−− 12 −−−<br>D3 K1 0.56 −−− −−−<br>L 0.48 0.61 0.71<br>e 4X L M 3.25 3.50 3.75<br>1 4 K N 1.80 2.00 2.20<br>4X<br>DETAIL B 4.84 1.40 6.59<br>2.30<br>het 4X fev bk 3.70  FSE=<br>N b1<br>M E2<br>0.70<br>8 5<br>SE 4X G 8X b Ga e al c===<br>K1 0.10 C A B 4X 1.00 1.27<br>0.05 C NOTE 3 PITCH<br>BOTTOM VIEW<br>5.55<br>ms ong<br>DIMENSION: MILLIMETERS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>ON Semiconductor  and          are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).  SCILLC owns the rights to a number of patents, trademarks,<br>copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.  SCILLC<br>reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any<br>particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without<br>limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications<br>and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC<br>does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for<br>surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where<br>personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and<br>its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,<br>any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture<br>of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner.<br>**----- End of picture text -----**<br>


7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. 

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**NVMFD5852NL/D** 

**6**