NVMFD027N10MCLT1G

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## MOSFET ~~_~~ - Power, Dual N-Channel 

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V(BR)DSS RDS(ON) MAX ID MAX<br>26 m  @ 10 V<br>100 V 28 A<br>35 m  @ 4.5 V<br>ee<br>D1 D2<br>G1 G2<br>S1 S2<br>DUAL N−CHANNEL<br>MARKING<br>DIAGRAM<br>1<br>2} ne<br>DFN8 5x6<br>Gt XXXXXX bt<br>(SO8FL) AYWZZ<br>CASE 506BT<br>{| D2<br>XXXXXX = Specific Device Code<br>A = Assembly Location<br>YW = Year= Work Week<br>W = Work Week =e<br>ZZ = Lot Traceability<br>**----- End of picture text -----**<br>


## 100 V, 26 m 28 A NVMFD027N10MCL 

## **Features** 

- Small Footprint (5x6 mm) for Compact Design 

- Low R to Minimize Conduction Losses DS(on) 

- Low QG and Capacitance to Minimize Driver Losses 

- AEC−Q101 Qualified and PPAP Capable 

- NVMFWD027N10MCL − Wettable Flank Products 

- These Devices are Pb−Free, Halogen Free/BFR Free, Beryllium Free and are RoHS Compliant 

**MARKING MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) **DIAGRAM Parameter Symbol Value Unit** 1 ~~es~~ 2} ne Drain−to−Source Voltage VDSS 100 V **DFN8 5x6** ~~a~~ Gt XXXXXX bt Gate−to−Source Voltage VGS ± 20 V **(SO8FL)** AYWZZ **CASE 506BT** Continuous Drain TC = 25 ° C ID 28 A ~~ee~~ {| D2 Current R JC (Note 1) Steady TC = 100 ° C 20 XXXXXX = Specific Device Code Power Dissipation State TC = 25 ° C PD 46 W A = Assembly Location ~~E~~ R JC (Note 1) ~~y~~ TC = 100 ° C 23 YW = Year= Work Week =e Continuous Drain TA = 25 ° C ID 7.4 A ZZ = Lot Traceability Current R(Notes 1, 2)JA Steady ~~—~~ TA = 100 ° C 5.2 Power Dissipation State TA = 25 ° C PD 3.1 W **ORDERING INFORMATION** R JA (Notes 1, 2) TA = 100 ° C 1.6 ~~re ee~~ **Device Package Shipping** † ~~a~~ Pulsed Drain Current T ~~ee~~ A = 25 ° ~~ee~~ C, tp = 10 s IDM 115 A ~~es~~ Operating Junction and Storage Temperature ~~Oe~~ TJ, Tstg −55 to ° C NVMFD027N10MCLT1G (Pb−Free)DFN8 Tape &1500 / Range +175 NVMFWD027N10MCLT1G Reel (Wettable Flanks) ~~**e**~~ Source Current (Body Diode) ~~e~~ IS 35 A ~~— s~~ †For information on tape and reel specifications, Single Pulse Drain−to−Source Avalanche EAS 154 mJ including part orientation and tape sizes, please ~~ee~~ Energy (ILead Temperature Soldering Reflow for Solder-L(pk) = 1.3 A) ~~ee~~ TL 260 ~~ee~~ ° C refer to our Tape and Reel Packaging SpecificationBrochure, BRD8011/D. ing Purposes (1/8 ″ from case for 10 s) ~~eeeee~~ Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL RESISTANCE RATINGS** 

|**Parameter**<br>~~es~~|**Symbol**<br>~~es~~|**Value**<br>~~es~~|**Unit**<br>~~es~~|
|---|---|---|---|
|Junction−to−Case − Steady State (Note 1)|R JC|3.29|°C/W|
|Junction−to−Ambient − Steady State (Note 2)|R JA|48||



1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 

2. Surface−mounted on FR4 board using 1 in[2] pad size, 2 oz. Cu pad. 

Publication Order Number: **NVMFD027N10MCL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2021 **October, 2021 − Rev. 0** 

## **NVMFD027N10MCL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|100|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||50||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 100 V|TJ= 25°C|||1.0|�A|
||||TJ= 125°C|||100||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS= 20 V||||100|nA|
|**ON CHARACTERISTICS**||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 38�A||1||3|V|
|Threshold Temperature Coefficient|VGS(TH)/TJ||||−5.4||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V, ID= 7 A|||21|26|m�|
|||VGS= 4.5 V, ID= 5 A|||28|35||
|Forward Transconductance|gFS|VDS= 10 V, ID= 7 A|||27||S|
|**CHARGES & CAPACITANCES**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 50 V|||720||pF|
|Output Capacitance|COSS||||300|||
|Reverse Transfer Capacitance|CRSS||||6|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 50 V, ID= 7 A|||5.5||nC|
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 50 V, ID= 7 A|||11|||
|Threshold Gate Charge|QG(TH)||||1.1|||
|Gate−to−Source Charge|QGS||||2|||
|Gate−to−Drain Charge|QGD||||1.4|||
|Plateau Voltage|VGP||||2.5||V|
|**SWITCHING CHARACTERISTICS**(Note 3)||||||||
|Turn−On Delay Time|td(ON)|VGS= 10 V, VDS= 50 V,<br>ID= 7 A, RG= 6�|||7||ns|
|Rise Time|tr||||2.5|||
|Turn−Off Delay Time|td(OFF)||||19|||
|Fall Time|tf||||3.2|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 7 A|TJ= 25°C||0.84|1.3|V|
||||TJ= 125°C||0.73|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 100 A/�s,<br>IS= 3 A|||28||ns|
|Reverse Recovery Charge|QRR||||17||nC|
|Charge Time|ta||||13.9||ns|
|Discharge Time|tb||||14.2||ns|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Switching characteristics are independent of operating junction temperatures 

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**NVMFD027N10MCL** 

## **TYPICAL CHARACTERISTICS** 

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25 25<br>3.0 V VDS = 10 V<br>20 20<br>VGS = 10 V to 3.2 V 2.8 V<br>15 15<br>TJ = 25 ° C<br>2.6 V<br>10 10<br>2.4 V<br>5 5<br>0 2.2 V 0 TJ = 150 ° C TJ = −55 ° C<br>0 1 2 3 4 5 0 1 2 3 4<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>50 33<br>45 TIDJ = 7 A = 25 ° C 31 T J  = 25 ° C<br>40 29 V GS  = 4.5 V<br>35<br>27<br>30<br>25<br>25<br>23<br>20 VGS = 10 V<br>21<br>15<br>10 19<br>5 17<br>0 15<br>2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>2.5 10<br>VGS = 10 V TJ = 175 ° C<br>ID = 7 A 1 TJ = 150 ° C<br>2.0<br>0.1 TJ = 125 ° C<br>1.5 0.01 TJ = 85 ° C<br>0.001<br>1.0 TJ = 25 ° C<br>0.0001<br>0.5 0.00001<br>−50 −25 0 25 50 75 100 125 150 175 10 20 30 40 50 60 70 80 90 100<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE (m , DRAIN−TO−SOURCE RESISTANCE (m<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>, NORMALIZED DRAIN−TO− IDSS<br>SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**Figure 6. Drain−to−Source Leakage Current vs. Voltage** 

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**NVMFD027N10MCL** 

## **TYPICAL CHARACTERISTICS** 

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1000<br>CISS<br>C OSS<br>100<br>10<br>VGS = 0 V<br>T J  = 25 ° C CRSS<br>f = 1 MHz<br>1<br>0 10 20 30 40 50 60 70 80 90 100<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 7. Capacitance Variation<br>100<br>VGS = 10 VGS = 10 V = 10 V<br>VDS = 50 VDS = 50 V = 50 V td(off)d(off)<br>ID = 50 AD = 50 A = 50 A t f<br>trr<br>td(on)d(on)<br>10<br>1<br>1 10 100<br>C, CAPACITANCE (pF)<br>t, TIME (ns)<br>**----- End of picture text -----**<br>


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10<br>9<br>8<br>7<br>6<br>5<br>4 QGS QGD<br>3<br>2 TJ = 25 ° C<br>ID = 7 A<br>1<br>V DS  = 50 V<br>0<br>0 2 4 6 8 10 12<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


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QG, TOTAL GATE CHARGE (nC)<br>**----- End of picture text -----**<br>


**Figure 8. Gate−to−Source Voltage vs. Total Charge** 

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100 10<br>VGS = 10 VGS = 10 V = 10 V V GS  = 0 V<br>VDS = 50 VDS = 50 V = 50 V td(off)d(off)<br>ID = 50 AD = 50 A = 50 A<br>t f<br>trr<br>td(on)d(on)<br>10<br>TJ = 125 ° C TJ = 25 ° C TJ = −55 ° C<br>1 1<br>1 10 100 0.5 0.6 0.7 0.8 0.9 1.0<br>RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage vs. Current<br>vs. Gate Resistance<br>1000 100<br>TC = 25 ° C<br>Single Pulse<br>VGS ≤  10 V<br>100<br>10<br>TJ(initial) = 25 ° C<br>10 10 � s<br>TJ(initial) = 125 ° C<br>1<br>1<br>RDS(on) Limit<br>Thermal Limit 0.5 ms<br>Package Limit 10 ms 1 ms<br>0.1 0.1<br>0.1 1 10 100 1000 0.00001 0.0001 0.001 0.01<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (s)<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>IS<br> (A)<br>IPEAK<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 12. Maximum Drain Current vs. Time in Avalanche** 

**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

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**NVMFD027N10MCL** 

## **TYPICAL CHARACTERISTICS** 

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100<br>Duty Cycle = 0.5<br>0.2<br>10<br>0.1<br>0.05<br>0.02<br>1<br>0.01<br>0.1<br>Single Pulse<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>t, PULSE TIME (sec)<br>C/W)<br>°<br>R(t) (<br>**----- End of picture text -----**<br>


**Figure 13. Transient Thermal Impedance** 

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**NVMFD027N10MCL** 

## **PACKAGE DIMENSIONS** 

# **DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)** CASE 506BT ISSUE E 

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2X<br>NOTES:<br>0.20 C 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>D A 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED<br>BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.<br>8 7 D16 5 B 2X 0.20 C 4.5. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELLAS THE TERMINALS.DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE BURRS.<br>6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED<br>AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST<br>POINT ON THE PACKAGE BODY.<br>7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.<br>PIN ONE E1 E 4X MILLIMETERS<br>IDENTIFIER h DIM MIN MAX MAX<br>NOTE 7 ÉÉ A 0.90 −−− 1.10<br>A1 −−− −−− 0.05<br>ÉÉ c A1 b 0.33 0.42 0.51<br>1 2 3 4 b1 0.33 0.42 0.51<br>c 0.20 −−− 0.33<br>TOP VIEW D 5.15 BSC<br>D1 4.70 4.90 5.10<br>0.10 C D2 3.90 4.10 4.30<br>A DETAIL A D3 1.50 1.70 1.90<br>E 6.15 BSC<br>0.10 C E1 5.70 5.90 6.10<br>NOTE 4 SIDE VIEW C [SEATING] PLANE E2e 3.90 1.27 BSC4.15 4.40<br>DETAIL A NOTE 6 G 0.45 0.55 0.65<br>h −−− −−− 12    �<br>D2 K 0.51 −−− −−−<br>D3 K1 0.56 −−− −−−<br>L 0.48 0.61 0.71<br>e 4X L M 3.25 3.50 3.75<br>1 4 K N 1.80 2.00 2.20<br>DETAIL B SOLDERING FOOTPRINT*<br>DETAIL B ALTERNATE<br>CONSTRUCTION 4.56<br>4X 2X 2X<br>M N b1 E2 0.758X 2.08 0.56<br>8 5<br>4X G 8X b<br>K1 0.10 C A B 4.84 1.404X 6.59<br>0.05 C NOTE 3 2.30<br>BOTTOM VIEW 3.70<br>0.70<br>4X 1.00 1.27<br>PITCH<br>5.55<br>DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>


   6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 

   7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA. 

- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

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**NVMFD027N10MCL** 

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