NVMD4N03R2G

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## MOSFET – Power, Dual, **- -** N Channel, SO 8 

**VDSS RDS(ON) Typ ID Max** 30 V 48 m @ VGS = 10 V 4.0 A ~~**a** ee~~ ee 

## 4 A, 30 V 

## NTMD4N03, NVMD4N03 

## **Features** 

- Designed for use in low voltage, high speed switching applications 

- Ultra Low On-Resistance Provides 

Higher Efficiency and Extends Battery Life 

− RDS(on) = 0.048 VGS = 10 V (Typ) − RDS(on) = 0.065 VGS = 4.5 V (Typ) 

- Miniature SO-8 Surface Mount Package − Saves Board Space 

- Diode is Characterized for Use in Bridge Circuits 

- Diode Exhibits High Speed, with Soft Recovery 

- NVMD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable* 

- These Devices are Pb-Free and are RoHS Compliant 

## **Applications** 

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N-Channel<br>D D<br>G G<br>S S<br>MARKING DIAGRAM<br>AND PIN ASSIGNMENT<br>8<br>1 D1 D1 D2 D2<br>8<br>SOIC-8<br>SUFFIX NB E4N03<br>CASE 751 AYWW<br>STYLE 11<br>1<br>S1 G1 S2 G2<br>**----- End of picture text -----**<br>


## **MARKING DIAGRAM** * **AND PIN ASSIGNMENT** 

- DC-DC Converters 

E4N03 = Specific Device Code A = Assembly Location Y = Year WW = Work Week = Pb-Free Package 

- Computers 

- Printers 

- Cellular and Cordless Phones 

- Disk Drives and Tape Drives 

(Note: Microdot may be in either location) 

- For additional marking information, refer to Application Note AND8002/D. 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

|**MAXIMUM RATINGS**(TJ = 25J = 25= 25°C unless otherwise noted)|**MAXIMUM RATINGS**(TJ = 25J = 25= 25°C unless otherwise noted)|Application Note AND8002/D.<br>.|
|---|---|---|
|**Rating**<br>**Symbol**<br>**Value**<br>**Unit**<br>~~TTT~~|||
|Drain-to-Source Voltage<br>VDSS<br>30<br>V<br>Gate-to-Source Voltage − Continuous<br>VGS<br>±20<br>V<br>Drain Current<br>− Continuous @ TA= 25°C<br>− Single Pulse (tp≤10 s)<br>ID<br>IDM<br>4.0<br>12<br>Adc<br>Apk<br>Total Power Dissipation<br>@ TA= 25°C (Note 1)<br>PD<br>2.0<br>W<br>Operating and Storage<br>Temperature Range<br>TJ, Tstg<br>−55 to<br>+150<br>°C<br>~~a~~<br>~~EEE~~<br>~~**P**f~~<br>~~e~~||† For information on tape and reel specifications,<br>including part orientation and tape sizes, please<br>**Device**<br>**Package**<br>**Shipping**<br>**ORDERING INFORMATION**<br>NTMD4N03R2G<br>SOIC-8<br>(Pb-Free)<br>2500 / Tape &<br>Reel<br>NVMD4N03R2G*<br>SOIC-8<br>(Pb-Free)<br>2500 / Tape &<br>Reel<br>~~=~~|
|Single Pulse Drain-to-Source<br>EAS<br>80|mJ|refer to our Tape and Reel Packaging Specification|
|Avalanche Energy − Starting TJ= 25°C||Brochure, BRD8011/D<br>.|
|(VDD= 25 Vdc, VGS= 5.0 Vdc,|||
|Peak IL= 4.45 Apk, L = 8 mH,|||
|RG= 25 )<br>Thermal Resistance<br>− Junction-to-Ambient (Note 1)<br>R JA<br>62.5<br>°C/W<br>Maximum Lead Temperature for<br>Soldering Purposes for 10 seconds<br>TL<br>260<br>°C<br>Stresses exceeding those listed in the Maximum Ratings table may damage the<br>~~a~~<br>~~Pp~~|||
|device. If any of these limits are exceeded, device functionality should not be|||
|assumed, damage may occur and reliability may be affected.|||



**Device Package Shipping**[†] NTMD4N03R2G SOIC-8 2500 / Tape & (Pb-Free) Reel NVMD4N03R2G* SOIC-8 2500 / Tape & (Pb-Free) Reel ~~=~~ † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

1. When surface mounted to an FR4 board using 1 ″ pad size, t ≤ 10 s 

Publication Order Number: **NTMD4N03R2/D** 

**1** 

© Semiconductor Components Industries, LLC, 2013 **January, 2026 − Rev. 5** 

## **NTMD4N03, NVMD4N03** 

**ELECTRICAL CHARACTERISTICS** (TC = 25 ° C unless otherwise noted) 

|**Characteristic**<br>**Symbol**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**OFF CHARACTERISTICS**<br>~~A~~|
|---|
|Drain-to-Source Breakdown Voltage<br>(VGS= 0 Vdc, ID= 250 A)<br>Temperature Coefficient (Positive)<br>V(BR)DSS<br>30<br>−<br>−<br>32<br>−<br>−<br>Vdc<br>mV/°C<br>Zero Gate Voltage Drain Current<br>(VDS= 30 Vdc, VGS= 0 Vdc, TJ= 25°C)<br>(VDS= 30 Vdc, VGS= 0 Vdc, TJ= 125°C)<br>IDSS<br>−<br>−<br>−<br>−<br>1.0<br>10<br>Adc<br>Gate-Body Leakage Current<br>IGSS<br>nAdc<br>~~ee~~<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~|
|(VGS=±20 Vdc, VDS= 0 Vdc)<br>−<br>−<br>100|
|**ON CHARACTERISTICS**(Note 2)|
|Gate Threshold Voltage<br>(VDS= VGS, ID= 250 Adc)<br>Temperature Coefficient (Negative)<br>VGS(th)<br>1.0<br>−<br>1.9<br>4.2<br>3.0<br>−<br>Vdc<br>mV/°C<br>Static Drain-to-Source On-State Resistance<br>(VGS= 10 Vdc, ID= 4 Adc)<br>(VGS= 4.5 Vdc, ID= 2 Adc)<br>RDS(on)<br>−<br>−<br>0.048<br>0.065<br>0.060<br>0.080<br>~~ee~~<br>~~ee~~<br>~~po~~|
|Forward Transconductance<br>gFS<br>Mhos|
|(VDS= 3 Vdc, ID= 2 Adc)<br>−<br>6.0<br>−|
|**DYNAMIC CHARACTERISTICS**|
|Input Capacitance<br>Ciss<br>−<br>285<br>400<br>pF|
|(VDS= 20 Vdc, VGS= 0 Vdc,<br>f = 1.0 MHz)<br>Output Capacitance<br>Coss<br>−<br>95<br>135|
|Reverse Transfer Capacitance<br>Crss<br>−<br>35<br>70|
|**SWITCHING CHARACTERISTICS**(Notes 2 & 3)<br>Turn-On Delay Time<br>(VDD= 20 Vdc, ID= 2 A,<br>VGS= 10 V,<br>RG= 2 )<br>td(on)<br>−<br>7.0<br>15<br>ns<br>Rise Time<br>tr<br>−<br>14<br>30<br>Turn-Off Delay Time<br>td(off)<br>−<br>16<br>30<br>Fall Time<br>tf<br>−<br>10<br>20<br>Gate Charge<br>(VDS= 10 Vdc,<br>VGS= 10 Vdc,<br>ID= 3.5 A)<br>QT<br>−<br>8.0<br>16<br>nC<br>Q1<br>−<br>1.1<br>−<br>Q2<br>−<br>1.9<br>−<br>~~7~~<br>~~i~~<br>~~ee~~<br>~~>~~<br>~~i~~<br>~~ee~~<br>~~>~~<br>~~i~~<br>~~ee~~<br>~~>~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~i~~<br>~~ee~~<br>~~a~~|
|**BODY-DRAIN DIODE RATINGS**(Note 2)|
|Diode Forward On-Voltage<br>(IS= 2 Adc, VGS= 0 V)<br>VSD<br>−<br>0.82<br>1.0<br>Vdc|
|(IS= 2 Adc, VGS= 0 V, TJ= 150°C)<br>−<br>0.63<br>−<br>Reverse Recovery Time<br>(IS= 2 A, VGS= 0 V,<br>dIS/dt = 100 A/ s)<br>trr<br>−<br>14<br>−<br>ns<br>ta<br>−<br>10<br>−<br>tb<br>−<br>4.0<br>−<br>Reverse Recovery Stored Charge<br>(IS= 2 A, dIS/dt = 100 A/ s, VGS= 0 V)<br>QRR<br>−<br>0.008<br>−<br>C<br>Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product<br>~~i~~<br>~~ee~~<br>ee<br>~~ee ee~~<br>~~iee~~<br>~~a~~|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

2. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle u ≤ 2%. 

3. Switching characteristics are independent of operating junction temperature. 

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## **TYPICAL MOSFET ELECTRICAL CHARACTERISTICS** 

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8 7<br>10 V 4 V 3.6 V<br>J ~ V DS ≥  10 V | { | | Yer 7 |<br>6<br>8 V<br>6<br>5<br>6 V 4.5 V<br>===<br>5 V 4<br>4 SS) [S][e]<br>3<br>Uf FIP<br>T J  = 25  ° C<br>VGS = 3 V 2<br>2<br>1 T J  = 125  ° C<br>fo | | TJ = 25  | ° C | e/a T J  = −55  ° C<br>0 oo o 0 HSH<br>0 0.2 0.4 0.6 0.8 1.0 0 1 2 3 4 5<br>VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)<br>Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics<br>0.10 0.10<br>VGS = 10 TJ = 25  ° C<br>0.08<br>0.075 Ee T = 125  ° C a ee ee e e<br>VGS = 4.5 V<br>a a<br>0.06<br>T = 25  ° C VGS = 10 V<br>0.05 Po OD)<br>a T = −55  ee ° C 0.04 a<br>0.025<br>0.02<br>-{ tt tt EEE<br>0 TTTETEEE| } ER 0<br>2 3 4 5 6 7 8 2 3 4 5 6 7 8<br>ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On-Resistance versus Drain Current Figure 4. On-Resistance versus Drain Current<br>and Temperature and Gate Voltage<br>1.5 10,000<br>VGS = 0 V<br>1.375 ID = 2 A<br>VGS = 10 V<br>1.25 eae 1000 =e8_========<br>BD 40 Beeeeeeeeeeeee TJ = 150  ° C<br>1.125<br>ttt<br>1 100<br>pftr}tt| || ) SGeer S TJ = 125  r ° C Sr<br>0.875 pet<br>tt EP<br>0.75 ee 10 e e e<br>−50 −25 0 25 50 75 100 125 150 0 5 10 15 20 25 30<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)<br>Figure 5. On-Resistance Variation with Figure 6. Drain-to-Source Leakage Current<br>Temperature versus Voltage<br>, DRAIN CURRENT (AMPS) , DRAIN CURRENT (AMPS)<br>ID ID<br>) )<br>, DRAIN-TO-SOURCE RESISTANCE ( , DRAIN-TO-SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>IDSS<br>, DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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## **POWER MOSFET SWITCHING** 

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals ( t) are determined by how fast the FET input capacitance can be charged by current from the generator. 

The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that 

t = Q/IG(AV) 

During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: 

tr = Q2 x RG/(VGG − VGSP) 

tf = Q2 x RG/VGSP 

## where 

VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance 

and Q2 and VGSP are read from the gate charge curve. 

During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: 

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). 

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. 

The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 

td(on) = RG Ciss In [VGG/(VGG − VGSP)] 

td(off) = RG Ciss In (VGG/VGSP) 

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800<br>TJ = 25  ° C<br>TTT C iss<br>600 E Crss LL<br>POWELL ELE<br>400 COOMA EEE<br>Ciss<br>FOCANSEEE ET<br>200 COCO<br>Coss<br>PCCCRCSEE Crss TT<br>0 CC VDS = 0 V DSS VGS = 0 V ES<br>10 5 0 5 10 15 20 25<br>VGS VDS<br>GATE-TO-SOURCE OR DRAIN-TO-SOURCE<br>VOLTAGE (VOLTS)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

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10 30 100<br>Q T VDD = 15 V td(off)<br>VGS ID = 4 A tf<br>8 aee a 20 VGS = 10 V ESCOaerae o tr<br>6 Py a<br>VDS<br>a 72 10 1 |<br>4 Q 1 Q 2 td(on)<br>i a SS SS SS oe<br>i 10 ——Sso see<br>2 rT AVI | [| | fl TIDJ = 4 A = 25  ° C PT | TT<br>At + a ee el<br>0 JN 0 1 ee<br>0 1 2 3 4 5 6 7 8 9 10 1 10 100<br>Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE ( Q )<br>Figure 8. Gate-to-Source and Drain-to-Source Figure 9. Resistive Switching Time Variation<br>Voltage versus Total Charge versus Gate Resistance<br>t, TIME (ns)<br>, GATE-TO-SOURCE VOLTAGE (VOLTS) , DRAIN-TO-SOURCE VOLTAGE (VOLTS)<br>GS DS<br>V V<br>**----- End of picture text -----**<br>


## **DRAIN-TO-SOURCE DIODE CHARACTERISTICS** 

The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. 

System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. 

The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 

high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. 

Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 

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4<br>VGS = 0 V<br>TJ = 25  ° C<br>pf<br>3 eee<br>ee<br>2 P| tT | | tT Ty<br>ee<br>1 PT tT | tT eeTA<br>ee ae<br>0<br>Pt [Pte]<br>0.5 0.6 0.7 0.8 0.9<br>VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)<br>, SOURCE CURRENT (AMPS)<br>IS<br>**----- End of picture text -----**<br>


**Figure 10. Diode Forward Voltage versus Current** 

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## **SAFE OPERATING AREA** 

The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25 °C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” 

Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the u 

total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(R 6 JC). 

A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. 

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100<br>V GS  = 20 V<br>SINGLE PULSE<br>TC = 25  ° C<br>10<br>1.0 ms<br>10 ms<br>1<br>0.1<br>RDS(on) LIMIT dc<br>THERMAL LIMIT<br>PACKAGE LIMIT<br>0.01 PU ET<br>0.1 1.0 10 100<br>VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)<br>, DRAIN CURRENT (AMPS)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

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**----- Start of picture text -----**<br>
80<br>I D  = 4.45 A<br>60<br>40<br>20<br>0 a eee<br>25 50 75 100 125 150<br>TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>Figure 12. Maximum Avalanche Energy versus<br>Starting Junction Temperature<br>AVALANCHE ENERGY (mJ)<br>, SINGLE PULSE DRAIN-TO-SOURCE<br>AS<br>E<br>**----- End of picture text -----**<br>


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## **TYPICAL ELECTRICAL CHARACTERISTICS** 

**==> picture [479 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.0<br>D = 0.5 i<br>o 0.2 e rtrrr totte tee<br>0.1 TIT ITTTTT<br>0.1 e err e | TIE | TIT EIT TT<br>0.05<br>Too 1 rr c]<br>0.02<br>0.0106  0.0431  0.1643  0.3507  0.4302<br>0.01 ia een aiiltea a OTitli CHIP Q Q Q Q Q [|<br>0.01 JUNCTION<br>SS 0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F H<br>eet || IT | |<br>pe T T F T T * 4<br>a = ee eee eee = = = = = AMBIENT |<br>SINGLE PULSE<br>0.001 PT CIE CO |<br>1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03<br>t, TIME (s)<br>THERMAL RESISTANCE<br>Rthja(t), EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Response** 

**==> picture [187 x 98] intentionally omitted <==**

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di/dt<br>IS<br>t rr<br>ta t b<br>—L Z TIME<br>| Z<br>A t p 0.25 IS<br>Ce<br>IS<br>**----- End of picture text -----**<br>


**Figure 14. Diode Reverse Recovery Waveform** 

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## **REVISION HISTORY** 

|**Revision**<br>**Description of Changes**<br>**Date**<br>5<br>Rebranded the document to**onsemi**format.<br>1/22/2026<br>This document has undergone updates prior to the inclusion of this revision history table. The changes tracked here only reflect updates made<br>~~—~~|
|---|
|on the noted approval dates.|



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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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**SOIC−8 NB** CASE 751−07 ISSUE AK 

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NOTES:<br>−X− 1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>4 MAXIMUM MATERIAL CONDITION.<br>−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW<br>STANDARD IS 751−07.<br>G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>A 4.80 5.00 0.189 0.197<br>C N X 45 � B 3.80 4.00 0.150 0.157<br>SEATING C 1.35 1.75 0.053 0.069<br>PLANE D 0.33 0.51 0.013 0.020<br>−Z− G 1.27 BSC 0.050 BSC<br>H 0.10 0.25 0.004 0.010<br>0.10 (0.004) J 0.19 0.25 0.007 0.010<br>H D M J MK 0.400   � 1.278   � 0.0160   � 0.0508   �<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244<br>GENERIC<br>MARKING DIAGRAM*<br>SOLDERING FOOTPRINT*<br>8 8 8 8<br>XXXXX XXXXX XXXXXX XXXXXX<br>1.52 ALYWX ALYWX � AYWW AYWW �<br>0.060<br>1 1 1 1<br>IC IC Discrete Discrete<br>(Pb−Free) (Pb−Free)<br>7.0 4.0<br>XXXXX = Specific Device Code XXXXXX = Specific Device Code<br>0.275 0.155<br>A = Assembly Location A = Assembly Location<br>L = Wafer Lot Y = Year<br>Y = Year WW = Work Week<br>W = Work Week � = Pb−Free Package<br>� = Pb−Free Package<br>0.6 1.270 *This information is generic. Please refer to<br>0.024 0.050 device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ � ”, may<br>or may not be present. Some products may<br>SCALE 6:1<br>� inches [mm] � not follow the Generic Marking.<br>**----- End of picture text -----**<br>


- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

*For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

## **STYLES ON PAGE 2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 1 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**SOIC−8 NB** CASE 751−07 ISSUE AK 

**==> picture [79 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
DATE 16 FEB 2011<br>**----- End of picture text -----**<br>


|STYLE 1:|STYLE 1:|STYLE 2:||STYLE 3:|STYLE 3:||STYLE 4:|STYLE 4:|
|---|---|---|---|---|---|---|---|---|
|PIN 1.|EMITTER|PIN 1.|COLLECTOR, DIE, #1|PIN 1.||DRAIN, DIE #1|PIN 1.|ANODE|
|2.|COLLECTOR|2.|COLLECTOR, #1|2.||DRAIN, #1|2.|ANODE|
|3.|COLLECTOR|3.|COLLECTOR, #2|3.||DRAIN, #2|3.|ANODE|
|4.|EMITTER|4.|COLLECTOR, #2|4.||DRAIN, #2|4.|ANODE|
|5.|EMITTER|5.|BASE, #2|5.||GATE, #2|5.|ANODE|
|6.|BASE|6.|EMITTER, #2|6.||SOURCE, #2|6.|ANODE|
|7.|BASE|7.|BASE, #1|7.||GATE, #1|7.|ANODE|
|8.|EMITTER|8.|EMITTER, #1|8.||SOURCE, #1|8.|COMMON CATHODE|
|STYLE 5:||STYLE 6:||STYLE 7:|||STYLE 8:||
|PIN 1.|DRAIN|PIN 1.|SOURCE|PIN 1.||INPUT|PIN 1.|COLLECTOR, DIE #1|
|2.|DRAIN|2.|DRAIN|2.||EXTERNAL  BYPASS|2.|BASE, #1|
|3.|DRAIN|3.|DRAIN|3.||THIRD STAGE SOURCE|3.|BASE, #2|
|4.|DRAIN|4.|SOURCE|4.||GROUND|4.|COLLECTOR, #2|
|5.|GATE|5.|SOURCE|5.||DRAIN|5.|COLLECTOR, #2|
|6.|GATE|6.|GATE|6.||GATE 3|6.|EMITTER, #2|
|7.|SOURCE|7.|GATE|7.||SECOND STAGE Vd|7.|EMITTER, #1|
|8.|SOURCE|8.|SOURCE|8.||FIRST STAGE Vd|8.|COLLECTOR, #1|
|STYLE 9:||STYLE 10:||STYLE 11:|||STYLE 12:||
|PIN 1.|EMITTER,  COMMON|PIN 1.|GROUND|PIN 1.||SOURCE 1|PIN 1.|SOURCE|
|2.|COLLECTOR, DIE #1|2.|BIAS 1|2.||GATE 1|2.|SOURCE|
|3.|COLLECTOR, DIE #2|3.|OUTPUT|3.||SOURCE 2|3.|SOURCE|
|4.|EMITTER, COMMON|4.|GROUND|4.||GATE 2|4.|GATE|
|5.|EMITTER, COMMON|5.|GROUND|5.||DRAIN 2|5.|DRAIN|
|6.|BASE, DIE #2|6.|BIAS 2|6.||DRAIN 2|6.|DRAIN|
|7.|BASE, DIE #1|7.|INPUT|7.||DRAIN 1|7.|DRAIN|
|8.|EMITTER, COMMON|8.|GROUND|8.||DRAIN 1|8.|DRAIN|
|STYLE 13:||STYLE 14:||STYLE 15:|||STYLE 16:||
|PIN 1.|N.C.|PIN 1.|N−SOURCE|PIN 1.|ANODE 1||PIN 1.|EMITTER, DIE #1|
|2.|SOURCE|2.|N−GATE|2.|ANODE 1||2.|BASE, DIE #1|
|3.|SOURCE|3.|P−SOURCE|3.|ANODE 1||3.|EMITTER, DIE #2|
|4.|GATE|4.|P−GATE|4.|ANODE 1||4.|BASE, DIE #2|
|5.|DRAIN|5.|P−DRAIN|5.|CATHODE, COMMON||5.|COLLECTOR, DIE #2|
|6.|DRAIN|6.|P−DRAIN|6.|CATHODE, COMMON||6.|COLLECTOR, DIE #2|
|7.|DRAIN|7.|N−DRAIN|7.|CATHODE, COMMON||7.|COLLECTOR, DIE #1|
|8.|DRAIN|8.|N−DRAIN|8.|CATHODE, COMMON||8.|COLLECTOR, DIE #1|
|STYLE 17:||STYLE 18:||STYLE 19:|||STYLE 20:||
|PIN 1.|VCC|PIN 1.|ANODE|PIN 1.||SOURCE 1|PIN 1.|SOURCE (N)|
|2.|V2OUT|2.|ANODE|2.||GATE 1|2.|GATE (N)|
|3.|V1OUT|3.|SOURCE|3.||SOURCE 2|3.|SOURCE (P)|
|4.|TXE|4.|GATE|4.||GATE 2|4.|GATE (P)|
|5.|RXE|5.|DRAIN|5.||DRAIN 2|5.|DRAIN|
|6.|VEE|6.|DRAIN|6.||MIRROR 2|6.|DRAIN|
|7.|GND|7.|CATHODE|7.||DRAIN 1|7.|DRAIN|
|8.|ACC|8.|CATHODE|8.||MIRROR 1|8.|DRAIN|
|STYLE 21:||STYLE 22:||STYLE 23:|||STYLE 24:||
|PIN 1.|CATHODE 1|PIN 1.|I/O LINE 1|PIN 1.||LINE 1 IN|PIN 1.|BASE|
|2.|CATHODE 2|2.|COMMON CATHODE/VCC|2.||COMMON ANODE/GND|2.|EMITTER|
|3.|CATHODE 3|3.|COMMON CATHODE/VCC|3.||COMMON ANODE/GND|3.|COLLECTOR/ANODE|
|4.|CATHODE 4|4.|I/O LINE 3|4.||LINE 2 IN|4.|COLLECTOR/ANODE|
|5.|CATHODE 5|5.|COMMON ANODE/GND|5.||LINE 2 OUT|5.|CATHODE|
|6.|COMMON ANODE|6.|I/O LINE 4|6.||COMMON ANODE/GND|6.|CATHODE|
|7.|COMMON ANODE|7.|I/O LINE 5|7.||COMMON ANODE/GND|7.|COLLECTOR/ANODE|
|8.|CATHODE 6|8.|COMMON ANODE/GND|8.||LINE 1 OUT|8.|COLLECTOR/ANODE|
|STYLE 25:||STYLE 26:||STYLE|27:||STYLE 28:||
|PIN 1.|VIN|PIN 1.|GND|PIN 1.||ILIMIT|PIN 1.|SW_TO_GND|
|2.|N/C|2.|dv/dt|2.||OVLO|2.|DASIC_OFF|
|3.|REXT|3.|ENABLE|3.||UVLO|3.|DASIC_SW_DET|
|4.|GND|4.|ILIMIT|4.||INPUT+|4.|GND|
|5.|IOUT|5.|SOURCE|5.||SOURCE|5.|V_MON|
|6.|IOUT|6.|SOURCE|6.||SOURCE|6.|VBULK|
|7.|IOUT|7.|SOURCE|7.||SOURCE|7.|VBULK|
|8.|IOUT|8.|VCC|8.||DRAIN|8.|VIN|
|STYLE 29:||STYLE 30:|||||||
|PIN 1.|BASE, DIE #1|PIN 1.|DRAIN 1||||||
|2.|EMITTER, #1|2.|DRAIN 1||||||
|3.|BASE, #2|3.|GATE 2||||||
|4.|EMITTER, #2|4.|SOURCE 2||||||
|5.|COLLECTOR, #2|5.|SOURCE 1/DRAIN 2||||||
|6.|COLLECTOR, #2|6.|SOURCE 1/DRAIN 2||||||
|7.|COLLECTOR, #1|7.|SOURCE 1/DRAIN 2||||||
|8.|COLLECTOR, #1|8.|GATE 1||||||



Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 2 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

**www.onsemi.com** 

~~**2**~~ 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

**TECHNICAL PUBLICATIONS** : **ONLINE SUPPORT** : www.onsemi.com/support **Technical Library:** www.onsemi.com/design/resources/technical−documentation **For additional information, please contact your local Sales Representative at onsemi Website:** www.onsemi.com www.onsemi.com/support/sales 

**==> picture [232 x 43] intentionally omitted <==**

