NVHL110N65S3F

## MOSFET – Power, N-Channel, SUPERFET III, FRFET 650 V, 30 A, 110 m ~~1°~~ NVHL110N65S3F 

## **Description** 

SUPERFET III MOSFET is ON Semiconductor’s brand-new high voltage super-junction (SJ) MOSFET family that is utilizing charge balance technology for outstanding low on-resistance and lower gate charge performance. This advanced technology is tailored to minimize conduction loss, provide superior switching performance, and withstand extreme dv/dt rate. 

Consequently, SUPERFET III MOSFET is very suitable for the various power system for miniaturization and higher efficiency. 

SUPERFET III FRFET MOSFET’s optimized reverse recovery performance of body diode can remove additional component and improve system reliability. 

## **Features** 

- 700 V @ TJ = 150°C 

- Typ. RDS(on) = 93 m 

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VDSS RDS(on) MAX ID MAX<br>650 V 110 m Ω  @ 10 V 30 A<br>ee<br>D<br>G<br>S<br>**----- End of picture text -----**<br>


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N−Channel MOSFET<br>**----- End of picture text -----**<br>


- Ultra Low Gate Charge (Typ. Qg = 58 nC) 

- Low Effective Output Capacitance (Typ. Coss(eff.) = 553 pF) 

- 100% Avalanche Tested 

- AEC−Q101 Qualified and PPAP Capable 

## **Applications** 

- Automotive On Board Charger HEV−EV 

- Automotive DC/DC converter for HEV−EV 

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G<br>D<br>S<br>TO−247 LONG LEADS<br>CASE 340CX<br>**----- End of picture text -----**<br>


## **MARKING DIAGRAM** 

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$Y&Z&3&K<br>NVHL<br>110N65S3F<br>**----- End of picture text -----**<br>


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$Y = ON Semiconductor Logo<br>&Z = Assembly Plant Code<br>&3 = Numeric Date Code<br>&K = Lot Code<br>NVHL110N65S3F = Specific Device Code<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 2 of this data sheet. 

Publication Order Number: **NVHL110N65S3F/D** 

**1** 

© Semiconductor Components Industries, LLC, 2018 **September, 2020 − Rev. 2** 

**NVHL110N65S3F** 

**ABSOLUTE MAXIMUM RATINGS** (TC = 25 ° C, Unless otherwise specified) 

|**ABSOLUTE M**|**AXIMUM RATINGS**(TC= 25°C, Unless other|wise specified)|||
|---|---|---|---|---|
|**Symbol**|**Parameter**||**Value**|**Unit**|
|VDSS|Drain to Source Voltage||650|V|
|VGSS|Gate to Source Voltage|DC|±30|V|
|||AC (f > 1 Hz)|±30|V|
|ID|Drain Current|Continuous (TC= 25°C)|30|A|
|||Continuous (TC= 100°C)|19.5||
|IDM|Drain Current|Pulsed (Note 1)|69|A|
|EAS|Single Pulsed Avalanche Energy (Note 2)||380|mJ|
|EAR|Repetitive Avalanche Energy (Note 1)||2.4|mJ|
|dv/dt|MOSFET dv/dt||100|V/ns|
||Peak Diode Recovery dv/dt (Note 3)||50||
|PD|Power Dissipation|(TC= 25°C)|240|W|
|||Derate Above 25°C|1.92|W/°C|
|TJ, TSTG|Operating and Storage Temperature Range||−55 to +150|°C|
|TL|Maximum Lead Temperature for Soldering, 1/8″f|rom Case for 5 s|300|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Repetitive rating: pulse-width limited by maximum junction temperature. 

2. IAS = 3.5 A, RG = 25 � , starting TJ = 25 ° C. 

3. ISD ≤ 15 A, di/dt ≤ 200 A/ � s, VDD ≤ 400 V, starting TJ = 25 ° C. 

## **THERMAL CHARACTERISTICS** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|R�JC|Thermal Resistance, Junction to Case, Max.|0.52|�C/W|
|R�JA|Thermal Resistance, Junction to Ambient, Max.|40||



## **PACKAGE MARKING AND ORDERING INFORMATION** 

|**Part Number**|**Top Marking**|**Package**|**Packing Method**|**Reel Size**|**Tape Width**|**Quantity**|
|---|---|---|---|---|---|---|
|NVHL110N65S3F|NVHL110N65S3F|TO−247|Tube|N/A|N/A|30 Units|



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**2** 

**NVHL110N65S3F** 

**ELECTRICAL CHARACTERISTICS** (TC = 25 ° C unless otherwise noted) 

|**ELECTRICAL**|**CHARACTERISTICS**(TC= 25°C unl|ess otherwise noted)|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|BVDSS|Drain to Source Breakdown Voltage|VGS= 0 V, ID= 1 mA, TJ= 25�C|650|−|−|V|
|||VGS= 0 V, ID= 10 mA, TJ= 150�C|700|−|−|V|
|�BVDSS/�TJ|Breakdown Voltage Temperature<br>Coefficient|ID= 20 mA, Referenced to 25�C|−|0.61|−|V/�C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 650 V, VGS= 0 V|−|−|10|�A|
|||VDS= 520 V, TC= 125�C|−|44|−||
|IGSS|Gate to Body Leakage Current|VGS=±30 V, VDS= 0 V|−|−|±100|nA|
|**ON CHARACTERISTICS**|||||||
|VGS(th)|Gate Threshold Voltage|VGS= VDS, ID= 0.74 mA|3.0|−|5.0|V|
|RDS(on)|Static Drain to Source On Resistance|VGS= 10 V, ID= 15 A|−|93|110|m�|
|gFS|Forward Transconductance|VDS= 20 V, ID= 15 A|−|17|−|S|
|**DYNAMIC CHARACTERISTICS**|||||||
|Ciss|Input Capacitance|VDS= 400 V, VGS= 0 V, f = 1 MHz|−|2560|−|pF|
|Coss|Output Capacitance||−|50|−|pF|
|Coss(eff.)|Effective Output Capacitance|VDS= 0 V to 400 V, VGS= 0 V|−|553|−|pF|
|Coss(er.)|Energy Related Output Capacitance|VDS= 0 V to 400 V, VGS= 0 V|−|83|−|pF|
|Qg(tot)|Total Gate Charge at 10 V|VDS= 400 V, ID= 15 A, VGS= 10 V<br>(Note 4)|−|58|−|nC|
|Qgs|Gate to Source Gate Charge||−|19|−|nC|
|Qgd|Gate to Drain “Miller” Charge||−|23|−|nC|
|ESR|Equivalent Series Resistance|f = 1 MHz|−|2|−|�|
|**SWITCHING CHARACTERISTICS**|||||||
|td(on)|Turn-On Delay Time|VDD= 400 V, ID= 15 A,<br>VGS= 10 V, Rg= 4.7�<br>(Note 4)|−|29|−|ns|
|tr|Turn-On Rise Time||−|32|−|ns|
|td(off)|Turn-Off Delay Time||−|61|−|ns|
|tf|Turn-Off Fall Time||−|16|−|ns|
|**SOURCE-DRAIN DIODE CHARACTERISTICS**|||||||
|IS|Maximum Continuous Source to Drain|Diode Forward Current|−|−|30|A|
|ISM|Maximum Pulsed Source to Drain Diode Forward Current||−|−|69|A|
|VSD|Source to Drain Diode Forward<br>Voltage|VGS= 0 V, ISD= 15 A|−|−|1.3|V|
|trr|Reverse Recovery Time|VGS= 0 V, ISD= 15 A,<br>dIF/dt = 100 A/�s|−|94|−|ns|
|Qrr|Reverse Recovery Charge||−|343|−|nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Essentially independent of operating temperature typical characteristics. 

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**NVHL110N65S3F** 

## **TYPICAL CHARACTERISTICS** 

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100<br>250  � s Pulse Test VGS = 10 V<br>TC = 25 ° C<br>8.0 V<br>7.0 V<br>6.5 V<br>10 6.0 V<br>5.5 V<br>1<br>0.1 1 10 20<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


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VDS, DRAIN−SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics 25** � **C** 

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100<br>VDS = 20 V<br>250  � s Pulse Test<br>10<br>TJ = 25 ° C<br>1 TJ = 150 ° C TJ = −55 ° C<br>2 3 4 5 6 7 8<br>VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 3. Transfer Characteristics<br>VGS = 0 V<br>10<br>T J  = 150 ° C<br>1<br>0.1 T J = 25 ° C<br>0.01<br>0.001 T J  = −55 ° C<br>0 0.5 1.0 1.5 2.0<br>VSD, BODY DIODE FORWARD VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 5. Body Diode Forward Voltage Variation vs. Source Current and Temperature** 

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100<br>250  � s Pulse Test VGS = 10 V<br>TC = 150 ° C<br>8.0 V<br>7.0 V<br>6.5 V<br>6.0 V<br>10<br>5.5 V<br>1<br>0.5<br>0.2 1 10 20<br>VDS, DRAIN−SOURCE VOLTAGE (V)<br>Figure 2. On−Region Characteristics<br>150 � C<br>0.3<br>0.2<br>VGS = 10 V<br>0.1 V GS  = 20 V<br>0<br>0 10 20 30 40 50 60 70<br>ID, DRAIN CURRENT (A)<br>Figure 4. On−Resistance Variation vs. Drain<br>Current and Gate Voltage<br>100K<br>10K<br>Ciss<br>1K<br>100 Coss<br>VGS = 0 V<br>f = 1 MHz<br>10<br>Crss<br>Ciss = Cgs + Cgd (Cds = shorted)<br>1 Coss = Cds + Cgd<br>Crss = Cgd<br>0.1<br>0.1 1 10 100 1K<br>, DRAIN CURRENT (A)<br>ID<br>) �<br>, DRAIN−SOURCE ON−RESISTANCE (<br>DS(on)<br>R<br>CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


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VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 6. Capacitance Characteristics** 

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**NVHL110N65S3F** 

## **TYPICAL CHARACTERISTICS** 

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10 1.2<br>9 I D  = 15 A VDS = 130 V VGS = 0 V<br>ID = 10 mA<br>8<br>1.1<br>7 V DS  = 400 V<br>6<br>5 1.0<br>4<br>3<br>0.9<br>2<br>1<br>0 0.8<br>0 10 20 30 40 50 60 −75 −25 25 75 125 175<br>QG, TOTAL GATE CHARGE (nC) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 7. Gate Charge Characteristics Figure 8. Breakdown Voltage Variation vs.<br>Temperature<br>3.0 100<br>ID = 15 A<br>2.5<br>VGS = 10 V 100  � s<br>2.0 10<br>RDS(on) Limit<br>1 ms<br>1.5<br>1.0 1 10 ms<br>TC = 25 ° C<br>0.5 R � JC = 0.52 ° C/W<br>Single Pulse<br>100 ms/DC<br>0 0.1<br>−75 −25 25 75 125 175 1 10 100 1000<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−SOURCE VOLTAGE (V)<br>Figure 9. On−Resistance Variation vs. Figure 10. Maximum Safe Operating Area<br>Temperature<br>40 15.0<br>12.5<br>30<br>10.0<br>20 7.5<br>5.0<br>10<br>2.5<br>0 0<br>25 50 75 100 125 150 0 100 200 300 400 500 600<br>TC, CASE TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN−TO−SOURCE<br>DSS<br>, GATE−SOURCE VOLTAGE (V)<br>BV<br>GS<br>V<br>BREAKDOWN VOLTAGE (Normalized)<br>, DRAIN−SOURCE<br>, DRAIN CURRENT (A)<br>RDS(on) ID<br>ON−RESISTANCE (Normalized)<br>J)<br>�<br> (<br>OSS<br>E<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Drain Current vs. Case Temperature** 

**Figure 12. EOSS vs. Drain−to−Source Voltage** 

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**NVHL110N65S3F** 

## **TYPICAL CHARACTERISTICS** 

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1.2 1000<br>1.0<br>0.8<br>0.6 100<br>Current Limited Max<br>0.4<br>0.2<br>0 10<br>0 25 50 75 100 125 150 0.00001 0.0001 0.001 0.01 0.1 1 10<br>TC, CASE TEMPERATURE ( ° C) t, RECTANGULAR PULSE (s)<br>Figure 13. Normalized Power Dissipation vs. Figure 14. Peak Current Capability<br>Case Temperature<br>400 1.2<br>ID = 15 A ID = 3 mA<br>1.1<br>300<br>1.0<br>TA = 150 ° C<br>200 0.9<br>0.8<br>TA = 25 ° C<br>100<br>0.7<br>0 0.6<br>6 7 8 9 10 −75 −25 25 75 125 175<br>VGS, GATE−TO−SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 15. RDS(on) vs. Gate Voltage Figure 16. Normalized Gate Threshold Voltage<br>vs. Temperature<br>100<br>If R = 0<br>t AV  = (L)(I AS )/(1.3*RATED BV DSS  − V DD )<br>If R = /  0<br>t AV  = (L/R)ln[(I  AS *R)/(1.3*RATED BV  DSS  − V DD ) +1]<br>Starting TJ = 25 ° C<br>10<br>Starting TJ = 125 ° C<br>1<br>0.0001 0.001 0.01 0.1 1 10<br>tAV, TIME IN AVALANCHE (ms)<br>NOTE: Refer to Application Notes AN7514 and AN7515<br>, PEAK CURRENT (A)<br>IDM<br>POWER DISSIPATION MULTIPLIER<br>) �<br>, ON−RESISTANCE (m<br>DS(on)<br>R<br>GATE THRESHOLD VOLTAGE (Normalized)<br>, AVALANCHE CURRENT (A)<br>IAS<br>**----- End of picture text -----**<br>


**Figure 17. Unclamped Inductive Switching Capability** 

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**NVHL110N65S3F** 

## **TYPICAL CHARACTERISTICS** 

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2<br>Duty Cycle − Descending Order<br>1<br>Duty Cycle = 0.5<br>0.2<br>0.1<br>0.1<br>0.05<br>0.02<br>0.01<br>Notes:<br>0.01 P DM Z � JC (t) = r(t) x R � JC<br>R � JC = 0.52 ° C/W<br>Single Pulse t1 Peak TJ = PDM x Z � JC (t) + TC<br>t 2 Duty Cycle, D = t 1 /t 2<br>0.001<br>0.00001 0.0001 0.001 0.01 0.1 1 10<br>t, RECTANGULAR PULSE DURATION (sec)<br>RESISTANCE (Normalized)<br>r(t), EFFECTIVE TRANSIENT THERMAL<br>**----- End of picture text -----**<br>


**Figure 18. Transient Thermal Response** 

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**NVHL110N65S3F** 

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VGS<br>RL Qg<br>VGS VDS Qgs Qgd<br>DUT<br>IG = Const.<br>Charge<br>**----- End of picture text -----**<br>


**Figure 19. Gate Charge Test Circuit & Waveform** 

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VDS RL VDS 90% 90% 90%<br>VGS VDD<br>RG<br>10% 10%<br>DUT VGS<br>VGS<br>td(on) tr td(off) tf<br>ton toff<br>**----- End of picture text -----**<br>


**Figure 20. Resistive Switching Test Circuit & Waveforms** 

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L<br>VDS EAS  � [1] 2 � LIAS2<br>BVDSS<br>ID<br>IAS<br>RG VDD ID(t)<br>VGS DUT VDD VDS(t)<br>t<br>p Time<br>t<br>p<br>**----- End of picture text -----**<br>


**Figure 21. Unclamped Inductive Switching Test Circuit & Waveforms** 

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**NVHL110N65S3F** 

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+<br>DUT<br>VSD<br>−<br>ISD<br>L<br>Driver<br>RG<br>Same Type<br>as DUT<br>VDD<br>VGS<br>−dv/dt controlled by RG<br>−ISD controlled by pulse period<br>Gate Pulse Width<br>D  �<br>Gate Pulse Period<br>VGS 10 V<br>(Driver)<br>IFM, Body Diode Forward Current<br>ISD di/dt<br>(DUT)<br>IRM<br>Body Diode Reverse Current<br>Body Diode Recovery dv/dt<br>(DUT)VDS VSD VDD<br>Body Diode<br>Forward Voltage Drop<br>**----- End of picture text -----**<br>


**Figure 22. Peak Diode Recovery dv/dt Test Circuit & Waveforms** 

SUPERFET and FRFET are a registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 

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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**TO−247−3LD** CASE 340CX ISSUE A 

DATE 06 JUL 2020 

**GENERIC MARKING DIAGRAM*** | ~~| op | 3.51 | 3.58 | 3.65 |~~ XXXXX = Specific Device Code A = Assembly Location ) Y = Year ~~| a | 5.34 | 5.46 | 5.58 |~~ q ~~| ob [1.17 | 1.26 | 1.35 |~~ WW = Work Week XXXXXXXXX G = Pb−Free Package AYWWG *This information is generic. Please refer to T ~~T~~ T T ~~T~~ device data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may ~~uy~~ not follow the Generic Marking. . | dpi | ~~13.08|~~ 1281|6.60 | 6.80 ~~~~ |~~ ~~**|**~~ 7.00 ~~~~~ ~ ~~||~~ | Electronic versions are uncontrolled except when accessed directly from the Document Repository. **98AON93302G** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

## **DOCUMENT NUMBER:** 

## **TO−247−3LD** 

**PAGE 1 OF 1** 

## **DESCRIPTION:** 

ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

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