NVE4153NT1G

## NTA4153N, NTE4153N, NVA4153N, NVE4153N 

## MOSFET – Single, N-Channel with ESD Protection, Small Signal, SC-75 and SC-89 20 V, 915 mA 

## **Features** 

- Low RDS(on) Improving System Efficiency 

- Low Threshold Voltage, 1.5 V Rated 

- ESD Protected Gate 

- NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable 

- Pb−Free Packages are Available 

## **Applications** 

- Load/Power Switches 

- Power Supply Converter Circuits 

## **http://onsemi.com** 

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||||
|---|---|---|
|V(BR)DSS|RDS(on) TYP|ID MAX|
|0.127  @ 4.5 V|
|0.170  @ 2.5 V|
|20 V|915 mA|
|0.242  @ 1.8 V|
|0.500  @ 1.5 V|

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3<br>N−Channel MOSFET<br>1 2<br>**----- End of picture text -----**<br>


- Battery Management 

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|||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|•|Portables like Cell Phones, PDAs, Digital Cameras, Pagers, etc.|MARKING DIAGRAM &|
|PIN ASSIGNMENT|
|MAXIMUM RATINGS|(TJ = 25|°|C unless otherwise stated)|3|3|
|Parameter|Symbol|Value|Units|SC−75 / SOT−416|Drain|
|2|CASE 463|
|Drain−to−Source Voltage|VDSS|20|V|1|STYLE 5|
|XX M|
|Gate−to−Source Voltage|VGS|±|6.0|V|
|3|
|ee|Continuous Drain|Steady|TA = 25|°|C|ID|915|mA|SC−89|a|
|ee|Current (Note 1)|State|TA = 85|°|C|660|1|2|CASE 463C|Gate1|Source2|
|Power Dissipation|Steady State|PD|300|mW|XX|= Device Code|
|(Note 1)|M|= Date Code*|
|a|ee|es|
|Pulsed Drain Current|tp =10 s|IDM|1.3|A|(Note: Microdot may be in either location)= Pb−Free Package|
|Se|Operating Junction and Storage Temperature|TJ,|−55 to|°|C|*Date Code orientation may vary depending|||
|eo|TSTG|150|upon manufacturing location.|
|a|Continuous Source Current (Body Diode)|IS|280|mA|SC−75, SC−89|
|Lead Temperature for Soldering Purposes|TL|260|°|C|
|ee|(1/8” from case for 10 s)|Gate|1|
|THERMAL RESISTANCE RATINGS|
|YY|Parameter|Symbol|Value|Units|3|Drain|
|Junction−to−Ambient − Steady State (Note 1)|R|JA|TI|°|C/W|
|SC−75 / SOT−416|416|
|SC−89|400|
|ee|Source|2|
|Stresses exceeding those listed in the Maximum Ratings table may damage the|
|device. If any of these limits are exceeded, device functionality should not be|
|Top View|
|assumed, damage may occur and reliability may be affected.|

**----- End of picture text -----**<br>


1. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 4 of this data sheet. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2014 **May, 2019 − Rev. 7** 

**NTA4153N/D** 

## **NTA4153N, NTE4153N, NVA4153N, NVE4153N** 

**ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise stated) 

|**ELECTRICAL CHARACTERISTICS**|(TJ= 25°C un|less otherwise stated)|less otherwise stated)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= 250�A||20|26||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ||||18.4||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V, VDS= 16 V||||100|nA|
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=±4.5 V||||±1.0|�A|
|**ON CHARACTERISTICS**(Note 2)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||0.45|0.76|1.1|V|
|Negative Threshold Temperature<br>Coefficient|VGS(TH)/TJ||||−2.15||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 4.5 V, ID= 600 mA|||127|230|m�|
|||VGS= 2.5 V, ID= 500 mA|||170|275||
|||VGS= 1.8 V, ID= 350 mA|||242|700||
|||VGS= 1.5 V, ID= 40 mA|||500|950||
|Forward Transconductance|gFS|VDS= 10 V, ID= 400 mA|||1.4||S|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1.0 MHz,<br>VDS= 16 V|||110||pF|
|Output Capacitance|COSS||||16|||
|Reverse Transfer Capacitance|CRSS||||12|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 10 V,<br>ID= 0.2 A|||1.82||nC|
|Threshold Gate Charge|QG(TH)||||0.2|||
|Gate−to−Source Charge|QGS||||0.3|||
|Gate−to−Drain Charge|QGD||||0.42|||
|**SWITCHING CHARACTERISTICS**(Note 3)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDD= 10 V,<br>ID= 0.2 A, RG= 10�|||3.7||ns|
|Rise Time|tr||||4.4|||
|Turn−Off Delay Time|td(OFF)||||25|||
|Fall Time|tf||||7.6|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 200 mA|TJ= 25°C||0.67|1.1|V|
||||TJ= 125°C||0.54|||



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

2. Pulse Test: pulse width ≤ 300 � s, duty cycle ≤ 2%. 

3. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NTA4153N, NTE4153N, NVA4153N, NVE4153N** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** 

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1.2<br>2.0 V<br>1.0<br>VGS = 2.6 V to 5.0 VGS = 2.6 V to 5.0 V = 2.6 V to 5.0 V<br>0.8<br>0.6 1.8 V<br>0.4<br>0.2 1.6 V<br>1.4 V<br>0<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)DS, DRAIN−TO−SOURCE VOLTAGE (VOLTS), DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics<br>0.4<br>VGS = 4.5 VGS = 4.5 V = 4.5 V<br>0.3<br>0.2 TJ = 125J = 125 = 125 ° C<br>TJ = 25J = 25 = 25 ° C<br>0.1<br>TJ = −55J = −55 = −55 ° C<br>0<br>0 0.1 0.2 0.3 0.4 0.5 0.6 0.7<br>ID, DRAIN CURRENT (AMPS)D, DRAIN CURRENT (AMPS) DRAIN CURRENT (AMPS)<br>DRAIN CURRENT (AMPS)<br>ID, D,<br>) �<br>DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),<br>R<br>**----- End of picture text -----**<br>


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1.2<br>2.0 V VDS �  10 V<br>1.0 1.0<br>VGS = 2.6 V to 5.0 VGS = 2.6 V to 5.0 V = 2.6 V to 5.0 V<br>0.8 0.8<br>0.6 1.8 V 0.6<br>0.4 0.4<br>TJ = 125 ° C TJ = 25 ° C<br>0.2 1.6 V 0.2<br>1.4 V TJ = −55 ° C<br>0 0<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 0.4 0.8 1.2 1.6 2.0<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)DS, DRAIN−TO−SOURCE VOLTAGE (VOLTS), DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.4 0.4<br>VGS = 4.5 VGS = 4.5 V = 4.5 V VGS =  2.5 V<br>0.3 0.3<br>TJ = 125 ° C<br>0.2 TJ = 125J = 125 = 125 ° C 0.2 TJ = 25 ° C<br>TJ = 25J = 25 = 25 ° C TJ = −55 ° C<br>0.1 0.1<br>TJ = −55J = −55 = −55 ° C<br>0 0<br>0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7<br>ID, DRAIN CURRENT (AMPS)D, DRAIN CURRENT (AMPS) DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance vs. Drain Current and Figure 4. On−Resistance vs. Drain Current and<br>Temperature Temperature<br>1.6<br>200<br>ID = 0.35 A TJ = 25 ° C<br>VGS = 4.5 V VGS = 0 V<br>1.4 160<br>CISS<br>1.2 120<br>1.0 80<br>0.8 40 COSS<br>CRSS<br>0.6 0<br>−50 −25 0 25 50 75 100 125 150 0 4 8 12 16 20<br>TJ, JUNCTION TEMPERATURE ( ° C) DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>DRAIN CURRENT (AMPS) DRAIN CURRENT (AMPS)<br>ID, D,  ID,<br>) � ) �<br>DRAIN−TO−SOURCE RESISTANCE ( DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),  DS(on),<br>R R<br>DRAIN−TO−SOURCE<br>C, CAPACITANCE (pF)<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**Figure 6. Capacitance Variation** 

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**3** 

**NTA4153N, NTE4153N, NVA4153N, NVE4153N** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
5<br>QT<br>4<br>3<br>QGS QGD<br>2<br>1 TIDA = 25= 0.2 A ° C<br>0<br>0 0.4 0.8 1.2 1.6 2.0<br>QG, TOTAL GATE CHARGE (nC)<br>GATE−TO−SOURCE VOLTAGE (VOLTS)<br>GS,<br>V<br>**----- End of picture text -----**<br>


**Figure 7. Gate−to−Source Voltage vs. Total Gate Charge** 

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0.6<br>VGS = 0 V<br>0.5<br>0.4<br>0.3<br>0.2 TJ = 125 ° C<br>0.1<br>TJ = 25 ° C<br>0<br>0 0.2 0.4 0.6 0.8<br>VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>, SOURCE CURRENT (AMPS)<br>IS<br>**----- End of picture text -----**<br>


**Figure 8. Diode Forward Voltage vs. Current** 

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1.0<br>D = 0.5<br>0.2<br>0.1<br>0.1<br>0.05<br>0.02<br>0.01 0.01<br>SINGLE PULSE<br>0.001<br>0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000<br>t, TIME (s)<br>r(t), NORMALIZED TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 9. Normalized Thermal Response** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**||||
|---|---|---|---|
|**Device**|**Marking**|**Package**|**Shipping**†|
|NTA4153NT1|TR|SC−75 / SOT−416|3000 / Tape & Reel|
|NTA4153NT1G|TR|SC−75 / SOT−416<br>(Pb−Free)|3000 / Tape & Reel|
|NTE4153NT1G|TP|SC−89<br>(Pb−Free)|3000 / Tape & Reel|
|NVA4153NT1G|VR|SC−75 / SOT−416<br>(Pb−Free)|3000 / Tape & Reel|
|NVE4153NT1G|VP|SC−89<br>(Pb−Free)|3000 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

**http://onsemi.com** 

**4** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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3 oe 2<br>1<br>SCALE 4:1<br>**----- End of picture text -----**<br>


**SC−75/SOT−416** CASE 463−01 ISSUE G 

DATE 07 AUG 2015 

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−E− NOTES:<br>1. DIMENSIONING AND TOLERANCING PER ANSI<br>T o T Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>2<br>MILLIMETERS INCHES<br>3 DIM MIN NOM MAX MIN NOM MAX<br>e −D− A 0.70 0.80 0.90 0.027 0.031 0.035<br>1 A1 0.00 0.05 0.10 0.000 0.002 0.004<br>b 3 PL b 0.15 0.20 0.30 0.006 0.008 0.012<br>0.20 (0.008) a M D HE 0.20 (0.008) E CDE 0.101.550.70 0.151.600.80 0.251.650.90 0.0040.0610.027 0.0060.0630.031 0.0100.0650.035<br>e 1.00 BSC 0.04 BSC<br>L 0.10 0.15 0.20 0.004 0.006 0.008<br>q a—D = B HE 1.50 1.60 BE 1.70 0.060 0.063 0.067<br>C<br>A GENERIC<br>MARKING DIAGRAM*<br>L A1<br>XX M<br>STYLE 1: STYLE 2: STYLE 3:<br>PIN 1. BASE PIN 1. ANODE PIN 1. ANODE<br> 2. EMITTER Jo  2. N/C  2. ANODE 1 a<br> 3. COLLECTOR  3. CATHODE  3. CATHODE<br>XX = Specific Device Code<br>STYLE 4: STYLE 5: M = Date Code<br>PIN 1. CATHODE PIN 1. GATE<br> 2. CATHODE  2. SOURCE = Pb−Free Package<br> 3. ANODE  3. DRAIN *This information is generic. Please refer to<br>device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ ”,<br>may or may not be present.<br>SOLDERING FOOTPRINT*<br>0.356<br>0.014<br>aT<br>1.803 0.787<br>0.071 0.031<br>7 Mm _<br>_ 0.508 a<br>0.020 1.000<br>0.039<br>SCALE 10:1 mm<br>(—) inches<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


**PAGE 1 OF 1** ~~—_~~ 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB15184C** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SC−75/SOT−416 PAGE 1 OF 1** ~~[[-_}__—__§_—___—_~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **SC−89, 3 LEAD CASE 463C−03 ISSUE C** 

## **DATE 31 JUL 2003** 

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SCALE 4:1<br>**----- End of picture text -----**<br>


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A<br>−X−<br>3<br>B −Y− S<br>1 2<br>W K s<br>Be G<br>2 PL<br>D 3 PL<br>a 0.08 (0.003) M X Y<br>M N<br>J<br>C<br>−T− SEATINGPLANE<br>aa, po<br>STYLE 1: STYLE 2: STYLE 3: STYLE 4:<br>PIN 1. BASE PIN 1. ANODE PIN 1. ANODE PIN 1. CATHODE<br> 2. EMITTER  2. N/C  2. ANODE  2. CATHODE<br> 3. COLLECTOR  3. CATHOD-  3. CATHODE  3. ANODE<br>E<br>**----- End of picture text -----**<br>


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H H<br>L<br>58 G<br>RECOMMENDED PATTERN<br>OF SOLDER PADS<br>**----- End of picture text -----**<br>


NOTES: 

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 

2. CONTROLLING DIMENSION: MILLIMETERS 

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 

4. 463C−01 OBSOLETE, NEW STANDARD 463C−02. 

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MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>A 1.50 1.60 1.70 0.059 0.063 0.067<br>B 0.75 0.85 0.95 0.030 0.034 0.040<br>C 0.60 0.70 0.80 0.024 0.028 0.031<br>D 0.23 0.28 0.33 0.009 0.011 0.013<br>G 0.50 BSC 0.020 BSC<br>H 0.53 REF 0.021 REF<br>J 0.10 0.15 0.20 0.004 0.006 0.008<br>K 0.30 0.40 0.50 0.012 0.016 0.020<br>L 1.10 REF 0.043 REF<br>M −−− −−− 10  _ −−− −−− 10  _<br>NS 1.50−−− 1.60−−− 1.7010  _ 0.059−−− 0.063−−− 0.06710  _<br>**----- End of picture text -----**<br>


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GENERIC<br>MARKING DIAGRAM*<br>3<br>xx  D<br>1 _ 2<br>xx = Specific Device Code<br>D = Date Code<br>*This information is generic. Please refer to<br>device data sheet for actual part<br>marking.<br>**----- End of picture text -----**<br>


Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON11472D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SC−89, 3 LEAD PAGE 1 OF 1** ~~er~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

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© Semiconductor Components Industries, LLC, 2019 

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