NVD3055L170T4G

NTD3055L170, NVD3055L170 

## MOSFET – Power, N-Channel, Logic Level, DPAK/IPAK 9.0 A, 60 V 

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## **9.0 AMPERES, 60 VOLTS R = 170 m DS(on)** 

Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. 

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D<br>N−Channel<br>G<br>S<br>4<br>4<br>1<br>1 » [2] *<br>3 2 3<br>DPAK IPAK<br>CASE 369C CASE 369D<br>(Surface Mounted) (Straight Lead)<br>STYLE 2 STYLE 2<br>**----- End of picture text -----**<br>


## **Features** 

- NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable 

- These are Pb−Free Devices 

## **Typical Applications** 

- Power Supplies 

- Converters 

- Power Motor Controls 

- Bridge Circuits 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

**DPAK Rating Symbol Value Unit CASE 369C** Drain−to−Source Voltage VDSS 60 Vdc **(Surface Mounted)** ~~Ee~~ Drain−to−Gate Voltage (RGS = 10 M ) VDGR 60 Vdc **STYLE 2** Gate−to−Source Voltage Vdc − Continuous VGS ± 15 **MARKING DIAGRAMS** ~~Sean~~ − Non−repetitive (tp 10 ms) VGS ± 20 **& PIN ASSIGNMENTS** ~~Rr~~ Drain Current Adc − Continuous @ TA = 25 ° C ID 9.0 1 − Gate AYWW − Continuous @ TA = 100 ° C ID 3.0 2 − Drain 31 − Single Pulse (tp 10 s) IDM 27 Apk 3 − Source 70LG Total Power Dissipation @ TA = 25 ° C PD 28.5 W ~~eee~~ Derate above 25 ° C ~~ae~~ 0.19 W/ ° C Total Power Dissipation @ TTotal Power Dissipation @ TAA = 25 = 25 °° C (Note 1)C (Note 2) 2.11.5 WW 2 − Drain1 − Gate AYWW3131 Operating and Storage Temperature Range TJ, Tstg −55 to ° C 3 − Source 70LG ~~“ttt~~ 175 ~~a~~ ry ~~ee~~ Single Pulse Drain−to−Source AvalancheEnergy − Starting TJ = 25 ° C E ~~ee~~ AS 30 mJ AYY = Assembly Location*=  Year=  Year (VDD = 25 Vdc, VGS = 5.0 Vdc, WW = Work Week ~~es~~ L = 1.0 mH, IL(pk) = 7.75 A, VDS = 60 Vdc) 3170L = Device Code Thermal Resistance ° C/W G = Pb−Free Package − Junction−to−Case R JC 5.2 − Junction−to−Ambient (Note 1) R JA 71.4 − Junction−to−Ambient (Note 2) R JA 100 ~~po~~ Maximum Lead Temperature for SolderingPurposes, 1/8 ″ from case for 10 seconds TL 260 ° C code may be blank. ~~eeee~~ Stresses exceeding those listed in the Maximum Ratings table may damage the **ORDERING INFORMATION** device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **MARKING DIAGRAMS** 

**& PIN ASSIGNMENTS** 

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1 − Gate<br>AYWW 4<br>2 − Drain 31 Drain<br>70LG<br>3 − Source<br>1 − Gate<br>4<br>2 − Drain1 − Gate AYWW3131<br>Drain<br>70LG<br>3 − Source<br>a ry<br>AYY = Assembly Location*=  Year=  Year<br>WW = Work Week<br>3170L = Device Code<br>G = Pb−Free Package<br>**----- End of picture text -----**<br>


* The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. 

Publication Order Number: **NTD3055L170/D** 

**1** 

© Semiconductor Components Industries, LLC, 2014 **October, 2024 − Rev. 8** 

**NTD3055L170, NVD3055L170** 

1. When surface mounted to an FR4 board using 0.5 sq in pad size. 2. When surface mounted to an FR4 board using minimum recommended pad size. 

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**2** 

**NTD3055L170, NVD3055L170** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)||||||
|---|---|---|---|---|---|---|
|**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|Drain−to−Source Breakdown Voltage (Note 3)<br>(VGS= 0 Vdc, ID= 250�Adc)<br>Temperature Coefficient (Positive)||V(BR)DSS|60<br>−|−<br>53.6|−<br>−|Vdc<br>mV/°C|
|Zero Gate Voltage Drain Current<br>(VDS= 60 Vdc, VGS= 0 Vdc)<br>(VDS= 60 Vdc, VGS= 0 Vdc, TJ= 150°C)||IDSS|−<br>−|−<br>−|1.0<br>10|�Adc|
|Gate−BodyLeakage Current (VGS=±15 Vdc, VDS= 0 Vdc)||IGSS|−|−|±100|nAdc|
|**ON CHARACTERISTICS**(Note 3)|||||||
|Gate Threshold Voltage (Note 3)<br>(VDS= VGS, ID= 250�Adc)<br>Threshold Temperature Coefficient (Negative)||VGS(th)|1.0<br>−|1.7<br>4.2|2.0<br>−|Vdc<br>mV/°C|
|Static Drain−to−Source On−Resistance (Note 3)<br>(VGS= 5.0 Vdc, ID= 4.5 Adc)||RDS(on)|−|153|170|m�|
|Static Drain−to−Source On−Voltage (Note 3)<br>(VGS= 5.0 Vdc, ID= 9.0 Adc)<br>(VGS= 5.0 Vdc, ID= 4.5 Adc, TJ= 150°C)||VDS(on)|−<br>−|1.8<br>1.3|2.1<br>−|Vdc|
|Forward Transconductance (Note 3) (VDS= 8.0 Vdc, ID= 6.0 Adc)||gFS|−|7.3|−|mhos|
|**DYNAMIC CHARACTERISTICS**|||||||
|Input Capacitance|(VDS= 25 Vdc, VGS= 0 Vdc,<br>f = 1.0 MHz)|Ciss|−|195|275|pF|
|Output Capacitance||Coss|−|70|100||
|Transfer Capacitance||Crss|−|29|42||
|**SWITCHING CHARACTERISTICS**(Note 4)|||||||
|Turn−On Delay Time|(VDD= 30 Vdc, ID= 9.0 Adc,<br>VGS= 5.0 Vdc,<br>RG= 9.1�) (Note 3)|td(on)|−|9.7|20|ns|
|Rise Time||tr|−|69|150||
|Turn−Off Delay Time||td(off)|−|10|20||
|Fall Time||tf|−|38|80||
|Gate Charge|(VDS= 48 Vdc, ID= 9.0 Adc,<br>VGS= 5.0 Vdc) (Note 3)|QT|−|4.7|10|nC|
|||Q1|−|1.4|−||
|||Q2|−|2.9|−||
|**SOURCE−DRAIN DIODE CHARACTERISTICS**|||||||
|Forward On−Voltage|(IS= 9.0 Adc, VGS= 0 Vdc) (Note 3)<br>(IS= 9.0 Adc, VGS= 0 Vdc, TJ= 150°C)|VSD|−<br>−|0.98<br>0.85|1.25<br>−|Vdc|
|Reverse Recovery Time|(IS= 9.0 Adc, VGS= 0 Vdc,<br>dIS/dt = 100 A/�s) (Note 3)|trr|−|29.8|−|ns|
|||ta|−|17.6|−||
|||tb|−|12.2|−||
|Reverse RecoveryStored Charge||QRR|−|0.031|−|�C|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 

4. Switching characteristics are independent of operating junction temperatures. 

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**3** 

**NTD3055L170, NVD3055L170** 

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20 16<br>VGS = 10 V VDS ≥  10 V<br>16<br>8 V 5 V 12<br>6 V<br>12<br>8<br>4 V<br>8<br>3.5 V 4<br>4 TJ = 25 ° C<br>3 V TJ = 100 ° C TJ = −55 ° C<br>0 0<br>0 1 2 3 4 5 6 7 8 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.35 0.35<br>VGS = 10 V<br>VGS = 15 V<br>0.3 0.3<br>0.25 TJ = 100 ° C 0.25<br>TJ = 100 ° C<br>0.2 TJ = 25 ° C 0.2<br>0.15 0.15 TJ = 25 ° C<br>TJ = −55 ° C<br>0.1 0.1<br>0.05 0.05 TJ = −55 ° C<br>0 0<br>4 6 8 10 12 14 16 18 4 8 12 16 20 24<br>ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current<br>Gate−to−Source Voltage and Gate Voltage<br>2.2 1000<br>ID = 4.5 A VGS = 0 V<br>2 V GS = 5 V<br>TJ = 150 ° C<br>1.8<br>100<br>1.6<br>1.4 TJ = 125 ° C<br>1.2<br>10<br>1<br>TJ = 100 ° C<br>0.8<br>0.6 1<br>−50 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 5. On−Resistance Variation with Figure 6. Drain−to−Source Leakage Current<br>Temperature versus Voltage<br>, DRAIN CURRENT (AMPS) , DRAIN CURRENT (AMPS)<br>ID ID<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>(NORMALIZED) IDSS<br>, DRAIN−TO−SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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**4** 

**NTD3055L170, NVD3055L170** 

## **POWER MOSFET SWITCHING** 

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (�t) are determined by how fast the FET input capacitance can be charged by current from the generator. 

The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used.  In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that 

t = Q/IG(AV) 

During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP.  Therefore, rise and fall times may be approximated by the following: 

tr = Q2 x RG/(VGG − VGSP) 

tf = Q2 x RG/VGSP 

## where 

VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance 

and Q2 and VGSP are read from the gate charge curve. 

During the turn−on and turn−off delay times, gate current is not constant.  The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network.  The equations are: 

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). 

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. 

The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements.  If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components.  Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load.  Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 

td(on) = RG Ciss In [VGG/(VGG − VGSP)] 

td(off) = RG Ciss In (VGG/VGSP) 

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700<br>VDS = 0 V VGS = 0 V TJ = 25 ° C<br>600<br>500 Ciss<br>400<br>300 Crss<br>Ciss<br>200<br>100 Coss<br>0 Crss<br>10 5 0 5 10 15 20 25<br>VGS VDS<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


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GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

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**5** 

**NTD3055L170, NVD3055L170** 

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6 1000<br>Q T<br>5 Q1 Q2<br>4 100<br>tr<br>3 tf<br>VGS<br>td(off)<br>2 10<br>td(on) VDS = 30 V<br>1 ID = 9 A ID = 9 A<br>TJ = 25 ° C VGS = 5 V<br>0 1<br>0 1 2 3 4 5 1 10 100<br>QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)<br>Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time<br>Voltage versus Total Charge Variation versus Gate Resistance<br>DRAIN−TO−SOURCE DIODE CHARACTERISTICS<br>10<br>VGS = 0 V<br>TJ = 25 ° C<br>8<br>6<br>4<br>2<br>0<br>0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96<br>VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>Figure 10. Diode Forward Voltage versus Current<br>SAFE OPERATING AREA<br>t, TIME (ns)<br>VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>IS, SOURCE CURRENT (AMPS)<br>**----- End of picture text -----**<br>


The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” 

Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 �s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(R�JC). 

A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For 

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. 

Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 

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**NTD3055L170, NVD3055L170** 

## **SAFE OPERATING AREA** 

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100 32<br>V GS  = 15 V  ID = 7.75 A<br>SINGLE PULSE<br>TC = 25 ° C<br>24<br>10<br>10  � s<br>16<br>100  � s<br>1 ms<br>1<br>RDS(on) LIMIT 8<br>THERMAL LIMIT<br>10 ms<br>PACKAGE LIMIT<br>dc<br>0.1 0<br>0.1 1 10 100 25 50 75 100 125 150 175<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus<br>Safe Operating Area Starting Junction Temperature<br>10<br>D = 0.5<br>0.2<br>1 0.1 P(pk)<br>0.05 R � JC(t) = r(t) R � JC<br>D CURVES APPLY FOR POWER<br>0.01 PULSE TRAIN SHOWN<br>t1 READ TIME AT t1<br>t2 TJ(pk) − TC = P(pk) R � JC(t)<br>SINGLE PULSE DUTY CYCLE, D = t1/t2<br>001<br>0.00001 0.0001 0.001 0.01 0.1 1 10<br>t, TIME ( � s)<br>Figure 13. Thermal Response<br>di/dt<br>IS<br>t rr<br>ta t b<br>TIME<br>t p 0.25 IS<br>IS<br>ID, DRAIN CURRENT (AMPS)<br>AVALANCHE ENERGY (mJ)<br>EAS, SINGLE PULSE DRAIN−TO−SOURCE<br>(NORMALIZED)<br>r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 14. Diode Reverse Recovery Waveform** 

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**7** 

**NTD3055L170, NVD3055L170** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package**|**Shipping**†|
|NTD3055L170G|DPAK<br>(Pb−Free)|75 Units / Rail|
|NTD3055L170−1G|IPAK<br>(Pb−Free)|75 Units / Rail|
|NTD3055L170T4G|DPAK<br>(Pb−Free)|2500 / Tape & Reel|
|NVD3055L170T4G*|DPAK<br>(Pb−Free)|2500 / Tape & Reel|
|NVD3055L170T4G−VF01*|DPAK<br>(Pb−Free)|2500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

*NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable 

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**8** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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4<br>1 [2]<br>3<br>SCALE 1:1<br>**----- End of picture text -----**<br>


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DPAK−3 6.10x6.54x2.28, 2.29P<br>CASE 369C<br>ISSUE K<br>**----- End of picture text -----**<br>


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DATE 14 MAY 2026<br>**----- End of picture text -----**<br>


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Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10527D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: DPAK−3 6.10x6.54x2.28, 2.29P PAGE 1 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2011 

DATE 13 MAY 2026 

**DPAK−3 6.10x6.54x2.28, 2.29P** CASE 369C ISSUE K 

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GENERIC<br>MARKING DIAGRAM*<br>XXXXXXG AYWW<br>ALYWW XXX<br>XXXXXG<br>IC Discrete<br>XXXXXX = Device Code<br>A = Assembly Location<br>L = Wafer Lot<br>Y =  Year<br>WW = Work Week<br>G = Pb−Free Package<br>**----- End of picture text -----**<br>


*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

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STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:<br>PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE<br>2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 2. ANODE<br>3. EMITTER 3. SOURCE 3. ANODE 3. GATE 3. CATHODE<br>4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 4. ANODE<br>STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10:<br>PIN 1. MT1 PIN 1. GATE PIN 1. N/C PIN 1. ANODE PIN 1. CATHODE<br>2. MT2 2. COLLECTOR 2. CATHODE 2. CATHODE 2. ANODE<br>3. GATE 3. EMITTER 3. ANODE 3. RESISTOR ADJUST 3. CATHODE<br>4. MT2 4. COLLECTOR 4. CATHODE 4. CATHODE 4. ANODE<br>**----- End of picture text -----**<br>


Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10527D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: DPAK−3 6.10x6.54x2.28, 2.29P PAGE 2 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

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