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NVD3055-150T4G
Power MOSFET, N Channel, 60 V, 9 A, 0.122 ohm, TO-252 (DPAK), Surface Mount
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- Manufacturer: ONSEMI
- Product type: Single MOSFETs
- No. of Pins: 3Pins
- Channel Type: N Channel
- Qualification: AEC-Q101
- Power Dissipation: 28.8W
- Transistor Mounting: Surface Mount
- Transistor Polarity: N Channel
- Power Dissipation Pd: 28.8W
- Rds(on) Test Voltage: 10V
- On Resistance Rds(on): 0.122ohm
- Transistor Case Style: TO-252 (DPAK)
- Drain Source Voltage Vds: 60V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 9A
- Drain Source On State Resistance: 0.122ohm
- Automotive Qualification Standard: AEC-Q101
- Gate Source Threshold Voltage Max: 3V
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 0.282 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
NTD3055-150, NVD3055-150 ## Power MOSFET **9.0 A, 60 V, N−Channel DPAK/IPAK** Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. ## **www.onsemi.com** ## **9.0 AMPERES, 60 VOLTS RDS(on) = 122 m (Typ)** ## **Features** - NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable **==> picture [484 x 455] intentionally omitted <==** **----- Start of picture text -----**<br> |||||||||| |---|---|---|---|---|---|---|---|---| |Unique Site and Control Change Requirements; AEC−Q101|D| |Qualified and PPAP Capable| |•|These Devices are Pb−Free and are RoHS Compliant| |N−Channel| |Typical Applications|G| |•|Power Supplies| |•|Converters|S| |•|Power Motor Controls|4| |•|Bridge Circuits| |4| |MAXIMUM RATINGS|(TJ = 25|°|C unless otherwise noted)| |1| |1|[2]| |Rating|Symbol|Value|Unit|3|2 3| |Drain−to−Source Voltage|VDSS|60|Vdc|DPAK|IPAK| |ee oe|CASE 369C|»|CASE 369D|,| |Drain−to−Gate Voltage (RGS = 10 M|)|VDGR|60|Vdc| |ee| |<|(SURFACE MOUNT)|(STRAIGHT LEAD)| |Gate−to−Source Voltage|Vdc|STYLE 2|STYLE 2| |− Continuous|VGS|20| |ee|− Non−repetitive (tp|10 ms)|VGS|30|MARKING DIAGRAMS| |Drain Current|Adc|& PIN ASSIGNMENTS| |− Continuous @ TA = 25|°|C|ID|9.0| |− Continuous @ TA = 100|°|C|ID|3.0|4|4| |oo|− Single Pulse (tp|10 s)|IDM|27|Apk|Drain|Drain| |Total Power Dissipation @ TA = 25|°|C|PD|28.8|W| |Derate above 25|°|C|0.19|W/|°|C| |Total Power Dissipation @ TA = 25|°|C (Note 1)|2.1|W| |Total Power Dissipation @ TA = 25|°|C (Note 2)|1.5|W| |ttt|Operating and Storage Temperature Range|TJ, Tstg|−55 to 175|°|C|d|2|G| |1|3| |—|Single Pulse Drain−to−Source Avalanche|TL|EAS|30|mJ|Drain| |Energy − Starting TJ = 25|°|C|Gate|Source|1|2|3| |(VDD = 25 Vdc, VGS = 10 Vdc,|Gate|Drain|Source| |L = 1.0 mH, IL(pk) = 7.75 A, VDS = 60 Vdc)| |ae|TU| |Thermal Resistance|°|C/W|A|= Assembly Location*| |− Junction−to−Case|R|JC|5.2|3150|= Device Code| |− Junction−to−Ambient (Note 1)|R|JA|71.4|Y|= Year| |ne|− Junction−to−Ambient (Note 2)|R|JA|100|WW|= Work Week| |Maximum Lead Temperature for Soldering|TL|260|°|C|G|= Pb−Free Package| |ee|Purposes, 1/8|″|from case for 10 seconds|ee|ee|* The Assembly Location code (A) is front sideoptional. In cases where the Assembly Location isoptional. In cases where the Assembly Location is| |Stresses exceeding those listed in the Maximum Ratings table may damage the| |device. If any of these limits are exceeded, device functionality should not be|stamped in the package, the front side assembly| |assumed, damage may occur and reliability may be affected.|code may be blank.| **----- End of picture text -----**<br> * The Assembly Location code (A) is front sideoptional. In cases where the Assembly Location isoptional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. 1. When surface mounted to an FR4 board using 0.5 sq in pad size. 2. When surface mounted to an FR4 board using minimum recommended pad size. ## **ORDERING INFORMATION** See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: **NTD3055−150/D** **1** © Semiconductor Components Industries, LLC, 2014 **May, 2017 − Rev. 7** **NTD3055−150, NVD3055−150** ## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise not|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise not|ed)||||| |---|---|---|---|---|---|---| |**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**||||||| |Drain−to−Source Breakdown Voltage (Note 3)<br>(VGS= 0 Vdc, ID= 250�Adc)<br>Temperature Coefficient (Positive)||V(BR)DSS|60<br>−|−<br>70.2|−<br>−|Vdc<br>mV/°C| |Zero Gate Voltage Drain Current<br>(VDS= 60 Vdc, VGS= 0 Vdc)<br>(VDS= 60 Vdc, VGS= 0 Vdc, TJ= 150°C)||IDSS|−<br>−|−<br>−|1.0<br>10|�Adc| |Gate−Body Leakage Current (VGS=±20 Vdc, VDS= 0 Vdc)||IGSS|−|−|±100|nAdc| |**ON CHARACTERISTICS**(Note 3)||||||| |Gate Threshold Voltage (Note 3)<br>(VDS= VGS, ID= 250�Adc)<br>Threshold Temperature Coefficient (Negative)||VGS(th)|2.0<br>−|3.0<br>6.4|4.0<br>−|Vdc<br>mV/°C| |Static Drain−to−Source On−Resistance (Note 3)<br>(VGS= 10 Vdc, ID= 4.5 Adc)||RDS(on)|−|122|150|m�| |Static Drain−to−Source On−Voltage (Note 3)<br>(VGS= 10 Vdc, ID= 9.0 Adc)<br>(VGS= 10 Vdc, ID= 4.5 Adc, TJ= 150°C)||VDS(on)|−<br>−|1.4<br>1.1|1.9<br>−|Vdc| |Forward Transconductance (Note 3) (VDS= 7.0 Vdc, ID= 6.0 Adc)||gFS|−|5.4|−|mhos| |**DYNAMIC CHARACTERISTICS**||||||| |Input Capacitance|(VDS= 25 Vdc, VGS= 0 Vdc,<br>f = 1.0 MHz)|Ciss|−|200|280|pF| |Output Capacitance||Coss|−|70|100|| |Transfer Capacitance||Crss|−|26|40|| |**SWITCHING CHARACTERISTICS**(Note 4)||||||| |Turn−On Delay Time|(VDD= 48 Vdc, ID= 9.0 Adc,<br>VGS= 10 Vdc,<br>RG= 9.1�) (Note 3)|td(on)|−|11.2|25|ns| |Rise Time||tr|−|37.1|80|| |Turn−Off Delay Time||td(off)|−|12.2|25|| |Fall Time||tf|−|23|50|| |Gate Charge|(VDS= 48 Vdc, ID= 9.0 Adc,<br>VGS= 10 Vdc) (Note 3)|QT|−|7.1|15|nC| |||Q1|−|1.7|−|| |||Q2|−|3.5|−|| |**SOURCE−DRAIN DIODE CHARACTERISTICS**||||||| |Forward On−Voltage|(IS= 9.0 Adc, VGS= 0 Vdc) (Note 3)<br>(IS= 19 Adc, VGS= 0 Vdc, TJ=<br>150°C)|VSD|−<br>−|0.98<br>0.86|1.20<br>−|Vdc| |Reverse Recovery Time|(IS= 9.0 Adc, VGS= 0 Vdc,<br>dIS/dt = 100 A/�s) (Note 3)|trr|−|28.9|−|ns| |||ta|−|21.6|−|| |||tb|−|7.3|−|| |Reverse Recovery Stored Charge||QRR|−|0.036|−|�C| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. **www.onsemi.com** **2** **NTD3055−150, NVD3055−150** **==> picture [236 x 173] intentionally omitted <==** **----- Start of picture text -----**<br> 20<br>VGS = 10 V<br>16<br>VGS = 9 V<br>VGS = 8 V VGS = 7 V<br>12<br>8 VGS = 6 V<br>4 VGS = 5 V<br>0<br>0 1 2 3 4 5 6 7 8<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>, DRAIN CURRENT (AMPS)<br>ID<br>**----- End of picture text -----**<br> **Figure 1. On−Region Characteristics** **==> picture [234 x 173] intentionally omitted <==** **----- Start of picture text -----**<br> 20<br>VDS ≥ 10 V<br>16<br>12<br>8<br>TJ = 25 ° C<br>4<br>T J = 100 ° C<br>0 TJ = −55 ° C<br>3 4 5 6 7 8 9<br>VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>, DRAIN CURRENT (AMPS)<br>ID<br>**----- End of picture text -----**<br> **Figure 2. Transfer Characteristics** **==> picture [489 x 416] intentionally omitted <==** **----- Start of picture text -----**<br> 0.5 0.5<br>V GS = 10 V V GS = 15 V<br>0.4 0.4<br>0.3 TJ = 100 ° C 0.3<br>TJ = 100 ° C<br>0.2 T J = 25 ° C 0.2 TJ = 25 ° C<br>0.1 TJ = −55 ° C 0.1 T J = −55 ° C<br>0 0<br>0 4 8 12 16 20 24 0 4 8 12 16 20 24<br>ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current<br>Gate−To−Source Voltage and Gate Voltage<br>2.2 1000<br>2 ID = 4.5 A VGS = 0 V<br>VGS = 10 V TJ = 150 ° C<br>1.8<br>100<br>1.6<br>TJ = 125 ° C<br>1.4<br>1.2<br>10<br>1 TJ = 100 ° C<br>0.8<br>0.6 1<br>−50 −25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>) � ) �<br>, DRAIN−TO−SOURCE RESISTANCE ( , DRAIN−TO−SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>(NORMALIZED)<br>IDSS<br>, DRAIN−TO−SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br> **Figure 5. On−Resistance Variation with Temperature** **Figure 6. Drain−To−Source Leakage Current versus Voltage** **www.onsemi.com** **3** **NTD3055−150, NVD3055−150** **==> picture [241 x 172] intentionally omitted <==** **----- Start of picture text -----**<br> 560<br>VDS = 0 V VGS = 0 V TJ = 25 ° C<br>480 Ciss<br>400<br>320 Crss<br>240 Ciss<br>160<br>Coss<br>80<br>Crss<br>0<br>10 5 VGS 0 VDS 5 10 15 20 25<br>GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br> **Figure 7. Capacitance Variation** **==> picture [231 x 174] intentionally omitted <==** **----- Start of picture text -----**<br> 12<br>Q T<br>10<br>8 VGS<br>Q1 Q2<br>6<br>4<br>2 ID = 9 A<br>TJ = 25 ° C<br>0<br>0 1 2 3 4 5 6 7 8<br>Qg, TOTAL GATE CHARGE (nC)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br> **Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge** **==> picture [242 x 158] intentionally omitted <==** **----- Start of picture text -----**<br> 100<br>VDS = 30 V<br>ID = 9 A<br>VGS = 10 V<br>tr<br>tf<br>td(off)<br>td(on)<br>10<br>1 10 100<br>t, TIME (ns)<br>**----- End of picture text -----**<br> **==> picture [104 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> RG, GATE RESISTANCE ( � )<br>**----- End of picture text -----**<br> **Figure 9. Resistive Switching Time Variation versus Gate Resistance** **==> picture [234 x 175] intentionally omitted <==** **----- Start of picture text -----**<br> 10<br>VGS = 0 V<br>TJ = 25 ° C<br>8<br>6<br>4<br>2<br>0<br>0.6 0.68 0.76 0.84 0.92 1<br>VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>, SOURCE CURRENT (AMPS)<br>IS<br>**----- End of picture text -----**<br> **Figure 10. Diode Forward Voltage versus Current** **==> picture [242 x 176] intentionally omitted <==** **----- Start of picture text -----**<br> 100<br>V GS = 20 V<br>SINGLE PULSE<br>TC = 25 ° C<br>10<br>10 � s<br>100 � s<br>1 ms<br>1 10 ms<br>RDS(on) LIMIT<br>THERMAL LIMIT<br>PACKAGE LIMIT dc<br>0.1<br>0.1 1 10 100<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>, DRAIN CURRENT (AMPS)<br>ID<br>**----- End of picture text -----**<br> **Figure 11. Maximum Rated Forward Biased Safe Operating Area** **==> picture [245 x 178] intentionally omitted <==** **----- Start of picture text -----**<br> 32<br>ID = 7.75 A<br>24<br>16<br>8<br>0<br>25 50 75 100 125 150 175<br>TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>AVALANCHE ENERGY (mJ)<br>, SINGLE PULSE DRAIN−TO−SOURCE<br>AS<br>E<br>**----- End of picture text -----**<br> **Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature** **www.onsemi.com** **4** **NTD3055−150, NVD3055−150** **==> picture [491 x 170] intentionally omitted <==** **----- Start of picture text -----**<br> 10<br>D = 0.5<br>0.2<br>1<br>0.1<br>P(pk)<br>0.05<br>0.01 t1<br>t2<br>SINGLE PULSE<br>DUTY CYCLE, D = t1/t2<br>0.1<br>0.00001 0.0001 0.001 0.01 0.1 1 10<br>t, TIME (s)<br> THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT<br>**----- End of picture text -----**<br> **Figure 13. Thermal Response** ## **ORDERING INFORMATION** |**ORDERING INFORMATION**||| |---|---|---| |**Device**|**Package**|**Shipping**†| |NTD3055−150G|DPAK<br>(Pb−Free)|75 Units / Rail| |NTD3055−150−1G|IPAK<br>(Pb−Free)|75 Units / Rail| |NTD3055−150T4G|DPAK<br>(Pb−Free)|2500 / Tape & Reel| |NTD3055−150T4H|DPAK<br>(Halide−Free)|2500 / Tape & Reel| |NVD3055−150T4G*|DPAK<br>(Pb−Free)|2500 / Tape & Reel| |NVD3055−150T4G−VF01|DPAK<br>(Pb−Free)|2500 / Tape & Reel| †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. **www.onsemi.com** **5** **NTD3055−150, NVD3055−150** ## **PACKAGE DIMENSIONS** **DPAK (SINGLE GAUGE)** CASE 369C ISSUE F - NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. **==> picture [481 x 374] intentionally omitted <==** **----- Start of picture text -----**<br> A 1. DIMENSIONING AND TOLERANCING PER ASME<br>Y14.5M, 1994.<br>E C 2. CONTROLLING DIMENSION: INCHES.<br>A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-<br>b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLDMENSIONS b3, L3 and Z.<br>FLASH, PROTRUSIONS, OR BURRS. MOLD<br>FLASH, PROTRUSIONS, OR GATE BURRS SHALL<br>4 NOT EXCEED 0.006 INCHES PER SIDE.<br>L3 Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE<br>D DETAIL A H OUTERMOST EXTREMES OF THE PLASTIC BODY.<br>6. DATUMS A AND B ARE DETERMINED AT DATUM<br>1 2 3 PLANE H.<br>7. OPTIONAL MOLD FEATURE.<br>L4 NOTE 7 DIM MININCHESMAX MILLIMETERSMIN MAX<br>b2 c BOTTOM VIEW A 0.086 0.094 2.18 2.38<br>e SIDE VIEW A1 0.000 0.005 0.00 0.13<br>b b 0.025 0.035 0.63 0.89<br>TOP VIEW 0.005 (0.13) M C b2b3 0.0280.180 0.0450.215 0.724.57 1.145.46<br>c 0.018 0.024 0.46 0.61<br>c2 0.018 0.024 0.46 0.61<br>H Z Z D 0.235 0.245 5.97 6.22<br>E 0.250 0.265 6.35 6.73<br>e 0.090 BSC 2.29 BSC<br>L2 [GAUGE] PLANE C SEATINGPLANE H 0.370 0.410 9.40 10.41<br>L 0.055 0.070 1.40 1.78<br>L1 0.114 REF 2.90 REF<br>L2 0.020 BSC 0.51 BSC<br>L L3 0.035 0.050 0.89 1.27<br>A1 BOTTOM VIEW L4 −−− 0.040 −−− 1.01<br>L1 CONSTRUCTIONSALTERNATE Z 0.155 −−− 3.93 −−−<br>DETAIL A<br>ROTATED 90 CW � SOLDERING FOOTPRINT* STYLE 2:PIN 1. GATE<br>2. DRAIN<br>3. SOURCE<br>6.20 3.00 4. DRAIN<br>0.244 0.118<br>2.58<br>0.102<br>5.80<br>1.60 6.17<br>0.228<br>0.063 0.243<br>SCALE 3:1<br>� inches [mm] �<br>**----- End of picture text -----**<br> *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. **www.onsemi.com** **6** **NTD3055−150, NVD3055−150** ## **PACKAGE DIMENSIONS** **IPAK** CASE 369D ISSUE C **==> picture [186 x 171] intentionally omitted <==** **----- Start of picture text -----**<br> B C<br>V R E<br>4<br>a<br>A<br>S<br>1 2 3<br>−T−<br>SEATING<br>PLANE K<br>J<br>F<br>H<br>D 3 PL<br>G 0.13 (0.005) M T<br>**----- End of picture text -----**<br> **==> picture [158 x 187] intentionally omitted <==** **----- Start of picture text -----**<br> NOTES:<br>1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: INCH.<br>INCHES MILLIMETERS<br>Z DIM MIN MAX MIN MAX<br>A 0.235 0.245 5.97 6.35<br>B 0.250 0.265 6.35 6.73<br>C 0.086 0.094 2.19 2.38<br>D 0.027 0.035 0.69 0.88<br>E 0.018 0.023 0.46 0.58<br>F 0.037 0.045 0.94 1.14<br>G 0.090 BSC 2.29 BSC<br>H 0.034 0.040 0.87 1.01<br>J 0.018 0.023 0.46 0.58<br>K 0.350 0.380 8.89 9.65<br>R 0.180 0.215 4.45 5.45<br>S 0.025 0.040 0.63 1.01<br>V 0.035 0.050 0.89 1.27<br>Z 0.155 −−− 3.93 −−−<br>STYLE 2:<br>PIN 1. GATE<br>2. DRAIN<br>3. SOURCE<br>4. DRAIN<br>**----- End of picture text -----**<br> ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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Updated at February 9, 2023
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