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NUP4202W1T2G
TVS Diode, NUP42, Unidirectional, 20 V, SC-88, 6 Pins
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- Manufacturer: ONSEMI
- Product type: TVS Diodes
- Product Range:NUP42 Series; SVHC:No SVHC (15-Jan-2018)
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 6Pins
- TVS Polarity: Unidirectional
- Product Range: NUP42
- Qualification: -
- Diode Mounting: Surface Mount
- Diode Case Style: SC-88
- Clamping Voltage Max: 20V
- Reverse Standoff Voltage: -
- Maximum Breakdown Voltage: -
- Minimum Breakdown Voltage: 6V
- Operating Temperature Max: 125°C
- Peak Pulse Power Dissipation: 500W
| Delivery and price | |
|---|---|
| Units per pack | 9000 |
| Price | 0.338 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
## NUP4202W1 ## Transient Voltage Suppressors ## **ESD Protection Diodes with Low Clamping Voltage** ## **http://onsemi.com** The NUP4202W1 transient voltage suppressor is designed to protect high speed data lines from ESD, EFT, and lightning. ## **Features** - Low Clamping Voltage - Stand−Off Voltage: 5 V ## **SC−88 LOW CAPACITANCE DIODE TVS ARRAY 500 WATTS PEAK POWER 6 VOLTS** - Low Leakage - Protection for the Following IEC Standards: IEC 61000−4−2 Level 4 ESD Protection ## **PIN CONFIGURATION AND SCHEMATIC** - UL Flammability Rating of 94 V−0 - This is a Pb−Free Device ## **Typical Applications** - High Speed Communication Line Protection - USB 1.1 and 2.0 Power and Data Line Protection - Digital Video Interface (DVI) and HDMI **==> picture [121 x 62] intentionally omitted <==** **----- Start of picture text -----**<br> I/O 1 6 I/O<br>VN 2 5 VP<br>I/O 3 4 I/O<br>**----- End of picture text -----**<br> - Monitors and Flat Panel Displays - MP3 **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) **Rating Symbol Value Unit** ~~ee es ee~~ Peak Power Dissipation8 x 20 S @ TA = 25 ° C (Note 1) Ppk 500 W ~~re~~ Operating Junction Temperature Range TJ −40 to +125 ° C Storage Temperature Range Tstg −55 to +150 ° C ~~-—__}_}__}~~ Lead Solder Temperature − TL 260 ° ~~—~~ C Maximum (10 Seconds) ~~ee~~ Human Body Model (HBM) ESD 16000 V Machine Model (MM) 400 IEC 61000−4−2 Air (ESD) 20000 IEC 61000−4−2 Contact (ESD) 20000 IEC 61000−4−4 (5/50 ns) EFT 40 A ~~pt~~ Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2). See Application Note AND8308/D for further description of survivability specs. **==> picture [147 x 203] intentionally omitted <==** **----- Start of picture text -----**<br> 1<br>SC−88<br>CASE 419B<br>PLASTIC<br>MARKING DIAGRAM<br>6<br>-<br>63 M<br>1<br>63 = Specific Device Code<br>M = Date Code<br>= Pb−Free Package<br>(Note: Microdot may be in either location)<br>ORDERING INFORMATION<br>**----- End of picture text -----**<br> **Device Package Shipping** NUP4202W1T2G SC−88 3000/Tape & Reel (Pb−Free) ~~er~~ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: **1** © Semiconductor Components Industries, LLC, 2009 **September, 2009 − Rev. 3** **NUP4202W1/D** **NUP4202W1** ## **ELECTRICAL CHARACTERISTICS** (TA = 25 ° C unless otherwise noted) |(TA = 25A = 25= 25°C unless otherwise noted)|C unless otherwise noted)| |---|---| |**Symbol**<br>~~—~~|**Parameter**<br>~~—~~| |IPP<br>~~—~~|Maximum Reverse Peak Pulse Current<br>~~—~~| |VC<br>~~—~~|Clamping Voltage @ IPP<br>~~—~~| |VRWM<br>~~—~~|Working Peak Reverse Voltage<br>~~—~~| |IR<br>~~—~~|Maximum Reverse Leakage Current @ VRWM<br>~~—~~| |VBR<br>~~—~~|Breakdown Voltage @ IT<br>~~—~~| |IT<br>~~—~~|Test Current<br>~~—~~| |IF<br>~~—~~|Forward Current<br>~~—~~| |VF<br>~~—~~|Forward Voltage @ IF<br>~~—~~| |Ppk<br>~~—~~|Peak Power Dissipation<br>~~—~~| |C<br>~~—~~|Capacitance @ VR= 0 and f = 1.0 MHz<br>~~—~~| **==> picture [171 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> I<br>IF<br>|<br>VC VBR VRWM<br>—S_ IR VF V<br>| IT<br>|<br>|<br>|<br>IPP<br>Uni−Directional TVS<br>**----- End of picture text -----**<br> |**Parameter**<br>~~a~~|**Symbol**<br>~~ee~~|**Conditions**<br>~~Ge~~|**Min**<br>~~Ge~~|**Typ**<br>~~Ge~~|**Max**<br>~~Ge~~|**Unit**<br>~~Ge~~| |---|---|---|---|---|---|---| |Reverse Working Voltage<br>~~a~~|VRWM<br>~~ee~~|(Note 2)<br>~~Ge~~|~~Ge~~|~~Ge~~|5.0<br>~~Ge~~|V<br>~~Ge~~| |Breakdown Voltage<br>~~a~~<br>~~a~~<br>~~ee~~|VBR<br>~~ee~~<br>~~eG~~|IT= 1 mA, (Note 3)<br>~~Ge~~<br>~~eG~~|6.0<br>~~Ge~~<br>~~eG~~|~~Ge~~<br>~~eG~~|~~Ge~~<br>~~eG~~|V<br>~~Ge~~<br>~~eG~~| |Reverse Leakage Current<br>~~ee~~<br>~~a~~|IR<br>|VRWM= 5 V<br>|||5.0<br>|A<br>| |Clamping Voltage<br>~~ee~~<br>~~a~~|VC<br>|IPP= 5 A (Note 4)<br>||8.5<br>|12.5<br>|V<br>| |Clamping Voltage<br>~~aee~~|VC<br>~~ee~~|IPP= 8 A (Note 4)<br>~~ee~~|~~ee~~|8.9<br>~~ee~~|20<br>~~ee~~|V<br>~~ee~~| |Maximum Peak Pulse Current<br>~~GC~~|IPP<br>~~GC~~|8x20 s Waveform (Note 4)<br>~~GC~~|~~GC~~|~~GC~~|28<br>~~GC~~|A<br>~~GC~~| |Junction Capacitance<br>~~ee~~<br>~~a~~|CJ<br>~~ee~~<br>|VR= 0 V, f = 1 MHz between I/O Pins and GND<br>~~ee~~<br>|~~ee~~<br>|3.0<br>~~ee~~|5.0<br>~~ee~~|pF<br>~~ee~~| |Junction Capacitance<br>~~aRe~~|CJ<br>~~Re~~|VR= 0 V, f = 1 MHz between I/O Pins<br>~~GC~~|~~GC~~|1.5|3.0|pF| |Clamping Voltage<br>~~aRe~~|VC<br>~~Re~~|@ IPP= 1 A (Notes 5 and 6)<br>~~GC~~|~~GC~~|14.5||V| |Clamping Voltage<br>~~Re~~<br>~~GC~~|VC<br>~~Re ~~<br>~~GC~~|Per IEC 61000−4−2 (Note 7)<br> ~~GC~~<br>~~GC~~|Figure 1 and 2<br>~~GC~~<br>~~GC~~|||V<br>~~GC~~| 2. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 3. VBR is measured at pulse test current IT. 4. Nonrepetitive current pulse per Figure 5 (Pin 5 to Pin 2). 5. Nonrepetitive current pulse per Figure 5 (Any I/O Pins). 6. Surge current waveform per Figure 5. 7. For test procedure see Figures 3 and 4 and Application Note AND8307/D. **Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2** **Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2** **http://onsemi.com** **2** **NUP4202W1** **IEC 61000−4−2 Spec.** |**Level**|**Test**<br>**Voltage**<br>**(kV)**|**First Peak**<br>**Current**<br>**(A)**|**Current at**<br>**30 ns (A)**|**Current at**<br>**60 ns (A)**| |---|---|---|---|---| |1|2|7.5|4|2| |2|4|15|8|4| |3|6|22.5|12|6| |4|8|30|16|8| **==> picture [231 x 156] intentionally omitted <==** **----- Start of picture text -----**<br> IEC61000−4−2 Waveform<br>Ipeak<br>100%<br>90%<br>I @ 30 ns<br>I @ 60 ns<br>10%<br>tP = 0.7 ns to 1 ns<br>**----- End of picture text -----**<br> **Figure 3. IEC61000−4−2 Spec** **==> picture [441 x 120] intentionally omitted <==** **----- Start of picture text -----**<br> ESD Gun Oscilloscope<br>TVS<br>50 �<br>Cable 50 �<br>**----- End of picture text -----**<br> **Figure 4. Diagram of ESD Test Setup** ## **The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices.** ## **ESD Voltage Clamping** For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. **==> picture [237 x 168] intentionally omitted <==** **----- Start of picture text -----**<br> 100<br>tr PEAK VALUE IRSM @ 8 �s<br>90<br>80 PULSE WIDTH (tP) IS DEFINED<br>AS THAT POINT WHERE THE<br>70 PEAK CURRENT DECAY = 8 �s<br>60<br>HALF VALUE IRSM/2 @ 20 �s<br>50<br>40<br>30<br>tP<br>20<br>10<br>0<br>0 20 40 60 80<br>t, TIME ( � s)<br>% OF PEAK PULSE CURRENT<br>**----- End of picture text -----**<br> **Figure 5. 8 X 20 � s Pulse Waveform** **http://onsemi.com** **3** **NUP4202W1** ## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) **==> picture [239 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> 100<br>90<br>80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>00 25 50 75 100 125 150 175 200<br>TA, AMBIENT TEMPERATURE (°C)<br>PEAK POWER DISSIPATION (%)<br>**----- End of picture text -----**<br> **Figure 6. Pulse Derating Curve** **==> picture [485 x 172] intentionally omitted <==** **----- Start of picture text -----**<br> 5.0 20<br>4.5 18<br>4.0 16<br>3.5 14<br>3.0 I/O−Ground 12<br>2.5 10<br>2.0 8<br>1.5 I/O lines 6<br>1.0 4<br>0.5 2<br>0.0 0<br>0 1 2 3 4 5 0 10 20 30 40 50<br>VBR, REVERSE VOLTAGE (V) PEAK PULSE CURRENT (A)<br>CLAMPING VOLTAGE (V)<br>JUNCTION CAPACITANCE (pF)<br>**----- End of picture text -----**<br> **Figure 7. Junction Capacitance vs Reverse Voltage** **Figure 8. Clamping Voltage vs. Peak Pulse Current (8 x 20 � s Waveform)** **http://onsemi.com** **4** **NUP4202W1** ## **APPLICATIONS INFORMATION** The new NUP4202W1 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the NUP4202W1 offers surge rated, low capacitance steering diodes and a TVS diode integrated in a single package (SC−88). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions to avoid damage to the power supply and any downstream components. ## **NUP4202W1 Configuration Options** The NUP4202W1 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or VCC + Vf). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 3, 4 and 6. The negative reference is connected at pin 2. This pin must be connected directly to ground by using a ground plane to minimize the PCB’s ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. ## **Option 1** Protection of four data lines and the power supply using VCC as reference. **==> picture [204 x 127] intentionally omitted <==** **----- Start of picture text -----**<br> I/O 1<br>I/O 2<br>1 6<br>2 5 VCC<br>3 4<br>I/O 3<br>I/O 4<br>**----- End of picture text -----**<br> For this configuration, connect pin 5 directly to the positive supply rail (VCC), the data lines are referenced to the supply voltage. The internal TVS diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. ## **Option 2** Protection of four data lines with bias and power supply isolation resistor. **==> picture [215 x 127] intentionally omitted <==** **----- Start of picture text -----**<br> I/O 1<br>I/O 2<br>VCC<br>1 6<br>10 k<br>2 5<br>3 4<br>I/O 3<br>I/O 4<br>**----- End of picture text -----**<br> The NUP4202W1 can be isolated from the power supply by connecting a series resistor between pin 5 and VCC. A 10 k� resistor is recommended for this application. This will maintain a bias on the internal TVS and steering diodes, reducing their capacitance. ## **Option 3** Protection of four data lines using the internal TVS diode as reference. **==> picture [205 x 127] intentionally omitted <==** **----- Start of picture text -----**<br> I/O 1<br>I/O 2<br>1 6<br>2 5 NC<br>3 4<br>I/O 3<br>I/O 4<br>**----- End of picture text -----**<br> In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal TVS can be used as the reference. For these applications, pin 5 is not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (Vc = Vf + VTVS). ## **ESD Protection of Power Supply Lines** When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: **http://onsemi.com** **5** **NUP4202W1** **==> picture [229 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> Power<br>Supply IESDpos<br>VCC<br>D1 IESDpos<br>Protected Data Line IESDneg<br>Device<br>D2<br>IESDneg VF + VCC<br>−VF<br>**----- End of picture text -----**<br> Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: For positive pulse conditions: Vc = VCC + VfD1 For negative pulse conditions: Vc = −VfD2 ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. **==> picture [227 x 163] intentionally omitted <==** **----- Start of picture text -----**<br> Power<br>Supply IESDpos<br>VCC<br>D1 IESDpos<br>Protected IESDneg<br>Device<br>Data Line<br>D2 VC = VCC + Vf + (L diESD/dt)<br>IESDneg<br>VC = −Vf − (L diESD/<br>dt)<br>**----- End of picture text -----**<br> An approximation of the clamping voltage for these fast transients would be: For positive pulse conditions: Vc = VCC + Vf + (L diESD/dt) For negative pulse conditions: Vc = −Vf – (L diESD/dt) As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic inductance will provide significant benefits in transient immunity. Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. The ON Semiconductor NUP4202W1 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes. **==> picture [152 x 130] intentionally omitted <==** **----- Start of picture text -----**<br> D1 D3 D5 D7<br>D2 D4 D6 D8<br>0<br>**----- End of picture text -----**<br> **Figure 9. NUP4202W1 Equivalent Circuit** During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below. **==> picture [171 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> Power<br>Supply<br>VCC<br>D1 IESDpos<br>Protected<br>Device<br>Data Line<br>D2<br>**----- End of picture text -----**<br> The resulting clamping voltage on the protected IC will be: Vc = VF + VTVS. The clamping voltage of the TVS diode is provided in Figure 8 and depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. **http://onsemi.com** **6** **NUP4202W1** ## **TYPICAL APPLICATIONS** UPSTREAM USB PORT **==> picture [405 x 178] intentionally omitted <==** **----- Start of picture text -----**<br> VBUS<br>VBUS<br>VBUS<br>RT VBUS<br>D+ D+<br>DOWNSTREAM<br>RT<br>D− D− USB PORT<br>VBUS USB VBUS<br>GND Controller NUP4202W1 GND<br>CT CT<br>VBUS<br>VBUS<br>NUP2202W1 RT<br>D+ DOWNSTREAM<br>RT USB PORT<br>D−<br>GND<br>CT CT<br>**----- End of picture text -----**<br> **Figure 10. ESD Protection for USB Port** **==> picture [410 x 239] intentionally omitted <==** **----- Start of picture text -----**<br> RJ45<br>Connector<br>TX+ TX+<br>TX−<br>TX−<br>Coupling<br>PHY Transformers<br>RX+<br>Ethernet RX+<br>(10/100)<br>RX−<br>RX−<br>NUP4202W1<br>VCC<br>GND<br>N/C N/C<br>**----- End of picture text -----**<br> **Figure 11. Protection for Ethernet 10/100 (Differential Mode)** **http://onsemi.com** **7** **NUP4202W1** **==> picture [254 x 202] intentionally omitted <==** **----- Start of picture text -----**<br> R1<br>RTIP<br>R3<br>R2<br>RRING<br>T1<br>VCC<br>T1/E1<br>TRANCEIVER<br>NUP4202W1<br>R4<br>TTIP<br>R5<br>TRING<br>T2<br>**----- End of picture text -----**<br> **Figure 12. TI/E1 Interface Protection** **http://onsemi.com** **8** **NUP4202W1** ## **PACKAGE DIMENSIONS** ## **SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE W **==> picture [155 x 126] intentionally omitted <==** **----- Start of picture text -----**<br> NOTES:<br>1. DIMENSIONING AND TOLERANCING PER ANSI<br>Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: INCH.<br>3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.<br>MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>A 0.80 0.95 1.10 0.031 0.037 0.043<br>A1 0.00 0.05 0.10 0.000 0.002 0.004<br>A3 0.20 REF 0.008 REF<br>b 0.10 0.21 0.30 0.004 0.008 0.012<br>C 0.10 0.14 0.25 0.004 0.005 0.010<br>D 1.80 2.00 2.20 0.070 0.078 0.086<br>E 1.15 1.25 1.35 0.045 0.049 0.053<br>e 0.65 BSC 0.026 BSC<br>- L =EE 0.10 0.20 0.30 EEE 0.004 0.008 0.012<br>HEE 2.00 2.10 2.20 0.078 0.082 0.086<br>**----- End of picture text -----**<br> **==> picture [445 x 329] intentionally omitted <==** **----- Start of picture text -----**<br> D 2. CONTROLLING DIMENSION: INCH.<br>3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.<br>e<br>MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>A 0.80 0.95 1.10 0.031 0.037 0.043<br>A1 0.00 0.05 0.10 0.000 0.002 0.004<br>6 5 4 A3 0.20 REF 0.008 REF<br>b 0.10 0.21 0.30 0.004 0.008 0.012<br>HE −E− C 0.10 0.14 0.25 0.004 0.005 0.010<br>D 1.80 2.00 2.20 0.070 0.078 0.086<br>1 2 3 E 1.15 1.25 1.35 0.045 0.049 0.053<br>e 0.65 BSC 0.026 BSC<br>ri - L =EE 0.10 0.20 0.30 EEE 0.004 0.008 0.012<br>HEE 2.00 2.10 2.20 0.078 0.082 0.086<br>b 6 PL<br>| ke<br>0.2 (0.008) M E M<br>SOLDERING FOOTPRINT*<br>_ A3 0.50<br>C 0.0197<br>f A ry] _ .<br>A1 L<br>0.65<br>A. JO fle 7<br>0.025<br>0.65<br>fo 0.025<br>0.40<br>0.0157<br>1.9<br>0.0748 SCALE 20:1 mm<br>SS inches<br>**----- End of picture text -----**<br> ## **SC−88/SC70−6/SOT−363** - *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. **ON Semiconductor** and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ## **PUBLICATION ORDERING INFORMATION** **N. American Technical Support** : 800−282−9855 Toll Free USA/Canada ## **LITERATURE FULFILLMENT** : Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA **Europe, Middle East and Africa Technical Support: Phone** : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 **Fax** : 303−675−2176 or 800−344−3867 Toll Free USA/Canada **Japan Customer Focus Center Email** : orderlit@onsemi.com Phone: 81−3−5773−3850 **ON Semiconductor Website** : **www.onsemi.com** **Order Literature** : http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative **NUP4202W1/D** **http://onsemi.com 9**
Updated at April 28, 2026
onsemi is a premier global supplier of intelligent power and sensing technologies, driving disruptive innovations across the automotive, industrial, and cloud infrastructure markets. Recognized for their commitment to sustainability and reliable supply chains, the company accelerates advancements in vehicle electrification, industrial automation, and 5G networks by solving the industry's most complex design challenges. At the core of their portfolio is an industry-leading selection of discrete semiconductors. This extensive range features thousands of high-performance bipolar transistors, single and dual MOSFETs, and a comprehensive array of diodes, including Zener, Schottky, and fast-recovery rectifiers. Engineered for superior thermal performance and energy efficiency, these foundational components are critical for demanding power conversion, switching, and signal conditioning applications. Beyond essential discretes, onsemi provides a robust suite of advanced power management and circuit protection solutions. Their lineup includes intelligent power modules, single IGBTs, and transient voltage suppression (TVS) diodes designed to safeguard sensitive circuitry. Complimented by integrated passive filters, AC/DC LED driver ICs, and specialized sub-2.4GHz RF transceivers, onsemi equips engineers with the scalable, high-quality technologies needed to build a cleaner, smarter, and more connected world.
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