NUP4004M5T1G

## NUP4004M5 

## ESD Protection Diode Array 

## **5−Pin, Bi−Directional, Quad** 

This 5−Pin bi−directional transient suppressor array is designed for applications requiring transient overvoltage protection capability. It is intended for use in transient voltage and ESD sensitive equipment such as computers, printers, cell phones, medical equipment, and other applications. Its integrated design provides bi−directional protection for four separate lines using a single TSOP−5 package. This device is ideal for situations where board space is a premium. 

## **Features** 

- Bi−directional Protection for Four Lines in a Single TSOP−5 Package 

- Low Leakage Current 

- Low Capacitance 

## **www.onsemi.com** 

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- Provides ESD Protection for JEDEC Standards JESD22 

   - Machine Model = Class C 

   - Human Body Model = Class 3B 

- Provides ESD Protection for IEC 61000−4−2, 15 kV (Air), 8 kV (Contact) 

- This is a Pb−Free Device 

## **Mechanical Characteristics** 

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- Void Free, Transfer−Molded, Thermosetting Plastic Case 

- Corrosion Resistant Finish, Easily Solderable 

- Package Designed for Optimal Automated Board Assembly 

- Small Package Size for High Density Applications 

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(Note: Microdot may be in either location) 

## **Applications** 

- LCD, Plasma TV Video Lines 

- Other Telephone Sets 

- Computers / Printers / Set−Top Boxes 

**MAXIMUM RATINGS** (TJ=25 ° C, unless otherwise specified) 

**Rating Symbol Value Unit** Operating Junction Temperature Range TJ −40 to ° C 125 Storage Temperature Range TSTG −55 to ° C 150 Lead Solder Temperature – Maximum (10 sec) TL 260 ° C Human Body Model ( HBM) ESD 16 kV Machine Model (MM) 0.4 IEC 61000−4−2 Air (ESD) 30 IEC 61000−4−2 Contact (ESD) 30 ~~+~~ Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **ORDERING INFORMATION** 

|**Device**|**Package**|**Shipping**†|
|---|---|---|
|NUP4004M5T1G|TSOP−5<br>(Pb−Free)|3000/Tape & Reel|



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

Publication Order Number: **NUP4004M5/D** 

**1** 

© Semiconductor Components Industries, LLC, 2008 

**October, 2017 − Rev. 3** 

**NUP4004M5** 

**ELECTRICAL CHARACTERISTICS** (TJ=25 ° C, unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=25°C, unl|ess otherwise specified)||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Conditions**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|Reverse Working Voltage|(Note 1)|VRWM|||5.0|V|
|Breakdown Voltage|IT= 1 mA, (Note 2)|VBR||7.0|8.0|V|
|Reverse Leakage Current|VRWM= 5 V|IR||100|1000|nA|
|Capacitance|VR= −3 V, f = 1 MHz<br>(Line to GND)|Cj||23||pF|
|Capacitance|VR= 3 V, f = 1 MHz<br>(Line to GND)|Cj||32||pF|



1. Surge protection devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 

2. VBR is measured at pulse test current IT. 

## **TYPICAL PERFORMANCE CURVES** 

(TJ = 25 ° C unless otherwise specified) 

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110 110<br>100 WAVEFORM 100<br>PARAMETERS<br>90 90<br>tr = 8  � s<br>80 td = 20  � s 80<br>70 70<br>c−t<br>60 60<br>50 td = IPP/2 50<br>40 40<br>30 30<br>20 20<br>10 10<br>0 0<br>0 5 10 15 20 25 30 0 25 50 75 100 125 150<br>t, TIME ( � s) TA, AMBIENT TEMPERATURE ( ° C)<br>PP<br>PP<br>PERCENT OF I<br>% OF RATED POWER OR I<br>**----- End of picture text -----**<br>


**Figure 1. Pulse Waveform** 

**Figure 2. Power Derating Curve** 

**www.onsemi.com** 

**2** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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## DATE  12 AUG 2020 

NOTES: 

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 

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NOTE 5 D 5X Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>0.20 C A B 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH<br>2X 0.10 T THICKNESS. MINIMUM LEAD THICKNESS IS THE<br>MINIMUM THICKNESS OF BASE MATERIAL.<br>M 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD<br>2X 0.20 T B 5 4 S FLASH, PROTRUSIONS, OR GATE BURRS. MOLDFLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT<br>1 2 3 EXCEED 0.15 PER SIDE. DIMENSION A.<br>K 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL<br>B G DETAIL Z TRIMMED LEAD IS ALLOWED IN THIS LOCATION.TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2<br>i A A FROM BODY.<br>MILLIMETERS<br>TOP VIEW DIM MIN MAX<br>A 2.85 3.15<br>B 1.35 1.65<br>DETAIL Z C 0.90 1.10<br>J D 0.25 0.50<br>C G 0.95 BSC<br>H 0.01 0.10<br>0.05 J 0.10 0.26<br>H C SEATINGPLANE END VIEW MK 0.200 0.6010<br>Se SIDE VIEW S 2.50 3.00<br>GENERIC<br>SOLDERING FOOTPRINT*<br>MARKING DIAGRAM*<br>1.9<br>0.074 5 5<br>0.95<br>0.037 XXXAYW XXX M<br>1 1<br>Analog Discrete/Logic<br>fog, bed ae<br>2.4 XXX = Specific Device Code XXX = Specific Device Code<br>0.094 A = Assembly Location M = Date Code<br>Y = Year = Pb−Free Package<br>W = Work Week<br>1.0<br>0.039 boo m = Pb−Free Package :<br>(Note: Microdot may be in either location)<br>ft 0.0280.7 SCALE 10:1 = inchesmm *This information is generic. Please refer todevice data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ ”, |<br>*For additional information on our Pb−Free strategy and soldering may or may not be present.<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ARB18753C** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: TSOP−5 PAGE 1 OF 1** ~~[a~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

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© Semiconductor Components Industries, LLC, 2018 

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