NTMD6N03R2G

## NTMD6N03R2, NVMD6N03R2 

## Power MOSFET 

## **30 V, 6 A, Dual N--Channel SOIC--8** 

## **Features** 

## **http://onsemi.com** 

- Designed for use in low voltage, high speed switching applications 

- Ultra Low On--Resistance Provides Higher Efficiency and Extends Battery Life 

|**VDSS**|**RDS(ON) Typ**|**ID Max**|
|---|---|---|
|30 V|24 mΩ@ VGS= 10 V|6.0 A|



- -- RDS(on) = 0.024 Ω, VGS = 10 V (Typ) 

- -- RDS(on) = 0.030 Ω, VGS = 4.5 V (Typ) 

 Miniature SOIC--8 Surface Mount Package Saves Board Space **N--Channel**  Diode is Characterized for Use in Bridge Circuits D D  Diode Exhibits High Speed, with Soft Recovery  AEC Q101 Qualified -- NVMD6N03R2  These Devices are Pb--Free and are RoHS Compliant G G **Applications**  DC--DC Converters ~~a4~~ S S  Computers **MARKING DIAGRAM &**  Printers **PIN ASSIGNMENT**  Cellular and Cordless Phones D1 D1 D2 D2  Disk Drives and Tape Drives 8 8 1 E6N03 **MAXIMUM RATINGS** (TJ = 25C unless otherwise noted) **SOIC--8** AYWW G **CASE 751** ~~G~~ **Rating Symbol Value Unit STYLE 11** 1 ~~=~~ Drain--to--Source Voltage VDSSDSS 30 Volts S1 G1 S2 G2 Gate--to--Source Voltage -- Continuous VGSGS 2020 Volts Drain Current---Continuous @ TA = 25CA = 25C = 25CCC IDD 6.0 Adc E6N03AA = Specific Device Code= Assembly Location= Assembly Location -- Single Pulse (tp   10 m s) IDMDM 30 Apk Y = Year Total Power Dissipation PDD Watts WW = Work Week  @ TA = 25A = 25A = 25 = 25C (Note 1)C (Note 2) C (Note 1)C (Note 2) 2.0 G = Pb--Free Package 

**Rating Symbol Value Unit STYLE 11** 1 Drain--to--Source Voltage VDSSDSS 30 Volts S1 G1 S2 G2 Gate--to--Source Voltage -- Continuous VGSGS 2020 Volts Drain Current---Continuous @ TA = 25CA = 25C = 25CCC IDD 6.0 Adc E6N03AA = Specific Device Code= Assembly Location= Assembly Location -- Single Pulse (tp   10 m s) IDMDM 30 Apk Y = Year Total Power Dissipation PDD Watts WW = Work Week  @ T@ TA = 25A = 25A = 25 = 25C (Note 1)C (Note 2) 1.292.0 G = Pb--Free Package Operating and Storage Temperature TJ, Tstg --55 to C (Note: Microdot may be in either location) Range +150 Single Pulse Drain--to--Source Avalanche EAS 325 mJ **ORDERING INFORMATION** Energy -- Starting TJ = 25C (VDD = 30 Vdc, VGS = 5.0 Vdc, **Device Package Shipping**[†] VDS = 20 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 Ω ) NTMD6N03R2G SOIC--8 2500 / Tape & Thermal Resistance R θ JA C/W (Pb--Free) Reel -- Junction--to--Ambient (Note 1) 62.5 -- Junction--to--Ambient (Note 2) 97 NVMD6N03R2G SOIC--8 2500 / Tape & Maximum Lead Temperature for Soldering TL 260 C ~~or~~ (Pb--Free) Reel Purposes for 10 seconds †For information on tape and reel specifications, ~~=~~ including part orientation and tape sizes, please Stresses exceeding Maximum Ratings may damage the device. Maximum refer to our Tape and Reel Packaging Specification Ratings are stress ratings only. Functional operation above the Recommended Brochure, BRD8011/D. Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 

1. When surface mounted to an FR4 board using 1 pad size, t  10 s 

2. When surface mounted to an FR4 board using 1 pad size, t = steady state 

Publication Order Number: 

**1** 

 Semiconductor Components Industries, LLC, 2011 **October, 2011 -- Rev. 3** 

**NTMD6N03R2/D** 

**NTMD6N03R2, NVMD6N03R2** 

## **ELECTRICAL CHARACTERISTICS** (TC = 25C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTICS** (TC= 25C unless otherwise noted)|**ELECTRICAL CHARACTERISTICS** (TC= 25C unless otherwise noted)||||||
|---|---|---|---|---|---|---|
|**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|Drain--to--Source Breakdown Voltage<br>(VGS= 0 Vdc, ID= 250mA)<br>Temperature Coefficient (Positive)||V(BR)DSS|30<br>--|--<br>30|--<br>--|Vdc<br>mV/C|
|Zero Gate Voltage Drain Current<br>(VDS= 24 Vdc, VGS= 0 Vdc, TJ= 25C)<br>(VDS= 24 Vdc, VGS= 0 Vdc, TJ= 125C)||IDSS|--<br>--|--<br>--|1.0<br>20|mAdc|
|Gate--Body Leakage Current<br>(VGS=20 Vdc, VDS= 0 Vdc)||IGSS|--|--|100|nAdc|
|**ON CHARACTERISTICS**(Note 3)|||||||
|Gate Threshold Voltage<br>(VDS= VGS, ID= 250mAdc)<br>Temperature Coefficient (Negative)||VGS(th)|1.0<br>--|1.8<br>4.6|2.5<br>--|Vdc<br>mV/C|
|Static Drain--to--Source On--State Resistance<br>(VGS= 10 Vdc, ID= 6 Adc)<br>(VGS= 4.5 Vdc, ID= 3.9 Adc)||RDS(on)|--<br>--|0.024<br>0.030|0.032<br>0.040|Ω|
|Forward Transconductance<br>(VDS= 15 Vdc, ID= 5.0 Adc)||gFS|--|10|--|Mhos|
|**DYNAMIC CHARACTERISTICS**|||||||
|Input Capacitance|(VDS= 24 Vdc, VGS= 0 Vdc,<br>f = 1.0 MHz)|Ciss|--|680|950|pF|
|Output Capacitance||Coss|--|210|300||
|Reverse Transfer Capacitance||Crss|--|70|135||
|**SWITCHING CHARACTERISTICS**(Notes 3 & 4)|||||||
|Turn--On Delay Time|(VDD= 15 Vdc, ID= 1 A,<br>VGS= 10 V,<br>RG= 6Ω)|td(on)|--|9|18|ns|
|Rise Time||tr|--|22|40||
|Turn--Off Delay Time||td(off)|--|45|80||
|Fall Time||tf|--|45|80||
|Turn--On Delay Time|(VDD= 15 Vdc, ID= 1 A,<br>VGS= 4.5 V,<br>RG= 6Ω)|td(on)|--|13|30|ns|
|Rise Time||tr|--|27|50||
|Turn--Off Delay Time||td(off)|--|22|40||
|Fall Time||tf|--|34|70||
|Gate Charge|(VDS= 15 Vdc,<br>VGS= 10 Vdc,<br>ID= 5 A)|QT|--|19|30|nC|
|||Q1|--|2.4|--||
|||Q2|--|5.0|--||
|||Q3|--|4.3|--||
|**BODY--DRAIN DIODE RATINGS**(Note 3)|||||||
|Diode Forward On--Voltage|(IS= 1.7 Adc, VGS= 0 V)<br>(IS= 1.7 Adc, VGS= 0 V, TJ= 150C)|VSD|--<br>--|0.75<br>0.62|1.0<br>--|Vdc|
|Reverse Recovery Time|(IS= 5 A, VGS= 0 V,<br>dIS/dt = 100 A/ms)|trr|--|26|--|ns|
|||ta|--|11|--||
|||tb|--|15|--||
|Reverse Recovery Stored Charge<br>(IS= 5 A, dIS/dt = 100 A/ms, VGS= 0 V)||QRR|--|0.015|--|mC|



3. Pulse Test: Pulse Width  300 m s, Duty Cycle  2%. 

4. Switching characteristics are independent of operating junction temperature. 

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**NTMD6N03R2, NVMD6N03R2** 

## **TYPICAL MOSFET ELECTRICAL CHARACTERISTICS** 

**==> picture [490 x 631] intentionally omitted <==**

**----- Start of picture text -----**<br>
12 10 V 3.4 V TJ = 25C 12<br>VDS  10 V<br>6 V 3.6 V<br>10 10<br>4 V 3.8 V<br>3.2 V<br>8 8<br>6 6<br>3 V<br>TJ = 25C<br>4 4<br>2.8 V<br>2 2 TJ = 125C<br>VGS = 2.6 V TJ = --55C<br>0 0<br>0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 1 2 3 4 5<br>VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) VGS, GATE--TO--SOURCE VOLTAGE (VOLTS)<br>Figure 1. On--Region Characteristics Figure 2. Transfer Characteristics<br>0.05 0.05<br>VGS = 10 TJ = 25C<br>0.045 0.045<br>0.04 0.04<br>0.035 T = 125  C 0.035<br>0.03 0.03 V GS = 4.5 V<br>0.025 T = 25C 0.025<br>0.02 T = --55C 0.02 V GS  = 10 V<br>0.015 0.015<br>0.01 0.01<br>1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12<br>ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On--Resistance versus Drain Current Figure 4. On--Resistance versus Drain Current<br>and Temperature and Gate Voltage<br>1.8 10,000<br>VGS = 0 V<br>ID = 3 A<br>1.6<br>VGS = 10 V<br>TJ = 150C<br>1.4 1000<br>1.2<br>TJ = 125C<br>1 100<br>0.8<br>0.6 10<br>--50 --25 0 25 50 75 100 125 150 0 5 10 15 20 25 30<br>TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS)<br>Figure 5. On--Resistance Variation with Figure 6. Drain--to--Source Leakage Current<br>Temperature versus Voltage<br>, DRAIN CURRENT (AMPS) , DRAIN CURRENT (AMPS)<br>ID ID<br>) Ω ) Ω<br>, DRAIN--TO--SOURCE RESISTANCE ( , DRAIN--TO--SOURCE RESISTANCE (<br>DS(on) DS(on)<br>R R<br>, LEAKAGE (nA)<br>(NORMALIZED)<br>IDSS<br>, DRAIN--TO--SOURCE RESISTANCE<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


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**NTMD6N03R2, NVMD6N03R2** 

## **POWER MOSFET SWITCHING** 

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are determined by how fast the FET input capacitance can be charged by current from the generator. 

The published capacitance data is difficult to use for calculating rise and fall because drain--gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that 

t = Q/I G(AV) 

During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: 

tr = Q2 x RG/(VGG -- VGSP) 

tf = Q2 x RG/VGSP 

## where 

VGG =thegatedrivevoltage, whichvariesfromzerotoVGG RG = the gate drive resistance 

and Q2 and VGSP are read from the gate charge curve. 

During the turn--on and turn--off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: 

The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off--state condition when calculating td(on) and is read at a voltage corresponding to the on--state when calculating td(off). 

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, producesavoltageatthesourcewhichreducesthegatedrive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If theparasiticswerenotpresent, theslopeof thecurveswould maintain a value of unity regardless of the switching speed. Thecircuitusedtoobtainthedataisconstructedtominimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. 

## td(on) = RG Ciss In [VGG/(VGG -- VGSP)] 

td(off) = RG Ciss In (VGG/VGSP) 

**==> picture [238 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
1600<br>Ciss T J  = 25C<br>1400<br>1200<br>1000<br>800 Crss Ciss<br>600<br>400 C oss<br>200 C rss<br>0 V DS = 0 V V GS = 0 V<br>10 5 0 5 10 15 20 25<br>VGS VDS<br>GATE--TO--SOURCE OR DRAIN--TO--SOURCE<br>VOLTAGE (VOLTS)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

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**4** 

**NTMD6N03R2, NVMD6N03R2** 

**==> picture [490 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 30 1000<br>Q T V DD = 15 V<br>8 V ID GS  = 6 A  = 10 V td(off)<br>VGS<br>20 100 tf<br>6<br>VDS tr<br>4 Q 1 Q 2<br>10 10 td(on)<br>2 TIDJ = 25= 6 AC<br>Q3<br>0 0 1<br>0 2 4 6 8 10 12 14 16 18 20 1 10 100<br>Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE ( Ω )<br>Figure 8. Gate--to--Source and Figure 9. Resistive Switching Time Variation<br>Drain--to--Source Voltage versus Total Charge versus Gate Resistance<br>t, TIME (ns)<br>, GATE--TO--SOURCE VOLTAGE (VOLTS) , DRAIN--TO--SOURCE VOLTAGE (VOLTS)<br>GS DS<br>V V<br>**----- End of picture text -----**<br>


## **DRAIN--TO--SOURCE DIODE CHARACTERISTICS** 

The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. 

System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it hasa finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in thetypicalreverserecoverywaveformofFigure14.Itisthis stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. 

The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductancesand capacitancesacted upon by 

high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probablenoisegenerated.Aratioof1isconsideredidealand values less than 0.5 are considered snappy. 

Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of thehighcelldensitydiodemeansthey canbe forcedthrough reverse recovery at a higher di/dt than a standard cell MOSFETdiodewithoutincreasingthecurrentringingorthe noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 

**==> picture [233 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>VGS = 0 V<br>5 TJ = 25C<br>4<br>3<br>2<br>1<br>0<br>0.5 0.6 0.7 0.8 0.9<br>VSD, SOURCE--TO--DRAIN VOLTAGE (VOLTS)<br>, SOURCE CURRENT (AMPS)<br>IS<br>**----- End of picture text -----**<br>


**Figure 10. Diode Forward Voltage versus Current** 

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**NTMD6N03R2, NVMD6N03R2** 

## **SAFE OPERATING AREA** 

The Forward Biased Safe Operating Area curves define the maximum simultaneous drain--to--source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25  C. Peak repetitive pulsed power limits are determined by using thethermalresponsedatainconjunctionwiththeprocedures discussed in AN569, “Transient Thermal Resistance -- General Data and Its Use.” 

Switching between the off--state and the on--state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the 

total power averaged over a complete switching cycle must not exceed (TJ(MAX) -- TC)/(RmJC). 

A power MOSFET designated E--FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditionsdifferingfromthosespecified.Althoughindustry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non--linearly with an increase of peak current in avalanche and peak junction temperature. 

**==> picture [236 x 170] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>VGS = 12 V<br>SINGLE PULSE<br>TA = 25C 1.0 ms<br>10<br>10 ms<br>1<br>dc<br>0.1<br>RDS(on) LIMIT<br>THERMAL LIMIT<br>PACKAGE LIMIT<br>0.01<br>0.1 1.0 10 100<br>VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS)<br>, DRAIN CURRENT (AMPS)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**==> picture [247 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
325<br>300<br>275 ID = 6<br>250 A<br>225<br>200<br>175<br>150<br>125<br>100<br>75<br>50<br>25<br>0<br>25 50 75 100 125 150<br>TJ, STARTING JUNCTION TEMPERATURE (C)<br>AVALANCHE ENERGY (mJ)<br>, SINGLE PULSE DRAIN--TO--SOURCE<br>AS<br>E<br>**----- End of picture text -----**<br>


**Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature** 

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**NTMD6N03R2, NVMD6N03R2** 

## **TYPICAL ELECTRICAL CHARACTERISTICS** 

**==> picture [478 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.0<br>D = 0.5<br>0.2<br>0.1<br>0.1<br>0.05<br>0.02<br>0.0106  Ω 0.0431  Ω 0.1643  Ω 0.3507  Ω 0.4302  Ω<br>0.01 CHIP<br>0.01 JUNCTION<br>0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F<br>AMBIENT<br>SINGLE PULSE<br>0.001<br>1.0E--05 1.0E--04 1.0E--03 1.0E--02 1.0E--01 1.0E+00 1.0E+01 1.0E+02 1.0E+03<br>t, TIME (s)<br>THERMAL RESISTANCE<br>Rthja(t), EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Response** 

**==> picture [203 x 98] intentionally omitted <==**

**----- Start of picture text -----**<br>
di/dt<br>IS<br>trr<br>ta tb<br>TIME<br>tp 0.25 IS<br>IS<br>**----- End of picture text -----**<br>


**Figure 14. Diode Reverse Recovery Waveform** 

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**NTMD6N03R2, NVMD6N03R2** 

## **PACKAGE DIMENSIONS** 

**==> picture [467 x 459] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOIC--8 NB<br>CASE 751--07<br>ISSUE AK<br>NOTES:<br>--X-- 1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>pe 5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>--Y-- 4 K 6. MAXIMUM MATERIAL CONDITION.751--01 THRU 751--06 ARE OBSOLETE. NEW<br>STANDARD IS 751--07.<br>G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>A 4.80 5.00 0.189 0.197<br>C N X 45 _ B 3.80 4.00 0.150 0.157<br>TD SEATING ge C 1.35 1.75 0.053 0.069<br>PLANE D 0.33 0.51 0.013 0.020<br>--Z-- G 1.27 BSC 0.050 BSC<br>H 0.10 0.25 0.004 0.010<br>0.10 (0.004) J 0.19 0.25 0.007 0.010<br>H D M J MK 0.400 _ 1.278 _ 0.0160 _ 0.0508 _<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S SOLDERING FOOTPRINT* S 5.80 6.20 0.228 0.244<br>STYLE 11:<br>PIN 1. SOURCE 1<br>2. GATE 1<br>3. SOURCE 2<br>1.52 4. GATE 2<br>0.060 5. DRAIN 2<br>6. DRAIN 2<br>7. DRAIN 1<br>8. DRAIN 1<br>p oCH<br>7.0 4.0<br>0.275 mal 0.155<br>0.6 1.270<br>0.024 Lng 0.050<br>SCALE 6:1<br> inches [mm] <br>*For additional information on our Pb--Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


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