NTMD5838NLR2G

## NTMD5838NL MOSFET – Power, Dual, N-Channel, SO-8 ~~_~~ 40 V, 8.9 A, 20 m Q 

## **Features** 

- Low RDS(on) 

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- Low Capacitance 

- Optimized Gate Charge 

**V(BR)DSS RDS(ON) MAX ID MAX** • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS 20 m @ 10 V Compliant 40 V 8.9 A 36.5 m @ 4.5 V ° ~~ce~~ **MAXIMUM RATINGS** (TJ = 25 C unless otherwise stated) ~~ee~~ **Parameter Symbol Value Unit** ~~eeee~~ **N−CHANNEL MOSFET** ~~ee~~ Drain−to−Source Voltage ~~ee~~ VDSS 40 V D D Gate−to−Source Voltage VGS ± 20 V ~~ee~~ Continuous Drain TA = 25 ° C ID 7.4 A Current R(Note 1) JA Steady TA = 70 ° C 5.9 G G Power Dissipation State TA = 25 ° C PD 2.1 W ~~BSee~~ R JA (Note 1) ~~|e~~ TA = 70 ° C ~~e~~ ~~**e** Se~~ 1.3 ~~ee 5~~ S ~~5~~ S Continuous Drain ~~|~~ TA = 25 ° C ID ~~|~~ 8.9 A Current R(Note 1) JA TA = 70 ° C 7.1 **MARKING DIAGRAM/** Power Dissipation t ≤ 10 s TA = 25 ° C PD 3.0 W **PIN ASSIGNMENT** R JA (Note 1) TA = 70 ° C 1.9 8D1 D1 D2 D2 ~~pya |eeSe~~ Pulsed DrainCurrent tp = 10 s IDM 35 A **CASE 751SO−8** D5838NAYWW **STYLE 11** ~~Se~~ Operating Junction and Storage ~~a|~~ T ~~a~~ J, TSTG ~~a~~ −55 to ° C 1 ~~,_|~~ Temperature +150 S1 G1 S2 G2 ~~ee~~ Source Current (Body Diode) IS 7.0 A (Top View) ~~eeee ee~~ Single Pulse Drain−to−Source Avalanche EAS 20 mJ A = Assembly Location Energy (L = 0.1 mH Y = Year IAS 21 A ~~aa~~ WW = Work Week Lead Temperature for Soldering Purposes TL 260 ° C = Pb−Free Package (1/8 ″ from case for 10 s) ~~ee~~ (Note: Microdot may be in either location) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the **ORDERING INFORMATION** Recommended Operating Conditions may affect device reliability. 

**ORDERING INFORMATION Device Package Shipping**[†] NTMD5838NLR2G SO−8 2500/Tape & Reel (Pb−Free) ~~7~~ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

**THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit** ~~es~~ Junction−to−Ambient Steady State R JA 58 (Notes 1 & 3) ° C/W Junction−to−Ambient − t ≤ 10 s (Note 1) R JA 40 ~~ee eeepO~~ Junction−to−Ambient Steady State (Note 2) R JA 106 

1. Surface−mounted on FR4 board using 1 sq−in pad (Cu area = 1.127 in sq [2 oz] including traces). 

2. Surface−mounted on FR4 board using 0.155 in sq (100mm[2] ) pad size. 

3. Both channels receive equivalent power dissipation 

   - 1 W applied on each channel: TJ = 2 W * 58 ° C/W + 25 ° C = 141 ° C 

Publication Order Number: **NTMD5838NL/D** 

**1** 

© Semiconductor Components Industries, LLC, 2012 **May, 2019 − Rev. 1** 

## **NTMD5838NL** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise specified) 

|**ELECTRICAL CHARACTERISTICS**(TJ=|25°C unless|otherwise specified)|otherwise specified)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID=|250�A|40|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/<br>TJ||||32||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 40 V|TJ= 25°C|||1.0|�A|
||||TJ= 125°C|||100||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS|=±20 V|||±100|nA|
|**ON CHARACTERISTICS**(Note 4)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID=|250�A|1.0|1.8|3.0|V|
|Negative Threshold Temperature Coefficient|VGS(TH)/TJ||||6.0||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V, ID= 7 A|||16.2|20|m�|
|||VGS= 4.5 V, ID= 7 A|||25.0|36.5||
|Forward Transconductance|gFS|VDS= 15 V, ID= 7 A|||4.0||S|
|**CHARGES, CAPACITANCES & GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1 MHz, VDS= 20 V|||785||pF|
|Output Capacitance|COSS||||123|||
|Reverse Transfer Capacitance|CRSS||||90|||
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 20 V; ID= 7 A|||17||nC|
|||VGS= 4.5 V, VDS= 20 V; ID= 7 A|||8.6|11||
|Threshold Gate Charge|QG(TH)||||0.8|||
|Gate−to−Source Charge|QGS||||2.8|||
|Gate−to−Drain Charge|QGD||||4.0|||
|Plateau Voltage|VGP||||3.2||V|
|Gate Resistance|RG||||1.8||�|
|**SWITCHING CHARACTERISTICS**(Note 5)||||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 20 V,<br>ID= 7 A, RG= 2.5�|||11||ns|
|Rise Time|tr||||23|||
|Turn−Off Delay Time|td(OFF)||||17|||
|Fall Time|tf||||4.0|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 7 A|TJ= 25°C||0.84|1.2|V|
||||TJ= 125°C||0.7|||
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 100 A/�s,<br>IS= 7 A|||17||ns|
|Charge Time|ta||||11|||
|Discharge Time|tb||||6.0|||
|Reverse Recovery Charge|QRR||||10||nC|



4. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

5. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NTMD5838NL** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [488 x 592] intentionally omitted <==**

**----- Start of picture text -----**<br>
50 50<br>10 V 5.5 V 4.4 V TJ = 25 ° C VDS ≥  5 V<br>40 40<br>7.5 V<br>4 V<br>30 30<br>20 3.6 V 20<br>TJ = 125 ° C<br>10 10 TJ = 25 ° C<br>3 V TJ = −55 ° C<br>0 0<br>0 1 2 3 4 5 2 3 4 5<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.06 0.035<br>TJ = 25 ° C TJ = 25 ° C<br>ID = 7 A<br>0.05<br>0.025 VGS = 4.5 V<br>0.04<br>0.03 VGS = 10 V<br>0.015<br>0.02<br>0.01 0.005<br>2 3 4 5 6 7 8 9 10 2 6 10 14 18<br>VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>1.6 100000<br>VGS = 4.5 V VGS = 0 V<br>ID = 7 A<br>1.4<br>1.2 10000 TJ = 150 ° C<br>1 1000 TJ = 125 ° C<br>0.8<br>0.6 100<br>−50 −25 0 25 50 75 100 125 150 5 15 25 35<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>DRAIN CURRENT (A) DRAIN CURRENT (A)<br>ID,  ID,<br>)<br>� )<br>DRAIN−TO−SOURCE RESISTANCE ( �<br>DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),<br>R DS(on),<br>R<br>DRAIN−TO−SOURCE , LEAKAGE (nA)<br>IDSS<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**==> picture [187 x 20] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 6. Drain−to−Source Leakage Current<br>vs. Voltage<br>**----- End of picture text -----**<br>


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**3** 

**NTMD5838NL** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [492 x 619] intentionally omitted <==**

**----- Start of picture text -----**<br>
1200 6<br>TJ = 25 ° C<br>1000 VGS = 0 V Q T<br>800 Ciss 4<br>QGS QGD<br>600<br>400 2<br>200 Coss VIDGS = 7 A = 10 V<br>Crss TJ = 25 ° C<br>0 0<br>0 10 20 30 40 0 1 2 3 4 5 6 7 8 9 10<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)<br>Figure 7. Capacitance Variation Figure 8. Gate−To−Source and<br>Drain−To−Source Voltage vs. Total Charge<br>1000<br>VDS = 20 V 12 V GS  = 0 V<br>ID = 7 A TJ = 25 ° C<br>VGS = 4.5 V 10<br>100<br>8<br>tr td(on) 6<br>td(off)<br>10<br>tf 4<br>2<br>1 0<br>1 10 100 0.2 0.4 0.6 0.8 1<br>RG, GATE RESISTANCE ( � ) VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage vs. Current<br>Variation vs. Gate Resistance<br>100 20<br>ID = 20 A<br>10<br>15<br>1  � s<br>1<br>10  � s<br>10<br>100  � s<br>0.1 VGS = 10 V<br>SINGLE PULSE 10 ms<br>TC = 25 ° C dc 5<br>0.01<br>RDS(on) LIMIT<br>THERMAL LIMIT<br>PACKAGE LIMIT<br>0.001 0<br>0.1 1 10 100 25 50 75 100 125 150<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs.<br>Safe Operating Area Starting Junction Temperature<br>C, CAPACITANCE (pF) , GATE−TO−SOURCE (V) , DRAIN−TO−SOURCE (V)<br>GS DS<br>V V<br>t, TIME (ns)<br>, SOURCE CURRENT (A)<br>IS<br>, DRAIN CURRENT (A)<br>ID<br>EAS, SINGLE PULSE DRAIN−TO−<br>SOURCE AVALANCHE ENERGY (mJ)<br>**----- End of picture text -----**<br>


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**4** 

**NTMD5838NL** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [485 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>D = 0.5<br>0.2<br>10<br>0.1<br>0.05<br>0.02<br>1<br>0.01<br>0.1<br>SINGLE PULSE<br>0.01<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>t, TIME (s)<br>C/W)<br>°<br>R(t) (<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Response** 

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**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [42 x 32] intentionally omitted <==**

**----- Start of picture text -----**<br>
8<br>1<br>SCALE 1:1<br>**----- End of picture text -----**<br>


**SOIC−8 NB** CASE 751−07 ISSUE AK DATE 16 FEB 2011 

**==> picture [468 x 427] intentionally omitted <==**

**----- Start of picture text -----**<br>
NOTES:<br>−X− 1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>py 5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>4 MAXIMUM MATERIAL CONDITION.<br>−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW<br>Th STANDARD IS 751−07.<br>G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>A 4.80 5.00 0.189 0.197<br>C N X 45 B 3.80 4.00 0.150 0.157<br>| a SEATING  “ C 1.35 1.75 0.053 0.069<br>PLANE D 0.33 0.51 0.013 0.020<br>−Z− G 1.27 BSC 0.050 BSC<br>H 0.10 0.25 0.004 0.010<br>0.10 (0.004) J 0.19 0.25 0.007 0.010<br>H D M J K 0.40 1.27 0.016 0.050<br>M 0  8  0  8<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244<br>GENERIC<br>MARKING DIAGRAM*<br>SOLDERING FOOTPRINT*<br>8 8 8 8<br>XXXXX XXXXX XXXXXX XXXXXX<br>1.52 ALYWX ALYWX AYWW AYWW<br>0.060<br>1 1 1 1<br>IC IC Discrete Discrete<br>r oogO: bd (Pb−Free) bed be (Pb−Free)<br>7.0 4.0<br>XXXXX = Specific Device Code XXXXXX = Specific Device Code<br>0.275 0.155<br>A = Assembly Location A = Assembly Location<br>L = Wafer Lot Y = Year<br>yt Y = Year WW = Work Week<br>W = Work Week = Pb−Free Package<br>= Pb−Free Package<br>0.6 1.270 *This information is generic. Please refer to<br>0.024 oon 0.050 device data sheet for actual part marking. |<br>Pb−Free indicator, “G” or microdot “ ”, may<br>mm or may not be present. Some products may<br>SCALE 6:1<br>inches not follow the Generic Marking.<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

**STYLES ON PAGE 2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 1 OF 2** ~~a~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**SOIC−8 NB** CASE 751−07 ISSUE AK 

## DATE 16 FEB 2011 

|STYLE 1:|STYLE 1:|STYLE 2:||STYLE 3:|STYLE 3:||STYLE 4:|STYLE 4:|
|---|---|---|---|---|---|---|---|---|
|PIN 1.|EMITTER|PIN 1.|COLLECTOR, DIE, #1|PIN 1.||DRAIN, DIE #1|PIN 1.|ANODE|
|2.|COLLECTOR|2.|COLLECTOR, #1|2.||DRAIN, #1|2.|ANODE|
|3.|COLLECTOR|3.|COLLECTOR, #2|3.||DRAIN, #2|3.|ANODE|
|4.|EMITTER|4.|COLLECTOR, #2|4.||DRAIN, #2|4.|ANODE|
|5.|EMITTER|5.|BASE, #2|5.||GATE, #2|5.|ANODE|
|6.|BASE|6.|EMITTER, #2|6.||SOURCE, #2|6.|ANODE|
|7.|BASE|7.|BASE, #1|7.||GATE, #1|7.|ANODE|
|8.|EMITTER|8.|EMITTER, #1|8.||SOURCE, #1|8.|COMMON CATHODE|
|STYLE 5:||STYLE 6:||STYLE 7:|||STYLE 8:||
|PIN 1.|DRAIN|PIN 1.|SOURCE|PIN 1.||INPUT|PIN 1.|COLLECTOR, DIE #1|
|2.|DRAIN|2.|DRAIN|2.||EXTERNAL  BYPASS|2.|BASE, #1|
|3.|DRAIN|3.|DRAIN|3.||THIRD STAGE SOURCE|3.|BASE, #2|
|4.|DRAIN|4.|SOURCE|4.||GROUND|4.|COLLECTOR, #2|
|5.|GATE|5.|SOURCE|5.||DRAIN|5.|COLLECTOR, #2|
|6.|GATE|6.|GATE|6.||GATE 3|6.|EMITTER, #2|
|7.|SOURCE|7.|GATE|7.||SECOND STAGE Vd|7.|EMITTER, #1|
|8.|SOURCE|8.|SOURCE|8.||FIRST STAGE Vd|8.|COLLECTOR, #1|
|STYLE 9:||STYLE 10:||STYLE 11:|||STYLE 12:||
|PIN 1.|EMITTER,  COMMON|PIN 1.|GROUND|PIN 1.||SOURCE 1|PIN 1.|SOURCE|
|2.|COLLECTOR, DIE #1|2.|BIAS 1|2.||GATE 1|2.|SOURCE|
|3.|COLLECTOR, DIE #2|3.|OUTPUT|3.||SOURCE 2|3.|SOURCE|
|4.|EMITTER, COMMON|4.|GROUND|4.||GATE 2|4.|GATE|
|5.|EMITTER, COMMON|5.|GROUND|5.||DRAIN 2|5.|DRAIN|
|6.|BASE, DIE #2|6.|BIAS 2|6.||DRAIN 2|6.|DRAIN|
|7.|BASE, DIE #1|7.|INPUT|7.||DRAIN 1|7.|DRAIN|
|8.|EMITTER, COMMON|8.|GROUND|8.||DRAIN 1|8.|DRAIN|
|STYLE 13:||STYLE 14:||STYLE 15:|||STYLE 16:||
|PIN 1.|N.C.|PIN 1.|N−SOURCE|PIN 1.|ANODE 1||PIN 1.|EMITTER, DIE #1|
|2.|SOURCE|2.|N−GATE|2.|ANODE 1||2.|BASE, DIE #1|
|3.|SOURCE|3.|P−SOURCE|3.|ANODE 1||3.|EMITTER, DIE #2|
|4.|GATE|4.|P−GATE|4.|ANODE 1||4.|BASE, DIE #2|
|5.|DRAIN|5.|P−DRAIN|5.|CATHODE, COMMON||5.|COLLECTOR, DIE #2|
|6.|DRAIN|6.|P−DRAIN|6.|CATHODE, COMMON||6.|COLLECTOR, DIE #2|
|7.|DRAIN|7.|N−DRAIN|7.|CATHODE, COMMON||7.|COLLECTOR, DIE #1|
|8.|DRAIN|8.|N−DRAIN|8.|CATHODE, COMMON||8.|COLLECTOR, DIE #1|
|STYLE 17:||STYLE 18:||STYLE 19:|||STYLE 20:||
|PIN 1.|VCC|PIN 1.|ANODE|PIN 1.||SOURCE 1|PIN 1.|SOURCE (N)|
|2.|V2OUT|2.|ANODE|2.||GATE 1|2.|GATE (N)|
|3.|V1OUT|3.|SOURCE|3.||SOURCE 2|3.|SOURCE (P)|
|4.|TXE|4.|GATE|4.||GATE 2|4.|GATE (P)|
|5.|RXE|5.|DRAIN|5.||DRAIN 2|5.|DRAIN|
|6.|VEE|6.|DRAIN|6.||MIRROR 2|6.|DRAIN|
|7.|GND|7.|CATHODE|7.||DRAIN 1|7.|DRAIN|
|8.|ACC|8.|CATHODE|8.||MIRROR 1|8.|DRAIN|
|STYLE 21:||STYLE 22:||STYLE 23:|||STYLE 24:||
|PIN 1.|CATHODE 1|PIN 1.|I/O LINE 1|PIN 1.||LINE 1 IN|PIN 1.|BASE|
|2.|CATHODE 2|2.|COMMON CATHODE/VCC|2.||COMMON ANODE/GND|2.|EMITTER|
|3.|CATHODE 3|3.|COMMON CATHODE/VCC|3.||COMMON ANODE/GND|3.|COLLECTOR/ANODE|
|4.|CATHODE 4|4.|I/O LINE 3|4.||LINE 2 IN|4.|COLLECTOR/ANODE|
|5.|CATHODE 5|5.|COMMON ANODE/GND|5.||LINE 2 OUT|5.|CATHODE|
|6.|COMMON ANODE|6.|I/O LINE 4|6.||COMMON ANODE/GND|6.|CATHODE|
|7.|COMMON ANODE|7.|I/O LINE 5|7.||COMMON ANODE/GND|7.|COLLECTOR/ANODE|
|8.|CATHODE 6|8.|COMMON ANODE/GND|8.||LINE 1 OUT|8.|COLLECTOR/ANODE|
|STYLE 25:||STYLE 26:||STYLE 27:|STYLE 27:||STYLE 28:||
|PIN 1.|VIN|PIN 1.|GND|PIN 1.||ILIMIT|PIN 1.|SW_TO_GND|
|2.|N/C|2.|dv/dt|2.||OVLO|2.|DASIC_OFF|
|3.|REXT|3.|ENABLE|3.||UVLO|3.|DASIC_SW_DET|
|4.|GND|4.|ILIMIT|4.||INPUT+|4.|GND|
|5.|IOUT|5.|SOURCE|5.||SOURCE|5.|V_MON|
|6.|IOUT|6.|SOURCE|6.||SOURCE|6.|VBULK|
|7.|IOUT|7.|SOURCE|7.||SOURCE|7.|VBULK|
|8.|IOUT|8.|VCC|8.||DRAIN|8.|VIN|
|STYLE 29:||STYLE 30:|||||||
|PIN 1.|BASE, DIE #1|PIN 1.|DRAIN 1||||||
|2.|EMITTER, #1|2.|DRAIN 1||||||
|3.|BASE, #2|3.|GATE 2||||||
|4.|EMITTER, #2|4.|SOURCE 2||||||
|5.|COLLECTOR, #2|5.|SOURCE 1/DRAIN 2||||||
|6.|COLLECTOR, #2|6.|SOURCE 1/DRAIN 2||||||
|7.|COLLECTOR, #1|7.|SOURCE 1/DRAIN 2||||||
|8.|COLLECTOR, #1|8.|GATE 1||||||



Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 2 OF 2** 

ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

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