NTLJD3115PT1G

NTMD4820N 

## Power MOSFET 

## **30 V, 8 A, Dual N−Channel, SOIC−8** 

## **Features** 

- Low R to Minimize Conduction Losses DS(on) 

- Low Capacitance to Minimize Driver Losses 

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- Optimized Gate Charge to Minimize Switching Losses 

- Dual SOIC−8 Surface Mount Package Saves Board Space 

> **V(BR)DSS** ~~ee~~ **RDS(on) Max ID Max Applications** 20 m @ 10 V 30 V 8 A • Disk Drives 27 m @ 4.5 V ~~| pe|S~~ • DC−DC Converters • Printers **N−Channel MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise stated) D **Rating Symbol Value Unit** ~~PO _~~ Drain−to−Source Voltage VDSS 30 V ~~ee —-~~ Gate−to−Source Voltage VGS ± 20 V ~~p~~ Continuous Drain ~~O~~ TA = 25 ° C ID ~~=~~ 6.4 A G ~~=[—]~~ Current R JA (Note 1) TA = 70 ° C 5.1 ~~|~~ Power Dissipation TA = 25 ° C PD 1.28 W R JA (Note 1) S ~~CC~~ Continuous Drain TA = 25 ° C ID 4.9 A ~~I~~ Current R JA (Note 2) Steady ~~——-~~ TA = 70 ° C 3.9 **MARKING  DIAGRAM& PIN ASSIGNMENT** Power Dissipation State TA = 25 ° C PD 0.75 W R JA (Note 2) D1 D1 D2 D2 ~~P| J~~ Continuous Drain TA = 25 ° C ID 8.0 A 8 Current R(Note 1) JA t < 10 s TA = 70 ° C 6.4 8 **CASE 751SOIC−8** AYWW4820N ~~po J[—] -—~~ Power Dissipation TA = 25 ° C PD 2.0 W 1 **STYLE 11** 1 R JA t < 10 s (Note 1) Pulsed Drain Current ~~ee~~ TA = 25 ~~=e[=]~~ ° C, IDM 32 A S1 G1 S2 G2 tp = 10 s 4820N = Device Code ~~Co~~ Operating Junction and Storage Temperature ~~PF~~ TJ, TSTG ~~—~~ −55 to ° C A = Assembly Location Y = Year +150 WW = Work Week ~~tt fd pt~~ Source Current (Body Diode) IS 2.0 A = Pb−Free Package Single Pulse Drain−to−Source Avalanche EAS 60.5 mJ Energy TJ = 25C, VDD = 30 V, VGS = 10 V, ~~a~~ IL = 11 Apk, L = 1.0 mH, RG = 25 **ORDERING INFORMATION** Lead Temperature for Soldering Purposes TL 260 ° C (1/8 ″ from case for 10 s) **Device Package Shipping**[†] **THERMAL RESISTANCE RATINGS** NTMD4820NR2G SOIC−8 2500/Tape & Reel **Rating Symbol Max Unit** (Pb−Free) ~~te a ee =~~ Junction−to−Ambient – Steady State (Note 1) R JA 97.5 †For information on tape and reel specifications, Junction−to−Ambient – t ≤ 10 s (Note 1) R JA 62 including part orientation and tape sizes, please ~~ee~~ ° C/W refer to our Tape and Reel Packaging Specification Junction−to−FOOT (Drain) R JF 40 Brochure, BRD8011/D. 

> ~~PO~~ ~~**—**~~ Junction−to−Ambient – Steady State (Note 2) ~~———~~ R JA ~~=i~~ 167.5 1. Surface−mounted on FR4 board using 1 inch sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2009 **August, 2009 − Rev. 2** 

**NTMD4820N/D** 

**NTMD4820N** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted)jk 

|**Characteristic**|**Symbol**|**Test Condition**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= 250�A||30|||V|
|Drain−to−Source Breakdown Voltage Tem-<br>perature Coefficient|V(BR)DSS/TJ||||26||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 24 V|TJ= 25°C|||1.0|�A|
||||TJ= 100°C|||10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=±20 V||||±100|nA|
|**ON CHARACTERISTICS**(Note 3)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.5||3.0|V|
|Negative Threshold Temperature Coeffi-<br>cient|VGS(TH)/TJ||||5.0||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V|ID= 7.5 A||15|20|m�|
|||VGS= 4.5 V|ID= 6.5 A||20|27||
|Forward Transconductance|gFS|VDS= 1.5 V, ID= 7.5 A|||21||S|
|**CHARGES, CAPACITANCES AND GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1.0 MHz, VDS= 15 V|||940||pF|
|Output Capacitance|COSS||||225|||
|Reverse Transfer Capacitance|CRSS||||125|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 15 V, ID= 7.5 A|||7.7||nC|
|Threshold Gate Charge|QG(TH)||||1.1|||
|Gate−to−Source Charge|QGS||||3.3|||
|Gate−to−Drain Charge|QGD||||3.2|||
|Total Gate Charge|QG(TOT)|VGS= 10 V, VDS= 15 V, ID= 7.5 A|||15.2||nC|
|**SWITCHING CHARACTERISTICS**(Note 4)||||||||
|Turn−On Delay Time|td(ON)|VGS= 10 V, VDD= 15 V,<br>ID= 1.0 A, RG= 6.0�|||9.4||ns|
|Rise Time|tr||||4.0|||
|Turn−Off Delay Time|td(OFF)||||21|||
|Fall Time|tf||||6.5|||
|**DRAIN−TO−SOURCE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V<br>ID= 2.0 A|TJ= 25°C||0.75|1.0|V|
||||TJ= 125°C||0.59||ns|
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt= 100 A/�s,<br>IS= 2.0 A|||17.8|||
|Charge Time|Ta||||8.3|||
|Discharge Time|Tb||||9.5|||
|Reverse Recovery Time|QRR||||8.0||nC|
|**PACKAGE PARASITIC VALUES**||||||||
|Source Inductance|LS|TA= 25°C|||0.66||nH|
|Drain Inductance|LD||||0.20||nH|
|Gate Inductance|LG||||1.50||nH|
|Gate Resistance|RG||||1.5|3.0|�|



3. Pulse Test: pulse width � 300 � s, duty cycle � 2%. 

4. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NTMD4820N** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [491 x 605] intentionally omitted <==**

**----- Start of picture text -----**<br>
15 15<br>6 V 10V TJ = 25 ° C 3.6 V VDS ≥  10 V<br>12.5 5 V<br>4.5 V<br>10 4.2 V 10<br>4 V 3.4 V<br>7.5 3.8 V<br>5 3.2 V 5 TJ = 125 ° C<br>2.5 2.8 V 3.0 V TJ = 25 ° C<br>TJ = −55 ° C<br>0 0<br>0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1 1.5 2 2.5 3 3.5 4 4.5<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.095 0.030<br>0.085 TJ = 25 ° C TJ = 25 ° C<br>ID = 7.5 A 0.025<br>0.075<br>VGS = 4.5 V<br>0.065 0.020<br>0.055<br>0.015<br>0.045<br>0.035 0.010 VGS = 10 V<br>0.025<br>0.005<br>0.015<br>0.005 0<br>3 4 5 6 7 8 9 10 2 4 6 8 10 12 14<br>VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>1.6 100000<br>1.5 ID = 7.5 A VGS = 0 V<br>VGS = 10 V<br>1.4<br>1.3<br>10000<br>1.2 TJ = 150 ° C<br>1.1<br>1.0<br>1000<br>0.9<br>0.8 TJ = 100 ° C<br>0.7<br>0.6 100<br>−50 −25 0 25 50 75 100 125 150 3 6 9 12 15 18 21 24 27 30<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>DRAIN CURRENT (AMPS) DRAIN CURRENT (AMPS)<br>ID,  ID,<br>) � ) �<br>DRAIN−TO−SOURCE RESISTANCE ( DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),  DS(on),<br>R R<br>, LEAKAGE (nA)<br>DRAIN−TO−SOURCE<br>IDSS<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**Figure 6. Drain−to−Source Leakage Current vs. Voltage** 

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**3** 

**NTMD4820N** 

## **TYPICAL PERFORMANCE CURVES** 

**==> picture [490 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
1300 10 20<br>1200 TJ = 25 ° C 9 QT<br>10001100 Ciss VGS = 0 V 8 VDS 16<br>900 7 VGS<br>800 6 12<br>700<br>5<br>600 QGS QGD<br>4 8<br>500<br>400 Coss 3<br>300 2 4<br>200100 Crss 1 TIDJ = 7.5 A = 25 ° C<br>0 0 0<br>0 5 10 15 20 25 30 0 2 4 6 8 10 12 14 16<br>DRAIN−TO−SOURCE VOLTAGE (VOLTS) QG, TOTAL GATE CHARGE (nC)<br>C, CAPACITANCE (pF)<br>VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)<br>**----- End of picture text -----**<br>


**Figure 7. Capacitance Variation** 

**Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge** 

**==> picture [490 x 395] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000 3<br>VDD = 10 V VGS = 0 V<br>ID = 1 A TJ = 25 ° C<br>VGS = 15 V<br>100 td(off) 2<br>tf<br>tr<br>td(on)<br>10 1<br>1 0<br>1 10 100 0.3 0.4 0.5 0.6 0.7 0.8<br>RG, GATE RESISTANCE (OHMS) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage vs. Current<br>Variation vs. Gate Resistance<br>100 75<br>ID = 11 A<br>10 �s<br>10 100 �s<br>50<br>1 ms<br>1 10 ms<br>VGS = 20 V<br>SINGLE PULSE 25<br>0.1 TC = 25 ° C<br>dc<br>RDS(on) LIMIT<br>THERMAL LIMIT<br>PACKAGE LIMIT<br>0.01 0<br>0.1 1 10 100 25 50 75 100 125 150<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE ( ° C)<br>t, TIME (ns)<br>, SOURCE CURRENT (AMPS)<br>IS<br>ID, DRAIN CURRENT (AMPS) AVALANCHE ENERGY (mJ)<br>EAS, SINGLE PULSE DRAIN−TO−SOURCE<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature** 

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**4** 

**NTMD4820N** 

## **PACKAGE DIMENSIONS** 

**==> picture [468 x 446] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOIC−8 NB<br>CASE 751−07<br>−X− ISSUE AJ NOTES:1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>oe 5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>4 MAXIMUM MATERIAL CONDITION.<br>−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW<br>STANDARD IS 751−07.<br>~ G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>C N X 45 A 4.80 5.00 0.189 0.197<br>B 3.80 4.00 0.150 0.157<br>SEATINGPLANE , /! C 1.35 1.75 0.053 0.069<br>−Z− D 0.33 0.51 0.013 0.020<br>G 1.27 BSC 0.050 BSC<br>0.10 (0.004) H 0.10 0.25 0.004 0.010<br>H D M J KJ 0.400.19 1.270.25 0.0160.007 0.0500.010<br>M 0  8  0  8<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S SOLDERING FOOTPRINT* S 5.80 6.20 0.228 0.244<br>STYLE 11:<br>PIN 1. SOURCE 1<br>2. GATE 1<br>3. SOURCE 2<br>1.52 4. GATE 2<br>0.060 5. DRAIN 2<br>6. DRAIN 2<br>7. DRAIN 1<br>8. DRAIN 1<br>ati<br>7.0 4.0<br>0.275 mal 0.155<br>0.6 1.270<br>0.024 sano 0.050<br>SCALE 6:1 mm<br>inches<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


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**NTMD4820N/D** 

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