NTJD5121NT2G.

## NTJD5121N, NVJD5121N 

## MOSFET – Power, Dual, N-Channel With ESD Protection, SC-88 60 V, 295 mA 

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## **Features** 

- Low RDS(on) 

- Low Gate Threshold 

- Low Input Capacitance 

- ESD Protected Gate 

- NV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable 

• This is a Pb−Free Device **Applications** • Low Side Load Switch • DC−DC Converters (Buck and Boost Circuits) **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise stated) **Parameter Symbol Value Unit** ~~es es es~~ Drain−to−Source Voltage VDSS 60 V ~~eses es~~ Gate−to−Source Voltage VGS ± 20 V ~~eses es~~ Continuous Drain Steady TA = 25 ° C ID 295 mA Current (Note 1) State TA = 85 ° C 212 ~~eo~~ t ≤ 5 s ~~|~~ TA = 25 ° C ~~|~~ 304 TA = 85 ° C 219 ~~=~~ Power Dissipation Steady TA = 25 ° C PD 250 mW (Note 1) State ~~oP~~ t ≤ 5 s 266 ~~es ee~~ Pulsed Drain Current t ~~es~~ p = 10 s ~~es~~ IDM 900 mA Operating Junction and Storage Temperature TJ, TSTG −55 to ° C 150 Source Current (Body Diode) IS 210 mA Lead Temperature for Soldering Purposes TL 260 ° C (1/8” from case for 10 s) ~~i es~~ Gate−Source ESD Rating (HBM) ESD ~~es~~ HBM 2000 ~~es~~ V ~~es~~ Gate−Source ESD Rating (MM) ~~es~~ ESDMM ~~es~~ 200 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

**==> picture [174 x 194] intentionally omitted <==**

**----- Start of picture text -----**<br>
V(BR)DSS RDS(on) MAX ID Max<br>ee es<br>1.6  @ 10 V<br>60 V 295 mA<br>2.5  @ 4.5 V<br>|i;<br>SC−88 (SOT−363)<br>S1 1 6 D1<br>G1 2 5 G2<br>D2 3 4 S2<br>+E<br>**----- End of picture text -----**<br>


**==> picture [165 x 170] intentionally omitted <==**

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Top View<br>MARKING DIAGRAM &<br>PIN ASSIGNMENT<br>D1 G2 S2<br>e<br>6<br>1<br>fo ne XX M<br>SC−88/SOT−363<br>CASE 419B<br>STYLE 26<br>1<br>S1 yuu G1 D2<br>XX = Device Code<br>M = Date Code<br>= Pb−Free Package<br>(Note: Microdot may be in either location)<br>**----- End of picture text -----**<br>


## **ORDERING INFORMATION** 

See detailed ordering and shipping information ion page 6 of this data sheet. 

## **THERMAL RESISTANCE RATINGS** 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2015 **May, 2019 − Rev. 9** 

**NTJD5121N/D** 

**NTJD5121N, NVJD5121N** 

|**Parameter**|**Symbol**|**Value**|**Unit**|
|---|---|---|---|
|Junction−to−Ambient – Steady State|R�JA|467|°C/W|
|Junction−to−Ambient – t≤5 s|R�JA|412||
|Junction−to−Lead – Steady State|R�JL|252||



1. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 

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**2** 

## **NTJD5121N, NVJD5121N** 

**ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise stated) 

|**ELECTRICAL CHARACTERISTIC**|**S**(TJ= 25°C u|nless otherwise stated)|nless otherwise stated)|||||
|---|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V, ID= 250�A||60|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(BR)DSS/TJ|ID= 250�A, ref to 25°C|||92||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V,<br>VDS= 60 V|TJ= 25°C|||1.0|�A|
||||TJ= 125°C|||500||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=±20 V||||±10|�A|
|**ON CHARACTERISTICS**(Note 2)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A||1.0|1.7|2.5|V|
|Negative Threshold Temperature<br>Coefficient|VGS(TH)/TJ||||4.0||mV/°C|
|Drain−to−Source On Resistance|RDS(on)|VGS= 10 V, ID= 500 mA|||1.0|1.6|�|
|||VGS= 4.5 V, ID= 200 mA|||1.2|2.5||
|Forward Transconductance|gFS|VDS= 5 V, ID= 200 mA|||80||S|
|Gate Resistance|RG||||536||�|
|**CHARGES AND CAPACITANCES**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1.0 MHz,<br>VDS= 20 V|||26||pF|
|Output Capacitance|COSS||||4.4|||
|Reverse Transfer Capacitance|CRSS||||2.5|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 25 V,<br>ID= 200 mA|||0.9||nC|
|Threshold Gate Charge|QG(TH)||||0.2|||
|Gate−to−Source Charge|QGS||||0.3|||
|Gate−to−Drain Charge|QGD||||0.28|||
|**SWITCHING CHARACTERISTICS**(Note 3)||||||||
|Turn−On Delay Time|td(on)|VGS= 4.5 V, VDD= 25 V,<br>ID= 200 mA, RG= 25�|||22||ns|
|Rise Time|tr||||34|||
|Turn−Off Delay Time|td(off)||||34|||
|Fall Time|tf||||32|||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V,<br>IS= 200 mA|TJ= 25°C||0.8|1.2|V|
||||TJ= 85°C||0.7|||



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse Test: pulse width ≤ 300 � s, duty cycle ≤ 2%. 

3. Switching characteristics are independent of operating junction temperatures. 

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**3** 

**NTJD5121N, NVJD5121N** 

## **TYPICAL PERFORMANCE CURVES** 

(TJ = 25 ° C unless otherwise noted) 

**==> picture [492 x 622] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.6 5 V VGS = 10 TJ = 25 ° C 1.2 VDS ≥  10 V<br>4.5 V 1<br>1.2 4 V<br>4.2 V<br>3.8 V 0.8<br>2.4 V 3.6 V<br>0.8 0.6<br>3.4 V<br>2.2 V<br>3.2 V<br>0.4<br>0.4 3 V 25 ° C<br>2.8 V<br>2.6 V 0.2 TJ = 125 ° C −55 ° C<br>0 0<br>0 1 2 3 4 5 0 1 2 3 4 5<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>2.4 2.4<br>VGS = 4.5 V<br>2 TJ = 125 ° C 2 VGS = 10 V<br>1.6 TJ = 85 ° C 1.6 TJ = 125 ° C<br>TJ = 25 ° C TJ = 85 ° C<br>1.2 1.2<br>TJ = 25 ° C<br>0.8 TJ = −55 ° C 0.8 TJ = −55 ° C<br>0.4 0.4<br>0 0<br>0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1<br>ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)<br>Figure 3. On−Resistance vs. Drain Current and Figure 4. On−Resistance vs. Drain Current and<br>Temperature Temperature<br>2.4 1.8<br>ID = 0.2 A<br>ID = 500 mA 1.6 VGS = 4.5 V and 10 V<br>2<br>1.4<br>1.6 1.2<br>1<br>4.5 V<br>1.2 10 V<br>ID = 200 mA 0.8<br>0.8 0.6<br>2 4 6 8 10 −50 −25 0 25 50 75 100 125 150<br>VGS, GATE−TO−SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 5. On−Resistance versus Figure 6. On−Resistance Variation with<br>Gate−to−Source Voltage Temperature<br>DRAIN CURRENT (A) DRAIN CURRENT (A)<br>ID,  ID,<br>)<br>� )<br>DRAIN−TO−SOURCE RESISTANCE ( �<br>DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),<br>R DS(on),<br>R<br>) �<br>DRAIN−TO−SOURCE<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),<br>R<br>**----- End of picture text -----**<br>


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**4** 

**NTJD5121N, NVJD5121N** 

## **TYPICAL PERFORMANCE CURVES** 

(TJ = 25 ° C unless otherwise noted) 

**==> picture [491 x 620] intentionally omitted <==**

**----- Start of picture text -----**<br>
40 5<br>TJ = 25 ° C ID = 0.2 A<br>V GS  = 0 V TJ = 25 ° C<br>4<br>30 Ciss VDD = 25 V<br>3<br>20<br>2<br>10 Coss<br>1<br>Crss<br>0 0<br>0 4 8 12 16 20 0 0.2 0.4 0.6 0.8 1<br>DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)<br>Figure 7. Capacitance Variation Figure 8. Gate−to−Source and<br>Drain−to−Source Voltage vs. Total Charge<br>1 2.5<br>VGS = 0 V 2.4 ID = 250  � A<br>2.3<br>2.2<br>2.1<br>2.0<br>1.9<br>1.8<br>0.1<br>1.7<br>TJ = 85 ° C 1.6<br>TJ = 25 ° C 1.51.4<br>1.3<br>1.2<br>1.1<br>0.01 1.0<br>0.4 0.6 0.8 1 1.2 −50 −25 0 25 50 75 100 125 150<br>VSD, SOURCE−TO−DRAIN VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 9. Diode Forward Voltage vs. Current Figure 10. Threshold Voltage with Temperature<br>1000<br>D = 0.5<br>0.2<br>100<br>0.1<br>0.05<br>0.02<br>10<br>0.01<br>SINGLE PULSE<br>1<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>PULSE TIME t,(s)<br>Figure 11. Thermal Response<br>C, CAPACITANCE (pF)<br>GATE−TO−SOURCE VOLTAGE (V)<br>GS,<br>V<br>, SOURCE CURRENT (A)<br>IS<br>GATE−TO−SOURCE VOLTAGE (V)<br>GS,<br>V<br>r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE<br>**----- End of picture text -----**<br>


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**5** 

**NTJD5121N, NVJD5121N** 

## **Table 1. ORDERING INFORMATION** 

|**Part Number**|**Marking**<br>**(XX)**|**Package**|**Shipping**†|
|---|---|---|---|
|NTJD5121NT1G|TF|SC−88<br>(Pb−Free)|3000 / Tape & Reel|
|NTJD5121NT2G|TF|SC−88<br>(Pb−Free)|3000 / Tape & Reel|
|NVJD5121NT1G|VTF|SC−88<br>(Pb−Free)|3000 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**6** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y 

**==> picture [479 x 420] intentionally omitted <==**

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1<br>SCALE 2:1 2X DATE 11 DEC 2012<br>aaa H D<br>- D H NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>A 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,<br>D GAGE PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-<br>PLANE SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.<br>4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF<br>6 5 4 THE PLASTIC BODY AND DATUM H.<br>L2 L 5. DATUMS A AND B ARE DETERMINED AT DATUM H.<br>E E1 DETAIL A 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THELEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.<br>7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.<br>1 2 3<br>ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN<br>EXCESS OF DIMENSION b AT MAXIMUM  MATERIAL CONDI-<br>2X aaa C TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER<br>bbb H D 2X 3 TIPS RADIUS OF THE FOOT.<br>e MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>B l= 6X b : A −−− −−− 1.10 −−− −−− 0.043<br>ddd M C A-B D A1 0.00 −−− 0.10 0.000 −−− 0.004<br>TOP VIEW A2 0.70 0.90 1.00 0.027 0.035 0.039<br>b 0.15 0.20 0.25 0.006 0.008 0.010<br>C 0.08 0.15 0.22 0.003 0.006 0.009<br>A2 DETAIL A D 1.80 2.00 2.20 0.070 0.078 0.086<br>A E 2.00 2.10 2.20 0.078 0.082 0.086<br>E1 1.15 1.25 1.35 0.045 0.049 0.053<br>e 0.65 BSC 0.026 BSC<br>L 0.26 0.36 0.46 0.010 0.014 0.018<br>L2 0.15 BSC 0.006 BSC<br>aaa 0.15 0.006<br>bbb 0.30 0.012<br>6X ccc C ccc 0.10 0.004<br>(tll, A1 C  A SEATINGPLANE Ma c === ddd 0.10 0.004<br>SIDE VIEW END VIEW GENERIC<br>MARKING DIAGRAM*<br>RECOMMENDED 6<br>SOLDERING FOOTPRINT*<br>6X 6X XXXM<br>0.30 0.66<br>1<br>Ta os 2.50 XXX = Specific Device Code<br>M = Date Code*<br>= Pb−Free Package<br>0.65 yo (Note: Microdot may be in either location)<br>PITCH<br>**----- End of picture text -----**<br>


## DATE 11 DEC 2012 

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 

   - *Date Code orientation and/or position may vary depending upon manufacturing location. 

**==> picture [83 x 5] intentionally omitted <==**

**----- Start of picture text -----**<br>
DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may not follow the Generic Marking. 

## **STYLES ON PAGE 2** 

**DOCUMENT NUMBER: 98ASB42985B** 

**DESCRIPTION: SC−88/SC70−6/SOT−363** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

**PAGE 1 OF 2** 

ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

## **SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y 

## DATE 11 DEC 2012 

|STYLE 1:|STYLE 2:|STYLE 3:|STYLE 4:|STYLE 5:|STYLE 6:|
|---|---|---|---|---|---|
|PIN 1. EMITTER 2|CANCELLED|CANCELLED|PIN 1. CATHODE|PIN 1. ANODE|PIN 1. ANODE 2|
|2. BASE 2|||2. CATHODE|2. ANODE|2. N/C|
|3. COLLECTOR 1|||3. COLLECTOR|3. COLLECTOR|3. CATHODE 1|
|4. EMITTER 1|||4. EMITTER|4. EMITTER|4. ANODE 1|
|5. BASE 1|||5. BASE|5. BASE|5. N/C|
|6. COLLECTOR 2|||6. ANODE|6. CATHODE|6. CATHODE 2|
|STYLE 7:|STYLE 8:|STYLE 9:|STYLE 10:|STYLE 11:|STYLE 12:|
|PIN 1. SOURCE 2|CANCELLED|PIN 1. EMITTER 2|PIN 1. SOURCE 2|PIN 1. CATHODE 2|PIN 1. ANODE 2|
|2. DRAIN 2||2. EMITTER 1|2. SOURCE 1|2. CATHODE 2|2. ANODE 2|
|3. GATE 1||3. COLLECTOR 1|3. GATE 1|3. ANODE 1|3. CATHODE 1|
|4. SOURCE 1||4. BASE 1|4. DRAIN 1|4. CATHODE 1|4. ANODE 1|
|5. DRAIN 1||5. BASE 2|5. DRAIN 2|5. CATHODE 1|5. ANODE 1|
|6. GATE 2||6. COLLECTOR 2|6. GATE 2|6. ANODE 2|6. CATHODE 2|
|STYLE 13:|STYLE 14:|STYLE 15:|STYLE 16:|STYLE 17:|STYLE 18:|
|PIN 1. ANODE|PIN 1. VREF|PIN 1. ANODE 1|PIN 1. BASE 1|PIN 1. BASE 1|PIN 1. VIN1|
|2. N/C|2. GND|2. ANODE 2|2. EMITTER 2|2. EMITTER 1|2. VCC|
|3. COLLECTOR|3. GND|3. ANODE 3|3. COLLECTOR 2|3. COLLECTOR 2|3. VOUT2|
|4. EMITTER|4. IOUT|4. CATHODE 3|4. BASE 2|4. BASE 2|4. VIN2|
|5. BASE|5. VEN|5. CATHODE 2|5. EMITTER 1|5. EMITTER 2|5. GND|
|6. CATHODE|6. VCC|6. CATHODE 1|6. COLLECTOR 1|6. COLLECTOR 1|6. VOUT1|
|STYLE 19:|STYLE 20:|STYLE 21:|STYLE 22:|STYLE 23:|STYLE 24:|
|PIN 1. I OUT|PIN 1. COLLECTOR|PIN 1. ANODE 1|PIN 1. D1 (i)|PIN 1. Vn|PIN 1. CATHODE|
|2. GND|2. COLLECTOR|2. N/C|2. GND|2. CH1|2. ANODE|
|3. GND|3. BASE|3. ANODE 2|3. D2 (i)|3. Vp|3. CATHODE|
|4. V CC|4. EMITTER|4. CATHODE 2|4. D2 (c)|4. N/C|4. CATHODE|
|5. V EN|5. COLLECTOR|5. N/C|5. VBUS|5. CH2|5. CATHODE|
|6. V REF|6. COLLECTOR|6. CATHODE 1|6. D1 (c)|6. N/C|6. CATHODE|
|STYLE 25:|STYLE 26:|STYLE 27:|STYLE 28:|STYLE 29:|STYLE 30:|
|PIN 1. BASE 1|PIN 1. SOURCE 1|PIN 1. BASE 2|PIN 1. DRAIN|PIN 1. ANODE|PIN 1. SOURCE 1|
|2. CATHODE|2. GATE 1|2. BASE 1|2. DRAIN|2. ANODE|2. DRAIN 2|
|3. COLLECTOR 2|3. DRAIN 2|3. COLLECTOR 1|3. GATE|3. COLLECTOR|3. DRAIN 2|
|4. BASE 2|4. SOURCE 2|4. EMITTER 1|4. SOURCE|4. EMITTER|4. SOURCE 2|
|5. EMITTER|5. GATE 2|5. EMITTER 2|5. DRAIN|5. BASE/ANODE|5. GATE 1|
|6. COLLECTOR 1|6. DRAIN 1|6. COLLECTOR 2|6. DRAIN|6. CATHODE|6. DRAIN 1|



Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. 

|**DOCUMENT NUMBER:**|**98ASB42985B**|Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.|Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.|
|---|---|---|---|
|**DESCRIPTION:**|**SC−88/SC70−6/SOT−363**||**PAGE 2 OF 2**|



ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

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