NTHD4508NT1G

## NTHD4508N 

## MOSFET – Power, Dual, N-Channel, ChipFET 20 V, 4.1 A 

## **Features** 

- Low RDS(on) and Fast Switching Speed 

## **http://onsemi.com** 

- Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6 

- Excellent Thermal Capabilities Where Heat Transfer is Required 

- Pb−Free Package is Available 

## **Applications** 

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||||
|---|---|---|
|V(BR)DSS|RDS(on) TYP|ID MAX|
|60 m|@ 4.5 V|
|20 V|4.1 A|
|80 m|@ 2.5 V|

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- DC−DC Buck/Boost Converters 

- Battery and Low Side Switching in Portable Equipment Such as MP3 Players, Cell Phones, DSCs and PDAs 

D1, D21, D2, D22 

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||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
||Battery and Low Side Switching in Portable Equipment Such as MP3|D1, D21, D2, D22|
|Players, Cell Phones, DSCs and PDAs|
|•|Level Shifting|
|MAXIMUM RATINGS|(TJ = 25|°|C unless otherwise noted)|G1, G2|
|Parameter|Symbol|Value|Unit|
|Drain−to−Source Voltage|VDSS|20|V|S1, S2|
|Gate−to−Source Voltage|VGS|±|12|V|N−Channel MOSFET|
|——|Continuous DrainCurrent|_—|SteadyState|TTJ J = 25 = 85|°°|CC|=|ID|==|3.02.2|A|“|
|t|5 s|TJ = 25|°|C|4.1|
|o|Power Dissipation|er]|Steady|TJ = 25|°|C|PD|1.13|W|&|
|State|TJ = 85|°|C|0.59|
|t|5 s|TJ = 25|°|C|2.1|CONNECTIONSPIN|
|Pulsed Drain Current|tp = 10|μ|s|IDM|12|A|
|Operating Junction and Storage Temperature|TTSTGJ,|−55 to150|°|C|D11|8|1|S11|1|
|Lead Temperature for Soldering Purposes|TL|260|°|C|D11|7|2|G11|2|
|(1/8” from case for 10 s)|
|D22|6|3|S22|3|
|THERMAL RESISTANCE RATINGS|
|Parameter|Symbol|Max|Unit|D22|5|4|G22|4|
|:|
|Junction−to−Ambient – Steady State|R|θ|JA|110|°|C/W|
|(Note 1)|

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- Level Shifting 

**ChipFET CASE 1206A STYLE 2** 

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PIN MARKING<br>CONNECTIONSPIN DIAGRAM<br>D11 8 1 S11 1 8<br>D11 7 2 G11 2 7<br>D22 6 3 S22 3 6<br>D22 5 4 G22 4 5<br>:<br>C8 = Specific Device Code<br>M = Month Code<br>C8<br>M<br>**----- End of picture text -----**<br>


Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 

**ORDERING INFORMATION** 

**Device Package Shipping**[†] NTHD4508NT1 ChipFET 3000/Tape & Reel ChipFET NTHD4508NT1G 3000/Tape & Reel ~~EE~~ (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2004 **May, 2019 − Rev. 3** 

**NTHD4508N/D** 

## **NTHD4508N** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**Parameter**|**Symbol**|**Test Conditions**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**OFF CHARACTERISTICS**|||||||
|Drain−to−Source Breakdown Voltage|V(BR)DSS|VGS= 0 V|20|||V|
|Zero Gate Voltage Drain Current|IDSS|VGS= 0 V, VDS= 16 V|||1.0|�A|
|||VGS= 0 V, VDS= 16 V, TJ= 125°C|||10||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=�12 V|||�100|nA|
|**ON CHARACTERISTICS**(Note 2)|||||||
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250�A|0.6||1.2|V|
|Drain−to−Source On−Resistance|RDS(on)|VGS= 4.5, ID= 3.1 A||60|75|m�|
|||VGS= 2.5, ID= 2.3 A||80|115||
|Forward Transconductance|gFS|VDS= 10 V, ID= 3.1 A||6.0||S|
|**CHARGES AND CAPACITANCES**|||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1.0 MHz,<br>VDS= 10 V||180||pF|
|Output Capacitance|COSS|||80|||
|Reverse Transfer Capacitance|CRSS|||25|||
|Total Gate Charge|QG(TOT)|VGS= 4.5 V, VDS= 10 V,<br>ID= 3.1 A||2.6|4.0|nC|
|Threshold Gate Charge|QG(TH)|||0.5|||
|Gate−to−Source Charge|QGS|||0.6|||
|Gate−to−Drain Charge|QGD|||0.7|||
|**SWITCHING CHARACTERISTICS**(Note 3)|||||||
|Turn−On Delay Time|td(ON)|VGS= 4.5 V, VDS= 16 V,<br>ID= 3.1 A, RG= 2.5�||5.0|10|ns|
|Rise Time|tr|||15|30||
|Turn−Off Delay Time|td(OFF)|||10|20||
|Fall Time|tf|||3.0|6.0||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||
|Forward Diode Voltage|VSD|VGS= 0 V, IS= 3.1 A||0.75|1.15|V|
|Reverse Recovery Time|tRR|VGS= 0 V, IS= 1.5 A,<br>dIS/dt = 100 A/�s||12.5||ns|
|Charge Time|ta|||9.0|||
|Discharge Time|tb|||3.5|||
|Reverse Recovery Charge|QRR|||6.0||nC|



2. Pulse Test: Pulse Width � 300 � s, Duty Cycle � 2%. 

3. Switching characteristics are independent of operating junction temperatures. 

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**2** 

**NTHD4508N** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

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8 8<br>VGS = 5 V to 3 V TJ = 25 ° C VDSDS ≥  10 V<br>V GS  = 2.4 V<br>2.2 V 2 V<br>6 6<br>4 1.8 V 4<br>2 1.6 V 2 TC = −55C = −55 = −55 ° C<br>1.4 V 25 ° C 100 ° C<br>0 0<br>0 1 2 3 4 5 6 7 8 9 10 0 0.5 1 1.5 2 2.5<br>VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)GS, GATE−TO−SOURCE VOLTAGE (VOLTS), GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics<br>0.15 0.1<br>ID = 3.1 A TJ = 25 ° C<br>T J  = 25 ° C<br>VGS = 2.5 V<br>0.10<br>0.07<br>VGS = 4.5 V<br>0.05<br>0 0.04<br>0 1 2 3 4 5 6 1 3 5 7<br>VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)<br>Figure 3. On−Resistance vs. Gate−to−Source Figure 4. On−Resistance vs. Drain Current and<br>Voltage Gate Voltage<br>DRAIN CURRENT (AMPS) DRAIN CURRENT (AMPS)<br>ID,  ID, D,<br>) � ) �<br>DRAIN−TO−SOURCE RESISTANCE ( DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),  DS(on),<br>R R<br>**----- End of picture text -----**<br>


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8<br>VDSDS ≥  10 V<br>6<br>4<br>2 TC = −55C = −55 = −55 ° C<br>25 ° C 100 ° C<br>0<br>0 0.5 1 1.5 2 2.5 3<br>VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)GS, GATE−TO−SOURCE VOLTAGE (VOLTS), GATE−TO−SOURCE VOLTAGE (VOLTS)<br>DRAIN CURRENT (AMPS)<br>ID, D,<br>**----- End of picture text -----**<br>


**Figure 3. On−Resistance vs. Gate−to−Source Voltage** 

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1.7 100<br>ID = 3.1 A VGS = 0 V<br>VGS = 4.5 V<br>1.5<br>1.3 TJ = 100 ° C<br>10<br>1.1<br>0.9<br>0.7 1<br>−50 −25 0 25 50 75 100 125 150 2 4 6 8 10 12 14 16 18 20<br>TJ, JUNCTION TEMPERATURE ( ° C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>DRAIN−TO−SOURCE , LEAKAGE (nA)<br>IDSS<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

**Figure 6. Drain−to−Source Leakage Current vs. Voltage** 

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**3** 

**NTHD4508N** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

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400 5<br>CISS VDS = 0 V VGS = 0 V TJ = 25 ° C QG 10<br>4<br>300<br>7.5<br>C RSS 3<br>200<br>5.0<br>2 Q GS Q GD<br>100<br>2.5<br>COSS 1<br>ID = 3.1 A<br>TJ = 25 ° C<br>0 0 0<br>10 5 0 5 10 15 20 0 0.5 1 1.5 2 2.5 3<br>VGS VDS QG, TOTAL GATE CHARGE (nC)<br>GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 8. Gate−to−Source and<br>Figure 7. Capacitance Variation Drain−to−Source Voltage vs. Total Charge<br>100 7<br>VDD = 16 V VGS = 0 V<br>ID = 2.3 A 6 TJ = 25 ° C<br>VGS = 4.5 V<br>5<br>4<br>10 td(off)<br>tr 3<br>td(on)<br>tf 2<br>1<br>1 0<br>1 10 100 0.3 0.45 0.6 0.75 0.9 1.05 1.2<br>RG, GATE RESISTANCE (OHMS) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>C, CAPACITANCE (pF)<br>GATE−TO−SOURCE VOLTAGE (VOLTS) DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>GS,  DS,<br>V V<br>t, TIME (ns)<br>, SOURCE CURRENT (AMPS)<br>IS<br>**----- End of picture text -----**<br>


**Figure 9. Resistive Switching Time Variation vs. Gate Resistance** 

**Figure 10. Diode Forward Voltage vs. Current** 

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**4** 

**NTHD4508N** 

## **SOLDERING FOOTPRINTS*** 

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2.032 2.032<br>0.08 0.08<br>0.457<br>0.018<br>0.635 0.635 1.032<br>0.025 0.025 0.043<br>0.178<br>0.007<br>0.457<br>0.018<br>0.711<br>0.254<br>0.028<br>0.010<br>0.66 0.66<br>0.026 0.026 SCALE 20:1 � inches [mm] �<br>Figure 11. Basic Figure 12. Style 2<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

## **BASIC PAD PATTERNS** 

The basic pad layout with dimensions is shown in Figure 11. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. 

The minimum recommended pad pattern shown in Figure 12 improves the thermal area of the drain connections (pins 5, 6, 7, 8) while remaining within the confines of the basic 

footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq. mm). This will assist the power dissipation path away from the device (through the copper lead−frame) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. 

ChipFET is a trademark of Vishay Siliconix. 

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**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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ChipFET<br>8 CASE1206A−03<br>ISSUE K<br>DATE  19 MAY 2009<br>&<br>1<br>SCALE 1:1<br>D NOTES:<br>1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>8 7 6 5 L 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.<br>4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL<br>5 6 7 8<br>AND VERTICAL SHALL NOT EXCEED 0.08 MM.<br>ft HE oem E O t 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.<br>4 3 2 1 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD<br>1 2 3 4 SURFACE.<br>MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>e1 b c A 1.00 1.05 1.10 0.039 0.041 0.043<br>e b 0.25 0.30 0.35 0.010 0.012 0.014<br>c 0.10 0.15 0.20 0.004 0.006 0.008<br>D 2.95 3.05 3.10 0.116 0.120 0.122<br>Lolqe RESET  ieeeeee E 1.55 1.65 1.70 0.061 0.065 0.067<br>e 0.65 BSC 0.025 BSC<br>A e1 0.55 BSC 0.022 BSC<br>L 0.28 0.35 0.42 0.011 0.014 0.017<br>H E 1.80 1.90 2.00 0.071 0.075 0.079<br>= 0.05 (0.002) 5° NOM 5° NOM<br>STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: STYLE 6:<br>PIN 1. DRAIN PIN 1. SOURCE 1 PIN 1. ANODE PIN 1. COLLECTOR PIN 1. ANODE PIN 1. ANODE<br> 2. DRAIN  2. GATE 1  2. ANODE  2. COLLECTOR  2. ANODE  2. DRAIN<br> 3. DRAIN  3. SOURCE 2  3. SOURCE  3. COLLECTOR  3. DRAIN  3. DRAIN<br> 4. GATE  4. GATE 2  4. GATE  4. BASE  4. DRAIN  4. GATE<br> 5. SOURCE  5. DRAIN 2  5. DRAIN  5. EMITTER  5. SOURCE  5. SOURCE<br> 6. DRAIN  6. DRAIN 2  6. DRAIN  6. COLLECTOR  6. GATE  6. DRAIN<br> 7. DRAIN  7. DRAIN 1  7. CATHODE  7. COLLECTOR  7. CATHODE  7. DRAIN<br> 8. DRAIN  8. DRAIN 1  8. CATHODE  8. COLLECTOR  8. CATHODE  8. CATHODE / DRAIN<br>SOLDERING FOOTPRINT GENERIC<br>MARKING DIAGRAM*<br>2.032<br>0.08<br>1<br>xxx M<br>xxx = Specific Device Code<br>M = Month Code<br>= Pb−Free Package<br>2.362 lols 0.65 (Note: Microdot may be in either location)<br>0.093<br>0.025 *This information is generic. Please refer to<br>PITCH device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ ”,<br>oa may or may not be present.<br>8X<br>8X Le 0.457 -—} 0.66 +<br>0.018 0.026<br>mm<br>7 > -b = inches<br>Basic Style<br>**----- End of picture text -----**<br>


## **OPTIONAL SOLDERING FOOTPRINTS ON PAGE 2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON03078D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: ChipFET PAGE 1 OF 2** ~~ee~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

DATE 19 MAY 2009 

**ChipFET** CASE 1206A−03 ISSUE K 

**ADDITIONAL SOLDERING FOOTPRINTS*** 

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2.032 2.032<br>0.08 0.08<br>1 1<br>re nm | 0.457 to<br>4X<br>0.018<br>2X<br>1.092<br>0.043<br>1.727<br>0.068<br>2.362 2.362<br>0.093 0.093<br>0.65<br>C t BEE<br>0.025<br>PITCH<br>4X 2X<br>Y o = 2X " in<br>0.66 1.118<br>0.457 0.66<br>2X 0.018 0.026 mm 0.026 0.044 inchesmm<br>— 4b inches Ara<br>Styles 1 and 4 Style 2<br>2.032 2.032<br>0.08 2X 0.08 2X<br>0.66 0.66<br>1 mp 0.026 1 eet 0.026<br>1.092 1.092<br>0.043 0.043<br>2.362 2.362<br>0.093 0.093<br>ue 0.65 0.65<br>0.025 0.025<br>PITCH PITCH<br>S l 1.118 | | | LIE 1.118 =<br>2X 0.457 0.044 0.044 2X 0.457<br>0.018 — a 0.018<br>mm mm<br>I) inches — a inches<br>Style 3 Style 5<br>**----- End of picture text -----**<br>


- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON03078D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: ChipFET PAGE 2 OF 2** ~~a~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

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