NTHD4102PT1G

## NTHD4102P 

## MOSFET – Dual, P-Channel, ChipFET 

## -20 V, -4.1 A 

## **Features** 

## **http://onsemi.com** 

- Offers an Ultra Low RDS(ON) Solution in the ChipFET Package 

- Miniature ChipFET Package 40% Smaller Footprint than TSOP−6 

- Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin Environments such as Portable Electronics 

- Simplifies Circuit Design since Additional Boost Circuits for Gate Voltages are not Required 

- Operated at Standard Logic Level Gate Drive, Facilitating Future Migration to Lower Levels using the same Basic Topology 

- Pb−Free Package is Available 

## **Applications** 

- Optimized for Battery and Load Management Applications in Portable Equipment such as MP3 Players, Cell Phones, and PDAs 

- Charge Control in Battery Chargers 

- Buck and Boost Converters 

|**V(BR)DSS**|**RDS(ON) TYP**|**ID MAX**|
|---|---|---|
||64 m @ −4.5 V||
|−20 V|85 m @ −2.5 V|−4.1 A|



120 m @ −1.8 V 

S1 S2 G1 G2 ~~od~~ D1 D2 **P−Channel MOSFET P−Channel MOSFET** 

**MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

|**MAXIMUM RATINGS**(TJ = 25J = 25= 25°C unless otherwise noted)|**MAXIMUM RATINGS**(TJ = 25J = 25= 25°C unless otherwise noted)|**MAXIMUM RATINGS**(TJ = 25J = 25= 25°C unless otherwise noted)|C unless otherwise noted)|||
|---|---|---|---|---|---|
|**Parameter**|||**Symbol**|**Value**|**Unit**|
|Drain−to−Source Voltage|||VDSS|−20|V|
|Gate−to−Source Voltage|||VGS|8.0|V|
|Continuous Drain<br>Current (Note 1)|Steady State|TA= 25°C|ID|−2.9|A|
|||TA= 85°C||−2.1||
||t≤10 s|TA= 25°C||−4.1||
|Power Dissipation<br>(Note 1)|Steady State|TA= 25°C|PD|1.1|W|
||t≤10 s|||2.1||
|Pulsed Drain<br>Current|tp= 10 s||IDM|−16|A|
|Operating Junction and Storage Temperature|||TJ,<br>TSTG|−55 to<br>150|°C|
|Source Current (Body Diode)<br>~~ee~~|||IS<br>~~eee~~|−1.1<br>~~eee~~|A<br>~~eee~~|
|Lead Temperature for Soldering<br>Purposes (1/8” from case for 10 s)<br>~~ee~~|||TL<br>~~eee~~|260<br>~~eee~~|°C<br>~~eee~~|



Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 

1. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces) 

**ChipFET CASE 1206A STYLE 2 PIN MARKING CONNECTIONS DIAGRAM** D1 8 1 S1 1 8 D1 7 2 G1 2 7 D2 6 3 S2 3 6 D2 5 4 G2 4 5 ~~i~~ C7 = Specific Device Code M = Month Code = Pb−Free Package : **ORDERING INFORMATION Device Package Shipping**[†] NTHD4102PT1 ChipFET 3000/Tape & Reel NTHD4102PT1G ChipFET 3000/Tape & Reel (Pb−Free) ~~———~~ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2011 **May, 2019 − Rev. 6** 

**NTHD4102P/D** 

**NTHD4102P** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C u|nless otherw|ise noted)|ise noted)|||||
|---|---|---|---|---|---|---|---|
|**Characteristic**|**Symbol**|**Test Condition**||**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|Drain−to−Source Breakdown Voltage|V(Br)DSS|VGS= 0 V, ID= −250�A||−20|||V|
|Drain−to−Source Breakdown Voltage<br>Temperature Coefficient|V(Br)DSS/TJ||||−15||mV/°C|
|Zero Gate Voltage Drain Current|IDSS|VGS=  0 V<br>VDS= −16 V|TJ= 25°C|||−1.0|�A|
||||TJ= 85°C|||−5.0||
|Gate−to−Source Leakage Current|IGSS|VDS= 0 V, VGS=�8.0 V||||�100|nA|
|**ON CHARACTERISTICS**(Note 2)||||||||
|Gate Threshold Voltage|VGS(TH)|VGS=  VDS,ID= −250�A||−0.45||−1.5|V|
|Gate Threshold Temperature Coefficient|VGS(TH)/TJ||||2.7||mV/°C|
|Drain−to−Source On Resistance|RDS(ON)|VGS= −4.5 V, ID= −2.9 A|||64|80|m�|
|||VGS= −2.5 V, ID= −2.2 A|||85|110||
|||VDS= −1.8 V, ID= −1.0 A|||120|170||
|Forward Transconductance|gFS|VDS= −10 V, ID= −2.9 A|||7.0||S|
|**CHARGES, CAPACITANCES, AND GATE RESISTANCE**||||||||
|Input Capacitance|CISS|VGS= 0 V, f = 1.0 MHz,<br>VDS= −16 V|||750||pF|
|Output Capacitance|COSS||||100|||
|Reverse Transfer Capacitance|CRSS||||45|||
|Total Gate Charge|QG(TOT)|VGS= −4.5 V, VDS= −16 V,<br>ID= −2.6 A|||7.6|8.6|nC|
|Gate−to−Source Charge|QGS||||1.3|||
|Gate−to−Drain Charge|QGD||||2.6|||
|**SWITCHING CHARACTERISTICS**(Note 3)||||||||
|Turn−On Delay Time|td(ON)|VGS= −4.5 V, VDD= −16 V,<br>ID= −2.6 A, RG= 2.0�|||5.5|10|ns|
|Rise Time|tr||||12|25||
|Turn−Off Delay Time|td(OFF)||||32|40||
|Fall Time|tf||||23|35||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||||
|Forward Diode Voltage|VSD|VGS= 0 V, IS= −1.1 A|||−0.8|−1.2|V|
|Reverse Recovery Time|tRR|VGS= 0 V, dIS/dt = 100 A/�s,<br>IS= 1.0 A|||20|40|ns|
|Charge Time|ta||||15|||
|Discharge Time|tb||||5|||
|Reverse Recovery Charge|QRR||||0.01||�C|



2. Pulse test: pulse width ≤ 300 � s, duty cycle ≤ 2% 

3. Switching characteristics are independent of operating junction temperatures 

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**2** 

**NTHD4102P** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

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**----- Start of picture text -----**<br>
10 VGS = −10 V to −2.8 V TJ = 25 ° C<br>9<br>8<br>−2.4 V<br>7<br>6<br>5<br>4<br>3<br>2 −1.8 V<br>1 −1.6 V<br>−1.4 V<br>0<br>0 1 2 3 4 5 6 7 8<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 1. On−Region Characteristics<br>0.2<br>0.18<br>0.16<br>0.14 VGS = −2.5 VGS = −2.5 V = −2.5 V<br>0.12<br>0.1<br>0.08 VGS = −4.5 VGS = −4.5 V = −4.5 V<br>0.06<br>0.04<br>0.02<br>0<br>2 3 4 5 6<br>−ID, DRAIN CURRENT (AMPS)<br>DRAIN CURRENT (AMPS)<br>D,<br>−I<br>) �<br>DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),<br>R<br>**----- End of picture text -----**<br>


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9<br>8<br>7<br>6<br>5<br>4<br>3<br>125 ° C<br>2<br>25 ° C<br>1 TJ = −55 ° C<br>0<br>0 0.5 1 1.5 2 2.5 3 3.5 4<br>−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>DRAIN CURRENT (AMPS)<br>D,<br>−I<br>**----- End of picture text -----**<br>


**Figure 2. Transfer Characteristics** 

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**----- Start of picture text -----**<br>
1.5<br>VGS = −4.5 V<br>1.3<br>VGS = −2.5 VGS = −2.5 V = −2.5 V<br>1.1<br>VGS = −4.5 VGS = −4.5 V = −4.5 V 0.9<br>0.7<br>0.5<br>4 5 6 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 4. On−Resistance Variation with<br>Temperature<br>10000<br>VGS = 0 V<br>1000 TJ = 125 ° C<br>TJ = 100 ° C<br>100<br>10<br>1 TJ = 25 ° C<br>0.1<br>2 3 4 5 6 7 8<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>DRAIN−TO−SOURCE<br>DS(on),<br>R RESISTANCE (NORMALIZED)<br>, LEAKAGE (nA)<br>DSS<br>−I<br>**----- End of picture text -----**<br>


**Figure 3. On−Resistance vs. Drain Current and Gate Voltage** 

**Figure 5. Drain−to−Source Leakage Current vs. Voltage** 

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**3** 

**NTHD4102P** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

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**----- Start of picture text -----**<br>
1000 5<br>900 TJ = 25 ° C QT<br>800 4<br>700 Ciss<br>600 3<br>500<br>Q1 Q2<br>400 2<br>300<br>200 1<br>100 Crss Coss TIDJ = −2.7 A = 25 ° C<br>0 0<br>0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 6 7 8<br>−VGS −VDS Qg, TOTAL GATE CHARGE (nC)<br>GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 7. Gate−to−Source and Drain−to−Source<br>Figure 6. Capacitance Variation Voltage vs. Total Gate Charge<br>1000 5<br>VDD = −10 V VGS = 0 V<br>ID = −1.0 A TJ = 25 ° C<br>VGS = −4.5 V 4<br>100<br>3<br>td(off)<br>tf 2<br>10 tr<br>td(on)<br>1<br>1 0<br>1 10 100 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2<br>RG, GATE RESISTANCE (OHMS) −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)<br>Figure 8. Resistive Switching Time Variation Figure 9. Diode Forward Voltage vs. Current<br>vs. Gate Resistance<br>100<br>10 10  � s<br>100  � s<br>1 ms<br>1 10 ms<br>VGS = −8 V<br>SINGLE PULSE<br>TC = 25 ° C<br>0.1<br>RDS(on) LIMIT dc<br>THERMAL LIMIT<br>PACKAGE LIMIT<br>0.01<br>0.1 1 10 100<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>C, CAPACITANCE (pF)<br>GATE−TO−SOURCE VOLTAGE (VOLTS) , DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>GS,<br>DS<br>−V<br>−V<br>t, TIME (ns)<br>, SOURCE CURRENT (AMPS)<br>S<br>−I<br>−ID, DRAIN CURRENT (AMPS)<br>**----- End of picture text -----**<br>


**Figure 10. Maximum Rated Forward Biased Safe Operating Area** 

ChipFET is a trademark of Vishay Siliconix. 

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**4** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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ChipFET<br>8 CASE1206A−03<br>ISSUE K<br>DATE  19 MAY 2009<br>&<br>1<br>SCALE 1:1<br>D NOTES:<br>1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>8 7 6 5 L 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.<br>4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL<br>5 6 7 8<br>AND VERTICAL SHALL NOT EXCEED 0.08 MM.<br>ft HE oem E O t 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.<br>4 3 2 1 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD<br>1 2 3 4 SURFACE.<br>MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>e1 b c A 1.00 1.05 1.10 0.039 0.041 0.043<br>e b 0.25 0.30 0.35 0.010 0.012 0.014<br>c 0.10 0.15 0.20 0.004 0.006 0.008<br>D 2.95 3.05 3.10 0.116 0.120 0.122<br>Lolqe RESET  ieeeeee E 1.55 1.65 1.70 0.061 0.065 0.067<br>e 0.65 BSC 0.025 BSC<br>A e1 0.55 BSC 0.022 BSC<br>L 0.28 0.35 0.42 0.011 0.014 0.017<br>H E 1.80 1.90 2.00 0.071 0.075 0.079<br>= 0.05 (0.002) 5° NOM 5° NOM<br>STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: STYLE 6:<br>PIN 1. DRAIN PIN 1. SOURCE 1 PIN 1. ANODE PIN 1. COLLECTOR PIN 1. ANODE PIN 1. ANODE<br> 2. DRAIN  2. GATE 1  2. ANODE  2. COLLECTOR  2. ANODE  2. DRAIN<br> 3. DRAIN  3. SOURCE 2  3. SOURCE  3. COLLECTOR  3. DRAIN  3. DRAIN<br> 4. GATE  4. GATE 2  4. GATE  4. BASE  4. DRAIN  4. GATE<br> 5. SOURCE  5. DRAIN 2  5. DRAIN  5. EMITTER  5. SOURCE  5. SOURCE<br> 6. DRAIN  6. DRAIN 2  6. DRAIN  6. COLLECTOR  6. GATE  6. DRAIN<br> 7. DRAIN  7. DRAIN 1  7. CATHODE  7. COLLECTOR  7. CATHODE  7. DRAIN<br> 8. DRAIN  8. DRAIN 1  8. CATHODE  8. COLLECTOR  8. CATHODE  8. CATHODE / DRAIN<br>SOLDERING FOOTPRINT GENERIC<br>MARKING DIAGRAM*<br>2.032<br>0.08<br>1<br>xxx M<br>xxx = Specific Device Code<br>M = Month Code<br>= Pb−Free Package<br>2.362 lols 0.65 (Note: Microdot may be in either location)<br>0.093<br>0.025 *This information is generic. Please refer to<br>PITCH device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ ”,<br>oa may or may not be present.<br>8X<br>8X Le 0.457 -—} 0.66 +<br>0.018 0.026<br>mm<br>7 > -b = inches<br>Basic Style<br>**----- End of picture text -----**<br>


## **OPTIONAL SOLDERING FOOTPRINTS ON PAGE 2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON03078D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: ChipFET PAGE 1 OF 2** ~~ee~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

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© Semiconductor Components Industries, LLC, 2019 

DATE 19 MAY 2009 

**ChipFET** CASE 1206A−03 ISSUE K 

**ADDITIONAL SOLDERING FOOTPRINTS*** 

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**----- Start of picture text -----**<br>
2.032 2.032<br>0.08 0.08<br>1 1<br>re nm | 0.457 to<br>4X<br>0.018<br>2X<br>1.092<br>0.043<br>1.727<br>0.068<br>2.362 2.362<br>0.093 0.093<br>0.65<br>C t BEE<br>0.025<br>PITCH<br>4X 2X<br>Y o = 2X " in<br>0.66 1.118<br>0.457 0.66<br>2X 0.018 0.026 mm 0.026 0.044 inchesmm<br>— 4b inches Ara<br>Styles 1 and 4 Style 2<br>2.032 2.032<br>0.08 2X 0.08 2X<br>0.66 0.66<br>1 mp 0.026 1 eet 0.026<br>1.092 1.092<br>0.043 0.043<br>2.362 2.362<br>0.093 0.093<br>ue 0.65 0.65<br>0.025 0.025<br>PITCH PITCH<br>S l 1.118 | | | LIE 1.118 =<br>2X 0.457 0.044 0.044 2X 0.457<br>0.018 — a 0.018<br>mm mm<br>I) inches — a inches<br>Style 3 Style 5<br>**----- End of picture text -----**<br>


- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON03078D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: ChipFET PAGE 2 OF 2** ~~a~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

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