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NP75N04YUK-E1-AY
Power MOSFET, N Channel, 40 V, 75 A, 3300 µohm, HSON, Surface Mount
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- Manufacturer: RENESAS
- Product type:
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 8Pins
- Channel Type: N Channel
- Product Range: NP75N04YUK Series
- Qualification: AEC-Q101
- Power Dissipation: 138W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: HSON
- Drain Source Voltage Vds: 40V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 75A
- Drain Source On State Resistance: 3300µohm
- Gate Source Threshold Voltage Max: 4V
| Delivery and price | |
|---|---|
| Units per pack | 2500 |
| Price | 0.733 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
Preliminary Data Sheet ## **NP75N04YUK** 40 V – 75 A – N-channel Power MOS FET Application: Automotive R07DS1004EJ0200 Rev.2.00 May 24, 2018 ## **Description** The NP75N04YUK is N-channel MOS Field Effect Transistors designed for high current switching applications. ## **Features** - Super low on-state resistance - RDS(on) = 3.3 m MAX. (VGS = 10 V, ID = 38 A) - Non logic level drive type - Designed for automotive application and AEC-Q101 qualified ## **Ordering Information** |**Part No.**|**Lead Plating**|**Packing**|**Packing**|**Package **| |---|---|---|---|---| |NP75N04YUK-E1-AY*1|Pure Sn (Tin)|Tape 2500 p/reel|Taping (E1 type)|8-pin HSON| |NP75N04YUK-E2-AY*1|||Taping (E2 type)|| Note: * 1 Pb-free (This product does not contain Pb in the external electrode) ## **Absolute Maximum Ratings** (TA = 25°C) |**Absolute Maximum Ratings**(TA|= 25°C)||| |---|---|---|---| |**Item**|**Symbol**|**Ratings **|**Unit**| |Drain to Source Voltage(VGS= 0 V)|VDSS|40|V| |Gate to Source Voltage(VDS= 0 V)|VGSS|20|V| |Drain Current(DC) (TC= 25°C)|ID(DC)|75|A| |Drain Current(pulse) *1, 4|ID(pulse)|300|A| |Total Power Dissipation(TC= 25°C)|PT1|138|W| |Total Power Dissipation(TA= 25°C) *2|PT2|1.0|W| |Channel Temperature|Tch|175|°C| |Storage Temperature|Tstg|–55 to +175|°C| |Repetitive Avalanche Current*3, 4|IAR|35|A| |Repetitive Avalanche Energy *3, 4|EAR|123|mJ| ## **Thermal Resistance** Channel to Case Thermal Resistance Rth(ch-C)*4 1.09 °C/W Channel to Ambient Thermal Resistance Rth(ch-A) *4 150 °C/W Notes: *1 TC = 25°C, PW 10 s, Duty Cycle 1% - *2 Mounted on glass epoxy substrate of 40 mm 40 mm 1.6 mmt with 4% Copper area (35 m) - *3 RG = 25 , VGS = 20 V 0 V - *4. Not subject of production test. Verified by design/characterization. R07DS1004EJ0200 Rev.2.00 May 24, 2018 Page 1 of 4 **NP75N04YUK** **Preliminary** ## **Electrical Characteristics** (TA = 25°C) |**Item**|**Symbol**|**MIN.**|**TYP.**|**MAX.**|**Unit**|**Test Conditions**| |---|---|---|---|---|---|---| |Zero Gate Voltage Drain Current|IDSS|—|—|1|A|VDS= 40 V, VGS= 0 V| |Gate Leakage Current|IGSS|—|—|100|nA|VGS=20 V, VDS= 0 V| |Gate to Source Threshold Voltage|VGS(th)|2.0|3.0|4.0|V|VDS= VGS, ID= 250A| |Forward Transfer Admittance*1|| yfs ||31|62|—|S|VDS= 5 V, ID= 38 A| |Drain to Source On-state Resistance*1|RDS(on)|—|2.6|3.3|m|VGS= 10 V, ID= 38 A| |Input Capacitance*2|Ciss|—|3400|5100|pF|VDS= 25 V<br>VGS= 0 V<br>f = 1 MHz| |Output Capacitance*2|Coss|—|480|720|pF|| |Reverse Transfer Capacitance*2|Crss|—|180|330|pF|| |Turn-on DelayTime*2|td(on)|—|24|48|ns|VDD= 20 V, ID= 38 A<br>VGS= 10 V<br>RG= 0| |Rise Time*2|tr|—|10|25|ns|| |Turn-off DelayTime*2|td(off)|—|60|120|ns|| |Fall Time*2|tf|—|7|17|ns|| |Total Gate Charge*2|QG|—|58|87|nC|VDD= 32 V<br>VGS= 10 V<br>ID= 75 A| |Gate to Source Charge|QGS|—|16|—|nC|| |Gate to Drain Charge|QGD|—|15|—|nC|| |BodyDiode Forward Voltage*1|VF(S-D)|—|0.9|1.5|V|IF= 75 A, VGS= 0 V| |Reverse RecoveryTime|trr|—|42|—|ns|IF= 75 A, VGS= 0 V<br>di/dt = 100 A/s| |Reverse RecoveryCharge|Qrr|—|51|—|nC|| Note: *1 Pulsed test Note: *2 Not subject of production test. Verified by design/characterization. ## **TEST CIRCUIT 1 AVALANCHE CAPABILITY** ## **TEST CIRCUIT 2 SWITCHING TIME** **==> picture [164 x 138] intentionally omitted <==** **----- Start of picture text -----**<br> D.U.T.<br>RG = 25 Ω L<br>PG.<br>50 Ω VDD<br>VGS = 20 → 0 V<br>BVDSS<br>ID IAS VDS<br>VDD<br>Starting Tch<br>**----- End of picture text -----**<br> **==> picture [274 x 132] intentionally omitted <==** **----- Start of picture text -----**<br> D.U.T.<br>VGS<br>PG. RG RL Wave FormVGS 0 10% VGS 90%<br>VDD<br>VDS<br>90% 90%<br>VGS VDS<br>0 VDS 0 1 0% 10%<br>Wave Form<br>τ td(on) tr td(off) tf<br>τ = 1 μs ton toff<br>Duty Cycle ≤ 1%<br>**----- End of picture text -----**<br> ## **TEST CIRCUIT 3 GATE CHARGE** **==> picture [122 x 57] intentionally omitted <==** **----- Start of picture text -----**<br> D.U.T.<br>IG = 2 mA RL<br>PG.<br>50 Ω VDD<br>**----- End of picture text -----**<br> R07DS1004EJ0200 Rev.2.00 May 24, 2018 Page 2 of 4 **NP75N04YUK** **Preliminary** ## **Typical Characteristics** (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA **==> picture [199 x 172] intentionally omitted <==** **----- Start of picture text -----**<br> 120<br>100<br>80<br>60<br>40<br>20<br>0<br>0 25 50 75 100 125 150 175<br>TC - Case Temperature - °C<br>dT - Percentage of Rated Power - %<br>**----- End of picture text -----**<br> TOTAL POWER DISSIPATION vs. CASE TEMPERATURE **==> picture [199 x 172] intentionally omitted <==** **----- Start of picture text -----**<br> 160<br>140<br>120<br>100<br>80<br>60<br>40<br>20<br>0<br>0 25 50 75 100 125 150 175<br>TC - Case Temperature - °C<br> - Total Power Disslpation - W<br>T<br>P<br>**----- End of picture text -----**<br> FORWARD BIAS SAFE OPERATING AREA **==> picture [386 x 419] intentionally omitted <==** **----- Start of picture text -----**<br> 1000<br>ID(Pulse) = 300 A<br>R DS(ON) Limited<br>(VGS=10 V)<br>100<br>I D(DC) = 75A<br>10<br>Power Dissipation Limited<br>1 Secondary Breakdown Limited<br>TC = 25 ° C<br>Single Pulse<br>0.1<br>0.1 1 10 100<br>VDS - Drain to Source Voltage - V<br>TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH<br>1000<br>R = 150°C/W<br>th(ch-A)<br>100<br>10<br>R = 1.09°C/W<br>th(ch-C)<br>1<br>0.1<br>Single pulse<br>Mounted on glass epoxy substrate of 40 mm × 40 mm × 1.6 mmt<br>with 4% copper area (35 μ m)<br>0.01<br>100 μ 1 m 10 m 100 m 1 10 100 1000<br>PW - Pulse Width - s<br>PW = 100<br>μs<br>PW = 1 ms<br>PW = 10 ms<br>DC<br> - Drain Current - A<br>ID<br> - Transient Thermal Resistance - °C/W<br>th(t)<br>R<br>**----- End of picture text -----**<br> R07DS1004EJ0200 Rev.2.00 May 24, 2018 Page 3 of 4 **NP75N04YUK** **Preliminary** ## DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE **==> picture [199 x 172] intentionally omitted <==** **----- Start of picture text -----**<br> 350<br>300<br>250<br>200<br>150<br>100<br>50 V GS = 10 V<br>Pulsed<br>0<br>0 0.2 0.4 0.6 0.8 1.0 1.2 1.4<br>VDS - Drain to Source Voltage - V<br> - Drain Current - A<br>ID<br>**----- End of picture text -----**<br> GATE TO SOURCE THRESHOLD VOLTAGE vs. CHANNEL TEMPERATURE **==> picture [200 x 183] intentionally omitted <==** **----- Start of picture text -----**<br> 4<br>3<br>2<br>1<br>VDS = VGS<br>ID = 250 μA<br>0<br>–100 –50 0 50 100 150 200<br>Tch - Channel Temperature - °C<br> - Gate to Source Threshold Voltage - V<br>GS(th)<br>V<br>**----- End of picture text -----**<br> **==> picture [207 x 195] intentionally omitted <==** **----- Start of picture text -----**<br> DRAIN TO SOURCE ON-STATE RESISTANCE vs.<br>DRAIN CURRENT<br>6<br>5<br>4<br>3<br>2<br>1 VGS = 10 V<br>Pulsed<br>0<br>1 10 100 1000<br>ID - Drain Current - A<br>Ω<br> - Drain to Source On-State Resistance - m<br>DS(on)<br>R<br>**----- End of picture text -----**<br> ## FORWARD TRANSFER CHARACTERISTICS **==> picture [200 x 387] intentionally omitted <==** **----- Start of picture text -----**<br> 100<br>10 T A = –55°C<br>25°C<br>75°C<br>125°C<br>1 175 ° C<br>0.1<br>0.01<br>VDS = 10 V<br>Pulsed<br>0.001<br>0 1 2 3 4 5 6<br>VGS - Gate to Source Voltage - V<br>FORWARD TRANSFER ADMITTANCE vs.<br>DRAIN CURRENT<br>100<br>T A = –55°C<br>25°C<br>75°C<br>125°C<br>175°C<br>10<br>V DS = 5 V<br>Pulsed<br>1<br>0.1 1 10 100<br>ID - Drain Current - A<br> - Drain Curent - A<br>ID<br>| - Forward Transfer Admittance - S<br>fs<br>|y<br>**----- End of picture text -----**<br> DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE **==> picture [197 x 193] intentionally omitted <==** **----- Start of picture text -----**<br> GATE TO SOURCE VOLTAGE<br>6<br>5<br>4<br>3<br>2<br>1 ID = 38 A<br>Pulsed<br>0<br>0 5 10 15 20<br>VGS - Gate to Source Voltage - V<br>Ω<br> - Drain to Source On-State Resistance - m<br>DS(on)<br>R<br>**----- End of picture text -----**<br> R07DS1004EJ0200 Rev.2.00 May 24, 2018 Page 4 of 4 **NP75N04YUK** **Preliminary** DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE **==> picture [441 x 624] intentionally omitted <==** **----- Start of picture text -----**<br> CHANNEL TEMPERATURE<br>6 10000<br>5<br>Ciss<br>4<br>3 1000<br>2<br>Coss<br>VGS = 10 V<br>1 Pulsed ID = 38 A V f = 1 MHzGS = 0 V Crss<br>0 100<br>–100 –50 0 50 100 150 200 0.1 1 10 100<br>Tch - Channel Temperature - °C VDS - Drain to Source Voltage - V<br>SWITCHING CHARACTERISTICS DYNAMIC INPUT/OUTPUT CHARACTERISTICS<br>1000 35<br>VVDDGS = 20 V= 10 V 30 VDDDD = 32 V20 V 32 V20 V20 V<br>RG = 0 Ω 8 V<br>25<br>100<br>td(off)<br>20 8<br>td(on) 15 V GS 6<br>10 tr<br>10 4<br>tf<br>5 2<br>VDSDS ID = 75 AD = 75 A = 75 A<br>1 0 0<br>0.1 1 10 100 0 10 20 30 40 50 60<br>ID - Drain Current - A QG- Gate Charge - nCG- Gate Charge - nC- Gate Charge - nC<br>SOURCE TO DRAIN DIODE FORWARD VOLTAGE REVERSE RECOVERY TIME vs.<br>DRAIN CURRENT<br>1000 100<br>VGS = 10 V VGS = 0 V<br>100<br>10 10<br>1<br>di/dt = 100 A/μs<br>Pulsed VGS = 0 V<br>0.1 1<br>0 0.2 0.4 0.6 0.8 1.0 1.2 0.1 1 10 100<br>VF(S-D) - Source to Drain Voltage - V IF - Drain Current - A<br>Ω<br> - Capacitance -pF<br>rss<br>, C<br>oss<br>, C<br>iss<br>C<br> - Drain to Source On-State Resistance - m<br>DS(on)<br>R<br> - Switching Time - ns, tf<br>d(off)<br>, tr<br> - Drain to Source Voltage - V<br>, t<br>DS<br>V<br>td(on)<br> - Diode Forward Current - A<br>IF - Reverse Recovery Time - nstrr<br>**----- End of picture text -----**<br> DYNAMIC INPUT/OUTPUT CHARACTERISTICS **==> picture [225 x 172] intentionally omitted <==** **----- Start of picture text -----**<br> 35 14<br>30 VDDDD = 32 V20 V 32 V20 V20 V 12<br>8 V<br>25 10<br>20 8<br>15 V GS 6<br>10 4<br>5 2<br>VDSDS ID = 75 AD = 75 A = 75 A<br>0 0<br>0 10 20 30 40 50 60<br>QG- Gate Charge - nCG- Gate Charge - nC- Gate Charge - nC<br> - Drain to Source Voltage - V - Gate to Source Voltage - V<br>DS GS<br>V V<br>**----- End of picture text -----**<br> R07DS1004EJ0200 Rev.2.00 May 24, 2018 Page 5 of 5 **NP75N04YUK** **Preliminary** ## **Package Drawing** (Unit: mm) ## **8-pin HSON (Mass: 0.128 g TYP.)** **==> picture [69 x 31] intentionally omitted <==** **----- Start of picture text -----**<br> 1, 2, 3 : Source<br>4 : Gate<br>5, 6, 7, 8 : Drain<br>**----- End of picture text -----**<br> ## **Equivalent Circuit** **==> picture [482 x 128] intentionally omitted <==** **----- Start of picture text -----**<br> Drain<br>Body<br>Gate Diode<br>Source<br>Remark: Strong electric field, when exposed to this device, can cause destruction of the gate oxide and<br>ultimately degrade the device operation. Steps must be taken to stop generation of static electricity<br>as much as possible, and quickly dissipate it once, when it has occurred.<br>**----- End of picture text -----**<br> R07DS1004EJ0200 Rev.2.00 May 24, 2018 Page 6 of 6 ## **Revision History** ## **NP75N04YUK Data Sheet** |**Rev.**|**Date**||**Description**| |---|---|---|---| |||**Page **|**Summary**| |1.00|Feb 08, 2013|—|First Edition Issued| |2.00|May 24 ,2018|1<br>2|Note 4 was added<br>Note 2 was added| All trademarks and registered trademarks are the property of their respective owners. C - 1 ## Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. 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