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NP16N06YLL-E1-AY
Power MOSFET, N Channel, 60 V, 16 A, 0.035 ohm, HSON, Surface Mount
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- Manufacturer: RENESAS
- Product type:
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 8Pins
- Channel Type: N Channel
- Product Range: NP16N06YLL Series
- Qualification: AEC-Q101
- Power Dissipation: 27.3W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: HSON
- Drain Source Voltage Vds: 60V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 16A
- Drain Source On State Resistance: 0.035ohm
- Gate Source Threshold Voltage Max: 2V
| Delivery and price | |
|---|---|
| Units per pack | 2500 |
| Price | 0.471 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
Data Sheet ## **NP16N06YLL** 60 V – 16 A – N-channel Power MOS FET A lication: Automotive pp R07DS1124EJ0100 Rev.1.00 Oct 30, 2013 ## **Description** These products are N-channel MOS Field Effect Transistors designed for high current switching applications. ## **Features** - Low on-state resistance - ⎯ RDS(on) = 35 mΩ MAX. (VGS = 10 V, ID = 8 A) - Low Ciss: Ciss = 400 pF TYP. (VDS = 25 V, VGS = 0 V) - Logic level drive type - Gate to Source ESD protection diode built in - Designed for automotive application and AEC-Q101 qualified ## **Outline** **==> picture [103 x 94] intentionally omitted <==** **----- Start of picture text -----**<br> Drain<br>Body<br>Gate Diode<br>Gate<br>Protection<br>Source<br>Diode<br>**----- End of picture text -----**<br> **==> picture [76 x 139] intentionally omitted <==** **----- Start of picture text -----**<br> 8-pin HSON<br>5<br>6<br>7<br>8<br>[4]<br>[3]<br>1 [2]<br>1, 2, 3 : Source<br>4 : Gate<br>5, 6, 7, 8: Drain<br>**----- End of picture text -----**<br> Remark: Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. ## **Ordering Information** **Part No. Lead Plating Packing Package** NP16N06YLL-E1-AY[*][1] Pure Sn (Tin) Tape 2500 p/reel Taping (E1 type) 8-pin HSON ~~ee~~ NP16N06YLL-E2-AY[*][1] Taping (E2 type) Note: * 1. Pb-free (This product does not contain Pb in the external electrode) ~~a~~ R07DS1124EJ0100 Rev.1.00 Oct 30, 2013 Page 1 of 7 NP16N06YLL ## **Absolute Maximum Ratings** (TA = 25°C) |**Absolute Maximum Ratings**|(TA= 25°C)||| |---|---|---|---| |**Item**|**Symbol**|**Ratings **|**Unit**| |Drain to Source Voltage(VGS= 0 V)|VDSS|60|V| |Gate to Source Voltage(VDS= 0 V)|VGSS|±20|V| |Drain Current(DC) (TC= 25°C)|ID(DC)|±16|A| |Drain Current(pulse) ∗1|ID(pulse)|±32|A| |Total Power Dissipation(TC= 25°C)|PT1|27.3|W| |Total Power Dissipation(TA= 25°C) ∗2|PT2|1.25|W| |Channel Temperature|Tch|175|°C| |Storage Temperature|Tstg|−55 to+175|°C| |Single Avalanche Current∗3|IAS|10|A| |Single Avalanche Energy ∗3|EAS|10|mJ| ## **Thermal Resistance** Channel to Case Thermal Resistance Rth(ch-C) 5.49 ° C/W Channel to Ambient Thermal Resistance[∗][2] Rth(ch-A) 120.0 ° C/W Notes: * 1. TC = 25°C, PW ≤ 10 μ s, Duty Cycle ≤ 1% - 2. Mounted on glass epoxy substrate of 40 mm × 40 mm × 1.6 mmt with 4% copper area (35 μ m) - 3. Tch(start) = 25 ° C, VDD = 30 V, RG = 25 Ω , L = 100 μ H, VGS = 20 V → 0 V R07DS1124EJ0100 Rev.1.00 Oct 30, 2013 Page 2 of 7 NP16N06YLL ## **Electrical Characteristics** (TA = 25°C) |**Item**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Test Conditions**| |---|---|---|---|---|---|---| |Zero Gate Voltage Drain Current|IDSS|||1|μA|VDS= 60 V, VGS= 0 V| |Gate Leakage Current|IGSS|||±10|μA|VGS= ±20 V, VDS= 0 V| |Gate Cut-off Voltage|VGS(off)|1.0|1.5|2.0|V|VDS= 10 V, ID= 1 mA| |Forward Transfer Admittance∗1|| yfs||5|12||S|VDS= 5.0 V, ID= 8 A| |Drain to Source On-state<br>Resistance∗1|RDS(on)1||31|35|mΩ|VGS= 10 V, ID= 8 A| ||RDS(on)2||42|55|mΩ|VGS= 4.5 V, ID= 8 A| |Input Capacitance|Ciss||400|600|pF|VDS= 25 V,<br>VGS= 0 V,<br>f = 1 MHz| |Output Capacitance|Coss||84|130|pF|| |Reverse Transfer Capacitance|Crss||54|100|pF|| |Turn-on DelayTime|td(on)||8|16|ns|VDD= 30 V, ID= 8 A,<br>VGS= 10 V,<br>RG= 0Ω| |Rise Time|tr||8|20|ns|| |Turn-off DelayTime|td(off)||25|50|ns|| |Fall Time|tf||5|12.5|ns|| |Total Gate Charge|QG||12|18|nC|VDD= 48 V,<br>VGS= 10 V,<br>ID= 16 A| |Gate to Source Charge|QGS||1.4||nC|| |Gate to Drain Charge|QGD||4||nC|| |BodyDiode Forward Voltage∗1|VF(S-D)||0.95|1.24|V|IF= 16 A, VGS= 0 V| |Reverse RecoveryTime|trr||27||ns|IF= 16 A, VGS= 0 V,<br>di/dt = 100 A/μs| |Reverse RecoveryCharge|Qrr||28||nC|| Note: * 1. Pulsed test ## **TEST CIRCUIT 1 AVALANCHE CAPABILITY** ## **TEST CIRCUIT 2 SWITCHING TIME** **==> picture [471 x 137] intentionally omitted <==** **----- Start of picture text -----**<br> D.U.T. D.U.T.<br>PG. RG = 25 Ω L PG. RG RL Wave FormVGS VGS0 10% VGS 90%<br>VGS = 20 → 0 V 50 Ω VDD VDD VDS<br>90% 90%<br>IAS BVDSS V0 GS VDS V0DS 1 0% 10%<br>Wave Form<br>VDD ID VDS τ td(on) tr td(off) tf<br>τ = 1 μs ton toff<br>Duty Cycle ≤ 1%<br>Starting Tch<br>**----- End of picture text -----**<br> ## **TEST CIRCUIT 3 GATE CHARGE** **==> picture [123 x 57] intentionally omitted <==** **----- Start of picture text -----**<br> D.U.T.<br>IG = 2 mA RL<br>PG.<br>50 Ω VDD<br>**----- End of picture text -----**<br> R07DS1124EJ0100 Rev.1.00 Oct 30, 2013 Page 3 of 7 NP16N06YLL ## **Typical Characteristics** (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA **==> picture [200 x 172] intentionally omitted <==** **----- Start of picture text -----**<br> 120<br>100<br>80<br>60<br>40<br>20<br>0<br>0 25 50 75 100 125 150 175<br>TC - Case Temperature - °C<br>dT - Percentage of Rated Power - %<br>**----- End of picture text -----**<br> TOTAL POWER DISSIPATION vs. CASE TEMPERATURE **==> picture [200 x 172] intentionally omitted <==** **----- Start of picture text -----**<br> 30<br>25<br>20<br>15<br>10<br>5<br>0<br>0 25 50 75 100 125 150 175<br>TC - Case Temperature - °C<br> - Total Power Dissipation - W<br>T<br>P<br>**----- End of picture text -----**<br> ## FORWARD BIAS SAFE OPERATING AREA **==> picture [387 x 419] intentionally omitted <==** **----- Start of picture text -----**<br> 100<br>I D(Pulse) = 32 A<br>R DS(ON) Limited<br>(VGS=10 V)<br>10 ID(DC) = 16 A<br>Power Dissipation Limited<br>1<br>Secondary Breakdown Limited<br>T C = 25°C<br>Single Pulse<br>0.1<br>0.1 1 10 100<br>VDS - Drain to Source Voltage - V<br>TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH<br>1000<br>R = 120 ° C/W<br>th(ch-A)<br>100<br>10 Rth(ch-C) = 5.5°C/W<br>1<br>0.1<br>Single pulse<br>Mounted on glass epoxy substrate of 40 mm × 40 mm × 1.6 mmt with 4% copper area (35 μm)<br>0.01<br>100 μ 1 m 10 m 100 m 1 10 100 1000<br>PW - Pulse Width - s<br>DC<br>PW = 10 ms<br>PW = 100<br>μs<br>PW = 1 ms<br> - Drain Current - A<br>ID<br> - Transient Thermal Resistance - °C/W<br>th(t)<br>R<br>**----- End of picture text -----**<br> R07DS1124EJ0100 Rev.1.00 Oct 30, 2013 Page 4 of 7 NP16N06YLL DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE ## FORWARD TRANSFER CHARACTERISTICS **==> picture [436 x 603] intentionally omitted <==** **----- Start of picture text -----**<br> 40 100<br>35<br>30 V GS = 10 V VGS = 5.0 V 10 TA = –55°C<br>–40°C<br>25 25°C<br>1<br>75°C<br>20 V GS = 4.5 V 100°C<br>125°C<br>15 0.1 150°C<br>175°C<br>10<br>0.01<br>5 VDS = 10 V<br>Pulsed Pulsed<br>0 0.001<br>0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 1 2 3 4<br>VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V<br>GATE CUT-OFF VOLTAGE vs. FORWARD TRANSFER ADMITTANCE vs.<br>CHANNEL TEMPERATURE DRAIN CURRENT<br>2.0 100<br>T A = –55°C<br>–40°C<br>1.5 25°C<br>75 ° C<br>100°C<br>125°C<br>1.0 10 150°C°CC<br>175°C°CC<br>0.5<br>V DS = 10 V VDS = 5 VDS = 5 V = 5 V<br>ID = 1 mA Pulsed<br>0 1<br>–100 –50 0 50 100 150 200 0.1 1 10<br>Tch - Channel Temperature - °C ID - Drain Current - AD - Drain Current - A - Drain Current - A<br>DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN TO SOURCE ON-STATE RESISTANCE vs.<br>DRAIN CURRENT GATE TO SOURCE VOLTAGE<br>100 100<br>80 VGS = 10 V 80 ID = 16 AD = 16 A = 16 A<br>5.0 V 8 A<br>4.5 V 3.2 A<br>60 60<br>40 40<br>20 20<br>Pulsed Pulsed<br>0 0<br>0.1 1 10 100 0 5 10 15<br>ID - Drain Current - A VGS - Gate to Source Voltage - VGS - Gate to Source Voltage - V - Gate to Source Voltage - V<br> - Drain Current - A - Drain Current - A<br>ID ID<br> - Gate Cut-off Voltage - V<br>GS(off)<br>V | - Forward Transfer Admittance - S<br>fs<br>|y<br>Ω Ω<br> - Drain to Source On-State Resistance - m - Drain to Source On-State Resistance - m<br>DS(on) DS(on)<br>R R<br>**----- End of picture text -----**<br> **==> picture [206 x 387] intentionally omitted <==** **----- Start of picture text -----**<br> 100<br>T A = –55°C<br>–40°C<br>25°C<br>75 ° C<br>100°C<br>125°C<br>10 150°C°CC<br>175°C°CC<br>VDS = 5 VDS = 5 V = 5 V<br>Pulsed<br>1<br>0.1 1 10 100<br>ID - Drain Current - AD - Drain Current - A - Drain Current - A<br>DRAIN TO SOURCE ON-STATE RESISTANCE vs.<br>GATE TO SOURCE VOLTAGE<br>100<br>80<br>ID = 16 AD = 16 A = 16 A<br>8 A<br>3.2 A<br>60<br>40<br>20<br>Pulsed<br>0<br>0 5 10 15 20<br>VGS - Gate to Source Voltage - VGS - Gate to Source Voltage - V - Gate to Source Voltage - V<br>| - Forward Transfer Admittance - S<br>fs<br>|y<br>Ω<br> - Drain to Source On-State Resistance - m<br>DS(on)<br>R<br>**----- End of picture text -----**<br> R07DS1124EJ0100 Rev.1.00 Oct 30, 2013 Page 5 of 7 NP16N06YLL DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE **==> picture [200 x 193] intentionally omitted <==** **----- Start of picture text -----**<br> CHANNEL TEMPERATURE<br>100<br>80 VGS = 10 V<br>5.0 V<br>4.5 V<br>60<br>40<br>20<br>I D = 8 A<br>Pulsed<br>0<br>–100 –50 0 50 100 150 200<br>Tch - Channel Temperature - °C<br>Ω<br> - Drain to Source On-State Resistance - m<br>DS(on)<br>R<br>**----- End of picture text -----**<br> SWITCHING CHARACTERISTICS **==> picture [200 x 388] intentionally omitted <==** **----- Start of picture text -----**<br> 1000<br>100<br>td(off)<br>td(on)<br>10<br>tr tf R V V DD GSG = 0 = 30 V = 10 VΩ<br>1<br>0.1 1 10 100<br>ID - Drain Current - A<br>SOURCE TO DRAIN DIODE FORWARD VOLTAGE<br>100<br>V GS = 10 V<br>10<br>VGS = 0 V<br>1<br>Pulsed<br>0.1<br>0 0.2 0.4 0.6 0.8 1.0 1.2<br>VF(S-D) - Source to Drain Voltage - V<br> - Switching Time - ns, tf<br>d(off)<br>, t, tr<br>td(on)<br> - Diode Forward Current - A<br>IF<br>**----- End of picture text -----**<br> SOURCE TO DRAIN DIODE FORWARD VOLTAGE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE **==> picture [225 x 387] intentionally omitted <==** **----- Start of picture text -----**<br> 1000<br>Ciss<br>100<br>C oss<br>C rss<br>VGS = 0 V<br>f = 1 MHz<br>10<br>0.01 0.1 1 10 100<br>VDS - Drain to Source Voltage - V<br>DYNAMIC INPUT/OUTPUT CHARACTERISTICS<br>50 10<br>45 VDD = 48 V 9<br>30 V<br>40 12 V 8<br>35 7<br>30 6<br>25 V GS 5<br>20 4<br>15 3<br>10 2<br>VDS<br>5 ID = 16 A 1<br>0 0<br>0 2 4 6 8 10 12 14<br>QG- Gate Charge - nC<br> - Capacitance -pF<br>rss<br>, C<br>oss<br>, C<br>iss<br>C<br> - Drain to Source Voltage - V - Gate to Source Voltage - V<br>DS GS<br>V V<br>**----- End of picture text -----**<br> REVERSE RECOVERY TIME vs. DRAIN CURRENT **==> picture [199 x 172] intentionally omitted <==** **----- Start of picture text -----**<br> 100<br>10<br>di/dt = 100 A/μs<br>VGS = 0 V<br>1<br>0.1 1 10 100<br>IF - Drain Current - A<br> - Reverse Recovery Time - ns<br>trr<br>**----- End of picture text -----**<br> R07DS1124EJ0100 Rev.1.00 Oct 30, 2013 Page 6 of 7 NP16N06YLL ## **Package Drawings** (Unit: mm) ## **8-pin HSON (Mass: 0.13 g TYP.)** Renesas package code: PLSN0008KA-A **==> picture [197 x 268] intentionally omitted <==** **----- Start of picture text -----**<br> 1<br>8<br>2 7<br>3 6<br>4 5<br>6.0 ±0.2 0.10 S<br>5.4 ±0.2<br>0.73<br>0.4<br>1, 2, 3 : Source<br>4 : Gate<br>5, 6, 7, 8: Drain<br>3.18 ±0.2<br>0.6 ±0.15 0.8 ±0.15<br>1.27<br>0.2± 0.2±<br>5.0 5.15<br>+0.1 0.05–<br>0.42<br>0.10 M<br>+0.05 0–<br>0 0.05<br>±<br>1.45 MAX.<br>0.42<br>0.2<br>±<br>3.8<br>**----- End of picture text -----**<br> R07DS1124EJ0100 Rev.1.00 Oct 30, 2013 Page 7 of 7 |**Revision History**|**Revision History**|**Revision History**||**NP16N06YLL Data Sheet**| |---|---|---|---|---| |||||| |**Rev.**|**Date**|||**Description**| |||**Page **||**Summary**| |1.00|Oct 30, 2013|—||First Edition Issued| |||||| All trademarks and registered trademarks are the property of their respective owners. C - 1 **==> picture [455 x 387] intentionally omitted <==** **----- Start of picture text -----**<br> Notice<br>1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for<br>the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the<br>use of these circuits, software, or information.<br>2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics<br>assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.<br>3. 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