NFAP1060L3TT

Intelligent Power Module (IPM), IGBT, 600 V, 10 A, 2 kV, SIP 29, SIP

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Manufacturer: ONSEMI
Product type: Intelligent Power Modules
IPM Power Device:IGBT; Voltage Rating (Vces / Vdss):600V; Current Rating (Ic / Id):10A; Isolation Voltage:2kV; IPM Case Style:SIP 29; IPM Series:SIP; Product Range:-; SVHC:No SVHC (15
SVHC: No SVHC (25-Jun-2025)
IPM Series: SIP
Product Range: -
IPM Case Style: SIP 29
IPM Power Device: IGBT
Isolation Voltage: 2kV
Current Rating (Ic / Id): 10A
Voltage Rating (Vces / Vdss): 600V

Delivery and price
Units per pack	250
Price	10.23 €
Current stock	10+
Lead time	30 days

Datasheet

## NFAP1060L3TT 

## Intelligent Power Module (IPM), 600 V, 10 A 

The NFAP1060L3TT is a fully−integrated inverter power stage consisting of a high−voltage driver, six IGBT’s and a thermistor, suitable for driving permanent magnet synchronous (PMSM) motors, brushless−DC (BLDC) motors and AC asynchronous motors. The IGBT’s are configured in a 3−phase bridge with separate emitter connections for the lower legs for maximum flexibility in the choice of control algorithm. The power stage has a full range of protection functions including cross−conduction protection, external shutdown and under−voltage lockout functions. An internal comparator and reference connected to the over−current protection circuit allows the designer to set the over−current protection level. 

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## **Features** 

- Three−phase 10A/600V IGBT Module with Integrated Drivers 

- Compact 44 mm x 20.9 mm Single In−line Package 

- Built−in Under Voltage Protection 

- Cross−conduction Protection 

**SIP29 CASE 127FB** 

- ITRIP Input to Shut Down All IGBTs 

- Integrated Bootstrap Diodes and Resistors 

- Thermistor for Substrate Temperature Measurement 

- UL1557 Certification (File number: E339285) 

## **Typical Applications** 

- Industrial Drives 

- Industrial Pumps 

- Industrial Fans 

- Industrial Automation 

**==> picture [274 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
HIN(U) HS1<br>LIN(U) LS1 HS1 HS2 HS3<br>HIN(V) Three channel HS2<br>half−bridge<br>LIN(V) driver LS2<br>with<br>HIN(W) protection HS3<br>circuits<br>LIN(W) LS3 LS1 LS2 LS3<br>ir)L VB(U) VB(V) e VB(W) VDD VSS TH P VS(U), U VS(V), V | VS(W), W<br>FLTEN ITRIP NU NV NW<br>**----- End of picture text -----**<br>


**MARKING DIAGRAM** NFAP1060L3TT ZZZATYWW NFAP1060L3TT ~~orm~~ = Specific Device Code ZZZ = Assembly Lot Code A = Assembly Location T = Test Location Y = Year WW = Work Week Device marking is on package top side 

## **ORDERING INFORMATION** 

|**Device**|**Package**|**Shipping**|
|---|---|---|
|NFAP1060L3TT|SIP29<br>(Pb−Free)|120 / Box|



**Figure 1. Functional Diagram** 

Publication Order Number: **NFAP1060L3TT/D** 

**1** 

© Semiconductor Components Industries, LLC, 2019 **May, 2019 − Rev. 0** 

**NFAP1060L3TT** 

**==> picture [477 x 366] intentionally omitted <==**

**----- Start of picture text -----**<br>
NFAP1060L3TT<br>VPN<br>P:13<br>+ RC filtering for<br>C1 CS HINx and LINx<br>not shown.<br>HV Ground From Op−amp Recommended<br>RSU circuit in noisy<br>environments.<br>NU:17 ITRIP:16<br>From HV<br>Power<br>RSV<br>Source NV:19 HIN(U):20<br>HIN(V):22<br>RSW<br>NW:21 HIN(W):23<br>To Op−amp LIN(U):24<br>circuit LIN(V):25<br>LIN(W):26<br>VB(U):9<br>+<br>Pull−up<br>VS(U), U:10 RP RTH<br>Controller<br>VB(V):5<br>+<br>FLTEN:18<br>Motor VS(V), V:6 TH:27<br>VDD=15V<br>VB(W):1 VDD:28 from<br>+ CD4 + external<br>regulator<br>VS(W), W:2 VSS:29<br>LV Ground<br>Star connection to HV Ground<br>**----- End of picture text -----**<br>


**Figure 2. Application Schematic** 

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**2** 

**NFAP1060L3TT** 

**==> picture [477 x 458] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bootstrap VB(U) (9)<br>Bootstrap VB(V) (5)<br>Bootstrap VB(W) (1)<br>VDD (28) P (13)<br>VSS (29)<br>TH (27) VS(W), W (2)<br>VS(V), V (6)<br>VS(U), U (10)<br>NU (17)<br>NV (19)<br>NW (21)<br>Level Level Level<br>Shifter Shifter Shifter<br>HIN(U) (20)<br>HIN(V) (22)<br>HIN(W) (23)<br>Logic Logic Logic<br>LIN(U) (24)<br>LIN(V) (25)<br>LIN(W) (26)<br>VDD<br>VDD undervoltage<br>shutdown FLTEN (18)<br>ITRIP (16) Over current<br>Internal Voltage protection<br>reference<br>**----- End of picture text -----**<br>


**Figure 3. Simplified Block Diagram** 

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**3** 

**NFAP1060L3TT** 

## **Table 1. PIN FUNCTION DESCRIPTION** 

|**Pin**|**Name**|**Description**|**Description**|**Description**||
|---|---|---|---|---|---|
|1|VB(W)|High−Side Bias Voltage for W phase IGBT Driving||||
|2|VS(W), W|High−Side Bias Voltage GND for W phase IGBT Driving, Output for W Phase||||
|5|VB(V)|High−Side Bias Voltage for V phase IGBT Driving||||
|6|VS(V), V|High−Side Bias Voltage GND for V phase IGBT Driving, Output for V Phase||||
|9|VB(U)|High−Side Bias Voltage for U phase IGBT Driving||||
|10|VS(U), U|High−Side Bias Voltage GND for U phase IGBT Driving, Output for U Phase||||
|13|P|Positive DC−Link Input||||
|16|ITRIP|Input for Over Current Protection||||
|17|NU|Negative DC−Link Input for U Phase||||
|18|FLTEN|Fault Output, Enable Input||||
|19|NV|Negative DC−Link Input for V Phase||||
|20|HIN(U)|Signal Input for High−Side U Phase||||
|21|NW|Negative DC−Link Input for W Phase||||
|22|HIN(V)|Signal Input for High−Side V Phase||||
|23|HIN(W)|Signal Input for High−Side W Phase||||
|24|LIN(U)|Signal Input for Low−Side U Phase||||
|25|LIN(V)|Signal Input for Low−Side V Phase||||
|26|LIN(W)|Signal Input for Low−Side W Phase||||
|27|TH|Series Resister for Thermistor (Temperature Detection)||||
|28|VDD|Low−Side Bias Voltage for IC and IGBTs Driving||||
|29|VSS|Low−Side Common Supply Ground||||
|NOTE:<br>Pins 3, 4, 7, 8, 11, 12, 14 and 15 are not present<br>**Table 2.ABSOLUTE MAXIMUM RATINGS**at Tc = 25°C (Note 1)||||||
|**Parameter**||**Symbol**|**Conditions**|**Rating**|**Unit**|
|Supply Voltage||VPN|P−NU,NV,NW,  VPN (surge) < 500 V (Note 2)|450|V|
|Collector − Emitter Voltage||Vces|P-U,V,W; U-NU; V-NV; W-NW|600|V|
|Each IGBT Collector Current||±Ic|P,U,V,W,NU,NV,NW terminal current|±10|A|
|Each IGBT Collector Current (Peak)||±Icp|Tc = 25°C, Under 1ms Pulse Width|20|A|
|Corrector Dissipation||Pc|Tc = 25°C, Per One Chip|19|W|
|High−Side Control Bias voltage||VBS|VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W) (Note 3)|−0.3 to +20.0|V|
|Control Supply Voltage||VDD|VDD−VSS|−0.3 to +20.0|V|
|Input Signal Voltage||VIN|HIN(U), HIN(V), HIN(W), LIN(U), LIN(V), LIN(W) − VSS|−0.3 to VDD|V|
|FLTEN Terminal Voltage||VFLTEN|FLTEN−VSS|−0.3 to VDD|V|
|Current Sensing Input Voltage||VITRIP|ITRIP−VSS|−0.3 to +7.0|V|
|Operating Junction Temperature||Tj||150|°C|
|Storage Temperature||Tstg||−40 to +125|°C|
|Module Case Operation Temperature||Tc||−40 to +125|°C|
|Tightening Torque||MT|Case mounting screws|0.9|Nm|
|Isolation Voltage||Viso|50 Hz sine wave AC 1 minute (Note 4)|2000|Vrms|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 

2. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal. 

3. VBS = VB(U)−VS(U), VB(V)−VS(V), VB(W)−VS(W) 

4. Test conditions : AC2500V, 1 s 

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**4** 

**NFAP1060L3TT** 

## **Table 3. RECOMMENDED OPERATING RANGES** 

|**Parameter**|**Symbol**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Supply voltage|VPN|P−NU,NV,NW|0|280|450|V|
|High−Side Control Bias voltage|VBS|VB(U)−VS(U), VB(V)−VS(V),<br>VB(W)−VS(W)|13.0|15|17.5|V|
|Control Supply Voltage|VDD|VDD−VSS|14.0|15|16.5|V|
|ON−state Input Voltage|VIN(ON)|HIN(U), HIN(V), HIN(W), LIN(U),<br>LIN(V), LIN(W) − VSS|3.0|−|5.0|V|
|OFF−state Input Voltage|VIN(OFF)||0|−|0.3|V|
|PWM Frequency|fPWM||1|−|20|kHz|
|Dead Time|DT|Turn−off to Turn−on (external)|0.5|−|−|�s|
|Allowable Input Pulse Width|PWIN|ON and OFF|1|−|−|�s|
|Tightening Torque||‘M3’ type screw|0.6|−|0.9|Nm|



Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 

**Table 4. ELECTRICAL CHARACTERISTICS** at Tc = 25 ° C, VBIAS (VBS, VDD) = 15 V unless otherwise noted. 

|**Table 4. ELECTRICAL CHARACTERI**|**STICS**at Tc = 25°C, VBIAS(VBS, VDD)|= 15 V unless|otherwise|noted.|||
|---|---|---|---|---|---|---|
|**Parameter**|**Test Conditions**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**POWER OUTPUT SECTION**|||||||
|Collector−Emitter Leakage Current|Vce=600V|Ices|−|−|1|mA|
|Bootstrap Diode Reverse Current|VR(DB)=600V|IR(DB)|−|−|1|mA|
|Collector−Emitter Saturation Voltage|VDD=VBS=15V, IN=5V, Ic=10A,<br>Tj=25°C|VCE(sat)|−|2.1|2.7|V|
||VDD=VBS=15V, IN=5V, Ic=5A,<br>Tj=100°C||−|1.8|−|V|
|FWDi Forward Voltage|IN=0V, Ic=−10A, Tj=25°C|VF|−|2.2|2.8|V|
||IN=0V, Ic=−5A, Tj=100°C||−|1.7|−|V|
|Junction to Case Thermal Resistance|Inverter IGBT Part (per 1/6 Module)|Rth(j−c)Q|−|−|6.3|°C/W|
||Inverter FRD Part (per 1/6 Module)|Rth(j−c)F|−|−|11.6|°C/W|
|**DRIVER SECTION**|||||||
|Quiescent VBS Supply Current|VBS=15V, HIN=0V, per driver|IQBS|−|0.07|0.4|mA|
|Quiescent VDD Supply Current|VDD=15V, HIN=0V, VDD−VSS|IQDDL|−|0.85|3.0|mA|
|ON Threshold voltage|HIN(U), HIN(V), HIN(W), LIN(U),<br>LIN(V), LIN(W) − VSS|VIN(ON)|−|−|2.5|V|
|OFF Threshold voltage||VIN(OFF)|0.8|−|−|V|
|Logic 1 Input Current|VIN = +3.3 V|IIN+|−|660|−|�A|
|Logic 0 Input Current|VIN = 0 V|IIN−|−|−|2|�A|
|FLTEN Terminal Sink Current|FAULT  : ON / VFLTEN = 0.1 V|IoSD|−|2|−|mA|
|Fault−Output Pulse Width|FLTEN−VSS|tFOD|20|−|−|�s|
|Enable Threshold|FLTEN−VSS|VEN+|−|−|2.5|V|
|||VEN−|0.8|−|−|V|
|Short Circuit Trip Level|ITRIP−VSS|VSC(ref)|0.44|0.49|0.54|V|
|High−Side Control Bias Voltage Under−<br>Voltage Protection|Reset Level|UVBSR|10.3|11.1|11.9|V|
||Detection Level|UVBSD|10.1|10.9|11.7|V|
|Supply Voltage Under−Voltage Protection|Reset Level|UVDDR|10.3|11.1|11.7|V|
||Detection Level|UVDDD|10.1|10.9|11.5|V|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**5** 

**NFAP1060L3TT** 

## **Table 5. ELECTRICAL CHARACTERISTICS** 

at Tc = 25 ° C, VBIAS (VBS, VDD) = 15 V, VCC = 300 V, L = 3.0 mH unless otherwise noted. 

|Switching Time<br>~~PO~~<br>~~PO~~|IC = 10 A, Tj = 25°C|tON<br>~~re~~<br>~~re~~|−<br>~~ee~~<br>~~ee~~|0.5<br>~~ee~~<br>~~ee~~|1.0<br>~~eee~~<br>~~ee~~|s<br>~~eee~~|
|---|---|---|---|---|---|---|
|||tOFF<br>~~re ~~<br>~~re~~<br>~~re~~|−<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|0.5<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1.0<br>~~eee~~<br>~~ee~~<br>~~ee~~|s<br>~~eee~~<br>~~ee~~|
|Turn−on Switching Loss<br>~~PO~~<br>~~PO~~<br>~~PO~~|IC = 5 A, Tj = 25°C|EON<br>~~re~~<br>~~re~~<br>~~re~~|−<br>~~ee~~<br>~~ee~~<br>~~ee~~|114<br>~~ee~~<br>~~ee~~<br>~~ee~~|−<br>~~ee~~<br>~~ee~~<br>~~eee~~|J<br>~~ee~~<br>~~eee~~|
|Turn−off Switching Loss<br>~~PO~~<br>~~PO~~<br>~~PO~~<br>~~Po~~||EOFF<br>~~re ~~<br>~~re~~<br>~~re~~<br>~~re~~|−<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|65<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|−<br> ~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|J<br>~~ee~~<br>~~eee~~|
|Total Switching Loss<br>~~PO~~<br>~~PO~~<br>~~Po~~<br>~~PO~~||ETOT<br>~~re ~~<br>~~re~~<br>~~re~~<br>~~rr~~|−<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|179<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|−<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~ee~~|J<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|Turn−on Switching Loss<br>~~PO~~<br>~~Po~~<br>~~PO~~<br>~~PO~~|IC = 5 A, Tj = 100°C|EON<br>~~re ~~<br>~~re~~<br>~~rr~~<br>~~re~~|−<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|136<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|−<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|J<br>~~eee~~<br>~~ee~~<br>~~ee~~|
|Turn−off Switching Loss<br>~~Po~~<br>~~PO~~<br>~~PO~~<br>~~Sa~~||EOFF<br>~~re ~~<br>~~rr~~<br>~~re~~<br>~~a~~|−<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|75<br> ~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~**e**e~~|−<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|J<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|Total Switching Loss<br>~~PO~~<br>~~PO~~<br>~~Sa~~||ETOT<br>~~rr ~~<br>~~re~~<br>~~a~~|−<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|211<br> ~~ee~~<br>~~ee~~<br>~~**e**e~~|−<br>~~ee~~<br>~~ee~~<br>~~eee~~|J<br>~~ee~~<br>~~ee~~<br>~~eee~~|
|Diode Reverse Recovery Energy<br>~~PO~~<br>~~Sa~~|IC = 5 A, Tj = 100°C<br>~~e~~|EREC<br>~~re ~~<br>~~a~~<br>~~e~~|−<br> ~~ee ~~<br>~~ee~~<br>~~e~~|27<br> ~~ee~~<br>~~**e**e~~<br>~~e~~|−<br>~~ee~~<br>~~eee~~|J<br>~~ee~~<br>~~eee~~|
|Diode Reverse Recovery Time<br>~~Sa~~||tRR<br>~~a~~<br>~~e~~|−<br>~~ee~~<br>~~e~~|174<br>~~**e**e~~<br>~~e~~|−<br>~~eee~~|ns<br>~~eee~~|
|Reverse Bias Safe Operating Area<br>~~Sa~~|IC = 20 A, VCE= 450 V|RBSOA<br>~~a~~|Full Square<br>~~ee ~~~~**e**eeee~~|||~~eee~~|
|Short Circuit Safe Operating Area<br>~~ee~~|VCE= 400 V, Tj = 100°C<br>~~ee~~|SCSOA<br>~~ee~~|5<br>~~ee~~|−<br>~~ee~~|−<br>~~ee~~|s<br>~~ee~~|



## **TYPICAL CHARACTERISTICS INV SECTION** 

**Figure 4. VCE vs. IC for Different Temperatures (VDD = 15 V)** 

**Figure 5. VF vs. IF for Different Temperatures** 

**Figure 6. EON vs. IC for Different Temperatures** 

**Figure 7. EOFF vs. IC for Different Temperatures** 

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**6** 

**NFAP1060L3TT** 

## **TYPICAL CHARACTERISTICS INV SECTION** 

**Figure 8. Thermal Impedance Plot** 

**Figure 9. Turn−on Waveform Tj = 100** ° **C, VCC = 300 V** 

**Figure 10. Turn−off Waveform Tj = 100** ° **C, VCC = 300 V** 

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**7** 

**NFAP1060L3TT** 

## **APPLICATIONS INFORMATION** 

**==> picture [477 x 349] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBS undervoltage protection reset signal<br>HIN<br>LIN<br>VDD undervoltage protection reset voltage (Note 6)<br>VDD VBS undervoltage protection reset voltage (Note 7)<br>VB(U), VB(V), VB(W) Voltage  � 0.54V<br>(Note 8)<br>Voltage < 0.44V<br>ITRIP<br>FLTEN driven<br>output<br>FLTEN driven<br>input<br>Cross−conduction prevention period (Note 5)<br>Upper IGBT<br>Gate Drive<br>Lower IGBT<br>Gate Drive<br>Automatic reset after protection (Fault−Output PulseWidth)<br>**----- End of picture text -----**<br>


## **Figure 11. Input / Output Timing Chart** 

5. This section of the timing diagram shows the effect of cross−conduction prevention. 

6. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go low, switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume. 

7. This section shows that when the bootstrap voltage on VB(U) (VB(V), VB(W)) drops, the corresponding high side output U (V, W) is switched off. When the voltage on VB(U) (VB(V), VB(W)) rises sufficiently, normal operation will resume. 

8. This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes later after the over−current condition is removed. 

## **Table 6. INPUT / OUTPUT LOGIC TABLE** 

||**INPUT**|||**OUTPUT**|||
|---|---|---|---|---|---|---|
|**HIN**|**LIN**|**ITRIP**|**High side IGBT**|**Low side IGBT**|**U,V,W**|**FAULT**|
|H|L|L|ON|OFF|P|OFF|
|L|H|L|OFF|ON|NU, NV, NW|OFF|
|L|L|L|OFF|OFF|High Impedance|OFF|
|H|H|L|OFF|OFF|High Impedance|OFF|
|X|X|H|OFF|OFF|High Impedance|ON|



## **Table 7. THERMISTOR CHARACTERISTICS** 

|**Parameter**|**Symbol**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Resistance|R25<br>R125|Tth=25℃|45.59|47|48.41|k�|
|||Tth=125℃|1.34|1.45|1.59|k�|
|B−Constant (25 to 50℃)|B||3953|4021|4033|K|
|Temperature Range|||−40||+125|°C|



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**NFAP1060L3TT** 

**Figure 12. Thermistor Resistance vs. Thermistor Temperature** 

**Figure 13. Thermistor Voltage vs. Thermistor Temperature Conditions: RTH = 4.7 k** Q **pull−up voltage 5.0 V (see Figure 12)** 

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**NFAP1060L3TT** 

## **FLTEN Pin** 

The FLTEN pin is connected to an open−drain FAULT output and an ENABLE input, it is required a pull−up resistor. If the pull−up voltage is 5 V, use a pull−up resistor with a value of 6.8 k Q or higher. If the pull−up voltage is 15 V, use a pull−up resistor with a value of 20 k Q or higher. The pulled up voltage in normal operation for the FLTEN pin should be above 2.5 V, noting that it is connected to an internal ENABLE input. The FAULT output is triggered if there is a VDD under−voltage or an overcurrent condition. 

Driving the FLTEN terminal pin is used to enable or shut down the built−in driver. If the voltage on the FLTEN pin rises above the positive going ENABLE threshold, the output drivers are enabled. If the voltage on the FLTEN pin falls below the negative going ENABLE threshold, the drivers are disabled. 

## **Under−voltage Protection** 

If VDD goes below the VDD supply under−voltage lockout falling threshold, the FAULT output is switched on. The FAULT output stays on until VDD rises above the VDD supply under−voltage lockout rising threshold. After VDD has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the LIN input before enabling the driver for the HIN signal. The hysteresis is approximately 200 mV. 

## **Overcurrent Protection** 

An over−current condition is detected if the voltage on the ITRIP pin is larger than the reference voltage. There is a blanking time of typically 350 ns to improve noise immunity. After a shutdown propagation delay of typically 0.9 s, the FAULT output is switched on. The FAULT output is held on for 20 s (minimum). 

## **Minimum Input Pulse Width** 

When input pulse width is less than 1 s, an output may u not react to the pulse. (Both ON signal and OFF signal) 

## **Calculation of Bootstrap Capacitor Value** 

The bootstrap capacitor value CB is calculated using the following approach. The following parameters influence the choice of bootstrap capacitor: 

- VBS: Bootstrap power supply. 15 V is recommended. 

- QG: Total gate charge of IGBT at VBS = 15 V. 17 nC 

- UVLO: Falling threshold for UVLO. Specified as 12 V. 

- IDMAX: High−side drive power dissipation. 

- Specified as 0.4 mA 

- TONMAX: Maximum ON pulse width of high side IGBT. 

## **Capacitance Calculation Formula:** 

CB = (QG + IDMAX * TONMAX)/(VBS − UVLO) 

The relationship between TONMAX and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated above. The recommended value of CB is in the range of 1 to 47 F, however, the value needs to be u verified prior to production. When not using the bootstrap circuit, each high side driver power supply requires an external independent power supply. 

The over−current protection threshold should be set to be equal or lower to 2 times the module rated current (Io). 

An additional fuse is recommended to protect against system level or abnormal over−current fault conditions. 

## **Capacitors on High Voltage and VDD Supplies** 

Both the high voltage and VDD supplies require an electrolytic capacitor and an additional high frequency capacitor. The recommended value of the high frequency capacitor is between 100 nF and 10 F. u 

**Figure 14. Bootstrap Capacitance vs. Tonmax** 

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**NFAP1060L3TT** 

## **TEST CIRCUITS** 

## **Ices, IR(DB)** 

|**Ices, IR(DB)**|||||||
|---|---|---|---|---|---|---|
||**U+**|**V+**|**W+**|**U−**|**V−**|**W−**|
|A|13|13|13|10|6|2|
|B|10|6|2|17|19|21|



|**U+,V+,W+ : High side phase**<br>**U−,V−,W− : Low side phase**|**U+,V+,W+ : High side phase**<br>**U−,V−,W− : Low side phase**|||
|---|---|---|---|
||**U(DB)**|**V(DB)**|**W(DB)**|
|A|9|5|1|
|B|29|29|29|



## **VCE(sat) (Test by pulse)** 

||**U+**|**V+**|**W+**|**U−**|**V−**|**W−**|
|---|---|---|---|---|---|---|
|A|13|13|13|10|6|2|
|B|10|6|2|17|19|21|
|C|20|22|23|24|25|26|



**==> picture [233 x 310] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBS=15V 9 ICE, IR<br>A A<br>10<br>VBS=15V 5<br>6 VCE, VR<br>VBS=15V 1<br>2<br>VDD=15V 28 B<br>29,17,19,21<br>Figure 15. Test Circuit for ICE<br>VBS=15V 9<br>10 A<br>VBS=15V 5<br>6<br>V IC<br>VBS=15V 1<br>VCE(sat)<br>2<br>VDD=15V 28<br>5V C B<br>29,17,19,21<br>**----- End of picture text -----**<br>


**Figure 16. Test Circuit for VCE(SAT)** 

## **VF (Test by pulse)** 

|**VF (Test by**|**pulse)**|||||||
|---|---|---|---|---|---|---|---|
||**U+**|**V+**||**W+**|**U−**|**V−**|**W−**|
|A|13|13||13|10|6|2|
|B|10|6||2|17|19|21|
|||||||||
||**U(DB)**||**V(DB)**||**W(DB)**|||
|A|9||5||1|||
|B|28||28||28|||



## **IQBS, IQDDL** 

|**IQBS, IQDDL**|||||
|---|---|---|---|---|
||**VBS U+**|**VBS V+**|**VBS W+**|**VDD**|
|A|9|5|1|28|
|B|10|6|2|29|



**==> picture [150 x 102] intentionally omitted <==**

**----- Start of picture text -----**<br>
A<br>V IC<br>VF<br>B<br>**----- End of picture text -----**<br>


**Figure 17. Test Circuit for VF** 

**==> picture [148 x 106] intentionally omitted <==**

**----- Start of picture text -----**<br>
ID<br>A A<br>VD*<br>B<br>**----- End of picture text -----**<br>


**Figure 18. Test Circuit for ID** 

**www.onsemi.com** 

**11** 

**NFAP1060L3TT** 

## **SWITCHING TIME (The circuit is a representative example of the lower side U phase.)** 

||**U+**|**V+**|**W+**|**U−**|**V−**|**W−**|
|---|---|---|---|---|---|---|
|A|13|13|13|13|13|13|
|B|17|19|21|17|19|21|
|C|10|6|2|13|13|13|
|D|17|19|21|10|6|2|
|E|20|22|23|24|25|26|



**==> picture [168 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
Input Signal<br>(0 to 5V)<br>90%<br>lo<br>10%<br>tON tOFF<br>**----- End of picture text -----**<br>


**==> picture [227 x 119] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBS =15V 9<br>10 A<br>VBS =15V 5 C<br>6 CS VCC<br>VBS =15V 1<br>2 D<br>VDD =15V 28<br>E B<br>Input Signal 29,17,19,21 Io<br>**----- End of picture text -----**<br>


**Figure 19. Test Circuit for Switching Time** 

**www.onsemi.com** 

**12** 

**NFAP1060L3TT** 

## **PACKAGE DIMENSIONS** 

## **SIP29, 44.0x20.9 FP−1** CASE 127FB ISSUE O 

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## **LITERATURE FULFILLMENT** : 

◊ 

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**NFAP1060L3TT/D** 

**13**

Updated at April 27, 2026

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