NFAM5065L4BT

**Share Feedback DATA SHEET** Your Opinion Matters **www.onsemi.com** ~~ee~~ 

## Intelligent Power Module (IPM), 650 V, 50 A NFAM5065L4BT 

## **General Description** 

The NFAM5065L4BT is a fully-integrated inverter power module consisting of an independent High side gate driver, LVIC, six IGBT’s and a temperature sensor (VTS or Thermistor (T)), suitable for driving permanent magnet synchronous (PMSM) motors, brushless DC (BLDC) motors and AC asynchronous motors. The IGBT’s are configured in a three-phase bridge with separate emitter connections for the lower legs for maximum flexibility in the choice of control algorithm. 

**DIP39 54.5 x 31.0 CASE MODGC** 

## **MARKING DIAGRAM** 

The power stage has under voltage lockout protection (UVP). Internal boost diodes are provided for high side gate boost drive. 

## **Features** 

- Three-phase 650 V, 50 A IGBT Module with Independent Drivers 

NFAM5065L4BT ZZZATYWW 

- Active Logic Interface 

- Built-in Undervoltage Protection (UVP) 

- Integrated Bootstrap Diodes and Resistors 

- Separate Low-side IGBT Emitter Connections for Individual Current Sensing of Each Phase 

- Temperature Sensor (VTS or Thermistor (T)) 

- UL1557 Certified (File No.339285) 

- This Device is Pb−Free and RoHS Compliant 

Device marking is on package top side 

NFAM5065L4BT = Specific Device Code ZZZ = Assembly Lot Code A = Assembly Location T = Test Location Y = Year WW = Work Week 

## **Typical Applications** 

- Industrial Drives 

- Industrial Pumps 

- Industrial Fans 

- Industrial Automation 

## **ORDERING INFORMATION** 

|**Device**|**Package**|**Shipping**|
|---|---|---|
|NFAM5065L4BT|DIP39<br>54.5 x 31.0<br>(Pb-Free)|90 / Box|



**==> picture [274 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
RTH VTH P U V W<br>VS(U)<br>VDD(UH)VB(U) High SideHVIC1 HS1<br>HIN(U)<br>VS(V)<br>VDD(VH)VB(V) High SideHVIC2 HS2 HS1 HS2 HS3<br>HIN(V)<br>VS(W)<br>VDD(WH)VB(W) High SideHVIC3 HS3<br>HIN(W)<br>VTS LS1 LS2 LS3<br>LIN(U)<br>LIN(V) Low Side LS1<br>LIN(W)CFODVFOCIN ProtectionLVICwith LS2LS3<br>VSS<br>VDD(L)<br>NU NV NW<br>**----- End of picture text -----**<br>


**Figure 1. Application Schematic** 

Publication Order Number: **NFAM5065L4BT/D** 

**1** 

© Semiconductor Components Industries, LLC, 2019 **January, 2024 − Rev. 2** 

**NFAM5065L4BT** 

## **APPLICATION SCHEMATIC** 

**==> picture [473 x 476] intentionally omitted <==**

**----- Start of picture text -----**<br>
5V line<br>RTH (39)<br>* NTC Thermistor<br>VB(U) (3) VTH (38)<br>VS(U) (1) P (37)<br>CS + C1<br>VB<br>HIN(U) (6) HIN HOUT<br>VDD(UH) (4) VDD HVIC1<br>U (36)<br>VSS VS<br>VB(V) (9)<br>VS(V) (7)<br>VB<br>HIN(V) (12) HIN HOUT<br>VDD(VH) (10) VDD HVIC2<br>V (35)<br>VSS VS Motor<br>VB(W) (15)<br>VS(W) (13)<br>MCU VB<br>HIN(W) (18) HIN HOUT<br>VDD(WH) (16) VDD HVIC3<br>W (34)<br>VSS VS<br>VTS (20) VTS<br>LIN(U) (21) LIN(U) OUT(U)<br>LIN(V) (22) LIN(V) NU (33)<br>LIN(W) (23)<br>LIN(W)<br>5V line<br>LVIC<br>VFO (24) VFO OUT(V)<br>CFOD (25) CFOD NV (32)<br>CIN (26) CIN<br>15V line<br>VDD(L) (28) VDD<br>VSS (27) VSS OUT(W)<br>NW (31)<br>Signal for over current trip<br>Phase current<br>**----- End of picture text -----**<br>


**Figure 2. Application Schematic − Adjustable Option** 

**www.onsemi.com** 

**Share Feedback** Your Opinion Matters 

**2** 

**NFAM5065L4BT** 

**BLOCK DIAGRAM** 

**==> picture [442 x 562] intentionally omitted <==**

**----- Start of picture text -----**<br>
RTH (39)<br>* NTC Thermistor<br>VTH (38)<br>VS(U) (1)<br>P (37)<br>VB(U) (3)<br>VB<br>VDD(UH) (4) VDD HOUT<br>HVIC1<br>HIN(U) (6) HIN<br>= VSS o VS = U (36)<br>VS(V) (7)<br>VB(V)(9)<br>VB<br>VDD(VH) (10) VDD HOUT<br>HVIC2<br>HIN(V) (12) HIN<br>VSS VS V (35)<br>VS(W) (13) Sle<br>VB(W) (15)<br>VB<br>VDD(WH) (16) VDD HOUT<br>HVIC3<br>HIN(W) (18) HIN<br>L VSS VS e||| W (34)<br>VTS (20) VTS OUT(U)<br>LIN(U) (21) LIN(U)<br>NU (33)<br>LIN(V) (22) LIN(V)<br>LIN(W) (23) LIN(W)<br>VFO (24) VFO OUT(V)<br>LVIC<br>CFOD (25) CFOD<br>NV (32)<br>CIN (26) CIN<br>VSS (27) VSS<br>VDD(L) (28) VDD OUT(W)<br>NW (31)<br>ele<br>Figure 3. Equivalent Block Diagram<br>**----- End of picture text -----**<br>


> **www.onsemi.com Share Feedback** ~~a~~ **3** Your Opinion Matters 

**NFAM5065L4BT** 

## **PIN FUNCTION DESCRIPTION** 

|**Pin**<br>~~a~~|**Name**|**Description**|
|---|---|---|
|1<br>~~a~~|VS(U)|High-Side Bias Voltage GND for U phase IGBT Driving|
|(2)<br>~~a~~|−|Dummy|
|3<br>~~a~~|VB(U)|High-Side Bias Voltage for U phase IGBT Driving|
|4<br>~~a~~|VDD(UH)|High-Side Bias Voltage for U phase IC|
|(5)<br>~~a~~|−<br>|Dummy<br>|
|6<br>~~eG~~|HIN(U)<br>~~eG~~|Signal Input for High-Side U Phase<br>~~eG~~|
|7<br>~~eG~~|VS(V)<br>~~eG~~|High-Side Bias Voltage GND for V phase IGBT Driving<br>~~eG~~|
|(8)<br>~~a~~|−|Dummy|
|9<br>~~a~~|VB(V)|High-Side Bias Voltage for V phase IGBT Driving|
|10<br>~~a~~|VDD(VH)|High-Side Bias Voltage for V phase IC|
|(11)<br>~~a~~|−|Dummy|
|12<br>~~a~~|HIN(V)|Signal Input for High-Side V Phase|
|13<br>~~a~~|VS(W)|High-Side Bias Voltage GND for W phase IGBT Driving|
|(14)<br>~~a~~<br>~~a~~|−<br>~~es~~|Dummy|
|15<br>~~a~~<br>~~a~~|VB(W)<br>~~es~~|High-Side Bias Voltage for W phase IGBT Driving|
|16<br>~~a~~|VDD(WH)<br>~~es~~|High-Side Bias Voltage for W phase IC|
|(17)<br>~~a~~|−|Dummy|
|18<br>~~a~~|HIN(W)<br>|Signal Input for High-Side W Phase<br>|
|(19)<br>~~eG~~|−<br>~~eG~~|Dummy<br>~~eG~~|
|20<br>~~Ge~~|VTS<br>~~Ge~~|Voltage Output for LVIC Temperature Sensing Unit<br>~~Ge~~|
|21<br>~~a ~~|LIN(U)<br> ~~eG~~|Signal Input for Low-Side U Phase<br>~~eG~~|
|22<br>~~a~~|LIN(V)|Signal Input for Low-Side V Phase|
|23<br>~~a ~~|LIN(W)<br> ~~eG~~|Signal Input for Low-Side W Phase<br>~~eG~~|
|24<br>~~a~~|VFO|Fault Output|
|25<br>~~a ~~|CFOD<br> ~~eG~~|Capacitor for Fault Output Duration Selection<br>~~eG~~|
|26<br>~~a~~|CIN|Input for Current Protection|
|27<br>~~a~~|VSS|Low-Side Common Supply Ground|
|28<br>~~a~~|VDD(L)|Low-Side Bias Voltage for IC and IGBTs Driving|
|(29)<br>~~a~~|−|Dummy|
|(30)<br>~~a~~|−|Dummy|
|31<br>~~a~~|NW<br>|Negative DC-Link Input for U Phase<br>|
|32<br>~~eG~~|NV<br>~~eG~~|Negative DC-Link Input for V Phase<br>~~eG~~|
|33<br>~~a~~|NU|Negative DC-Link Input for W Phase|
|34<br>~~a~~|W|Output for U Phase|
|35<br>~~a~~|V|Output for V Phase|
|36<br>~~a eG~~|U<br>~~eG~~|Output for W Phase<br>~~eG~~|
|37<br>~~a ~~|P<br> ~~eG~~|Positive DC-Link Input<br>~~eG~~|
|38<br>~~a~~|VTH|Thermistor Bias Voltage (T) / Not connection|
|39<br>~~a~~|RTH|Series Resister for Thermistor (Temperature Detection) *optional for T|



1. Pins of () are the dummy for internal connection. These pins should be no connection. 

**www.onsemi.com** ~~—_—~~ 

**www.onsemi.com** 

**Share Feedback** Your Opinion Matters 

**4** 

**NFAM5065L4BT** 

## **ABSOLUTE MAXIMUM RATINGS** (TC = 25 ° C) (Note 2) 

|**ABSOLUTE MAXIMUM RATINGS**|**ABSOLUTE MAXIMUM RATINGS**(TC = 25C = 25= 25°C) (Note 2)||||
|---|---|---|---|---|
|**Symbol**|**Rating**|**Conditions**|**Value**|**Unit**|
|VPN|Supply Voltage|P−NU, NV, NW|450|V|
|VPN(surge)|Supply Voltage (Surge)|P−NU, NV, NW (Note 3)|550|V|
|VPN(PROT)|Self Protection Supply Voltage Limit<br>(Short−Circuit Protection Capability)|VDD = VBS = 13.5 V～16.5 V, TJ= 150°C,<br>VCES < 650 V, Non−Repetitive, < 2 s|400|V|
|Vces|Collector−emitter voltage||650|V|
|VRRM<br>~~a~~|Maximum Repetitive<br>Revers Voltage<br>~~a~~|~~a~~|650<br>~~a~~|V<br>~~a~~|
|±Ic<br>~~a~~|Each IGBT Collector Current<br>~~a~~|~~a~~|±30<br>~~a~~|A<br>~~a~~|
|Iop<br>~~a~~|Output current (peak)<br>~~a~~|PWM control<br>~~a~~|±50<br>~~a~~|A<br>~~a~~|
|±Icp<br>~~a~~|Each IGBT Collector<br>Current (Peak)<br>~~a~~|Under 1 ms Pulse Width<br>~~a~~|±100<br>~~a~~|A<br>~~a~~|
|VDD<br>~~a~~<br>~~——~~|Control Supply Voltage<br>~~a~~<br>~~——~~|VDD(UH,VH,WH), VDD(L)−VSS<br>~~a~~<br>~~oe~~|−0.3 to 20<br>~~a~~<br>~~oe~~|V<br>~~a~~|
|VBS<br>~~——~~|High−Side<br>Control Bias voltage<br>~~——~~|VB(U)−VS(U), VB(V)−VS(V),<br>VB(W)−VS(W)<br>~~oe~~|−0.3 to 20<br>~~oe~~|V|
|VIN<br>~~——~~|Input Signal Voltage<br>~~——~~|HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),<br>LIN(W)–VSS<br>~~oe~~|−0.3 to VDD<br>~~oe~~|V|
|VFO<br>~~——~~|Fault Output Supply Voltage<br>~~——~~|VFO–VSS<br>~~oe~~|−0.3 to VDD<br>~~oe~~|V|
|IFO<br>~~——~~<br>~~a~~|Fault Output Current<br>~~——~~<br>~~a~~|Sink Current at VFO pin<br>~~oe~~<br>~~a~~|2<br>~~oe~~<br>~~a~~|mA<br>~~a~~|
|VCIN<br>~~a~~|Current Sensing<br>Input Voltage<br>~~a~~|CIN–VSS<br>~~a~~|−0.3 to VDD<br>~~a~~|V<br>~~a~~|
|Pc<br>~~a~~|Corrector Dissipation<br>~~a~~|Per One Chip<br>~~a~~|125<br>~~a~~|W<br>~~a~~|
|TJ|Operating Junction Temperature|~~a~~|−40 to +150|°C|
|Tstg<br>~~a~~|Storage temperature<br>~~a~~|~~a~~<br>~~a~~|−40 to +125<br>~~a~~|°C<br>~~a~~|
|Tc<br>~~a~~|Module Case Operation Temperature<br>~~a~~|~~a~~<br>~~a~~|−40 to +125<br>~~a~~|°C<br>~~a~~|
|VISO<br>~~a~~|Isolation voltage<br>~~a~~|60 Hz, Sinusoidal, AC 1 minute,<br>Connection<br>Pins to Heat Sink Plate<br>~~a~~<br>~~a~~|2500<br>~~a~~|Vrms<br>~~a~~|



3. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal. 

## **THERMAL CHARACTERISTICS** 

|**Symbol**<br>~~esee~~|**Rating**<br>~~ee~~|**Conditions**<br>~~ee~~|**Min**<br>~~ee~~|**Typ**<br>~~ee~~|**Max**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|
|Rth(j-c)Q<br>~~esee~~|Junction-to-Case Thermal<br>Resistance<br>~~ee~~|Inverter IGBT Part (per 1/6 module)<br>~~ee~~|−<br>~~ee~~|−<br>~~ee~~|1.0<br>~~ee~~|°C/W<br>~~ee~~|
|Rth(j-c)F<br>~~esee~~||Inverter FWD Part (per 1/6 module)<br>~~ee~~|−<br>~~ee~~|−<br>~~ee~~|1.7<br>~~ee~~|°C/W<br>~~ee~~|



**www.onsemi.com** 

**Share Feedback** Your Opinion Matters 

**5** 

**NFAM5065L4BT** 

## **RECOMMENDED OPERATING CONDITIONS** (Note 5) 

|**Symbol**<br>~~a~~|**Rating**<br>~~a~~<br>~~a~~|**Conditions**<br>~~a~~|**Conditions**<br>~~a~~|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|VPN<br>~~a~~|Supply Voltage<br>~~a~~<br>~~a~~|P−NU, NV, NW||−|300|400|V|
|VDD|Gate Driver Supply<br>Voltages<br>~~a~~<br>~~a~~<br>~~a~~|VDD(UH,VH,WH), VDD(L)−VSS<br>~~a~~||13.5<br>~~a~~|15<br>~~a~~|16.5|V|
|VBS<br>~~a~~<br>~~a~~||VB(U)−VS(U), VB(V)−VS(V),<br>VB(W)−VS(W)<br>~~a~~<br>~~a~~<br>~~ee~~||13.0<br>~~a~~<br>~~ee~~|15<br>~~a~~<br>~~ee~~|18.5<br>~~ee~~|V|
|dVDD / dt,<br>dVBS / dt<br>~~a~~<br>~~a~~|Supply Voltage Variation<br>~~a~~<br>~~a~~|~~a~~<br>~~ee~~||−1<br>~~ee~~|−<br>~~ee~~|1<br>~~ee~~|V/ s|
|fPWM<br>~~a~~|PWM Frequency<br>~~a~~|~~ee ~~||1<br> ~~ee ~~|−<br> ~~ee ~~|20<br> ~~ee~~|kHz|
|DT<br>~~a ~~|Dead Time<br> ~~a~~|Turn-off to Turn-on (external)||1.5|−|−|s|
|Io|Allowable r.m.s. Current|VPN = 300 V,<br>VDD = 15 V,<br>P.F. = 0.8<br>Tc≤125°C,<br>Tj≤150°C<br>(Note 5)|fPWM= 5 kHz|−|−|30.0|Arms|
||||fPWM=  15 kHz|−|−|21.2||
|PWIN (on)|Allowable Input Pulse<br>Width<br>~~PP~~|200 V≤VPN≤400 V<br>13.5 V≤VDD≤16.5 V<br>13.0 V≤VBS≤18.5 V<br>−20°C≤Tc≤100°C<br>~~PP~~||1.0|−|−|s|
|PWIN (off)||||1.5|−|−||
|~~a~~|Package Mounting Torque|M3 type screw||0.6|0.7|0.9|Nm|



Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 

5. Allowable r.m.s current depends on the actual conditions. 

6. Flatness tolerance of the heatsink should be within −50 m to +100 m. 

## **ELECTRICAL CHARACTERISTICS** (TC = 25 ° C, VDD = 15 V, VBS = 15 V, unless otherwise specified.) (Note 7) 

|Ices<br>~~ns~~<br>~~fo~~|Collector-Emitter Leakage<br>Current<br>~~ns~~<br>~~fo~~|Collector-Emitter Leakage<br>Current<br>~~ns~~<br>~~fo~~|Vce = Vces, TJ= 25°C<br>~~ns~~<br>|−<br>~~ns~~<br>~~ee~~<br>|−<br>~~ns~~<br>~~ee~~<br>|1<br>~~ns~~<br>|mA<br>~~ns~~<br>|
|---|---|---|---|---|---|---|---|
||||Vce = Vces, TJ= 150°C<br>~~ns~~<br>|−<br>~~ns~~<br>~~ee~~<br>|−<br>~~ns~~<br>~~ee~~<br>|10<br>~~ns~~<br>|mA<br>~~ns~~<br>|
|VCE(sat)<br>~~fo~~|Collector-Emitter Saturation<br>Voltage<br>~~fo~~||VDD = VBS = 15 V, IN = 5 V<br>Ic = 50 A, TJ= 25°C<br>|−<br>~~ee~~<br>|1.65<br>~~ee~~<br>|2.30<br>|V<br>|
||||VDD = VBS = 15 V, IN = 5 V<br>Ic = 50 A, TJ= 150°C<br>|−<br>~~ee~~<br>|1.85<br>~~ee~~<br>|−<br>|V<br>|
|VF<br>|FWDi Forward Voltage<br>||IN = 0 V, Ic = 50 A, TJ= 25°C<br>~~OO~~|−<br>~~OO~~|2.00<br>~~OO~~|2.40<br>~~OO~~|V<br>~~OO~~|
||||IN = 0 V, Ic = 50 A, TJ= 150°C<br>~~OO~~|−<br>~~OO~~<br>~~re~~|2.00<br>~~OO~~<br>~~a~~|−<br>~~OO~~<br>~~a~~|V<br>~~OO~~|
|ton|Switching Times|High Side|VPN = 300 V, VDD(H) = VDD(L) = 15 V<br>Ic = 50 A, TJ= 25°C, IN = 0⇔5 V<br>Inductive Load|0.90<br>~~re~~<br>~~re~~|1.50<br>~~a~~|2.10<br>~~a~~|s|
|tc(on)||||−<br>~~re ~~<br>~~re~~<br>~~re~~|0.40<br> ~~a~~<br>~~ee~~|0.70<br>~~a~~<br>~~ee~~|s<br>~~ee~~|
|toff||||−<br>~~re~~<br>~~re~~<br>~~re~~|1.80<br>~~ee~~<br>~~ee~~|2.40<br>~~ee~~<br>~~ee~~|s<br>~~ee~~<br>~~ee~~|
|tc(off)||||−<br>~~re~~<br>~~re~~<br>~~re~~|0.25<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.75<br>~~ee~~<br>~~ee~~<br>~~ee~~|s<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|trr||||−<br>~~re~~<br>~~re~~<br>~~re~~|0.25<br>~~ee~~<br>~~ee~~<br>~~ee~~|−<br>~~ee~~<br>~~ee~~<br>~~ee~~|s<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|ton||Low Side|VPN = 300 V, VDD(H) = VDD(L) = 15 V<br>Ic = 50 A, TJ= 25°C, IN = 0⇔5 V<br>Inductive Load|0.90<br>~~re~~<br>~~re~~<br>~~re~~|1.50<br>~~ee~~<br>~~ee~~<br>~~ee~~|2.10<br>~~ee~~<br>~~ee~~<br>~~es~~|s<br>~~ee~~<br>~~ee~~|
|tc(on)||||−<br>~~re~~<br>~~re~~<br>~~re~~|0.30<br>~~ee~~<br>~~ee~~<br>~~ee~~|0.60<br>~~ee~~<br>~~es~~<br>~~ee~~|s<br>~~ee~~<br>~~ee~~|
|toff<br>~~_——~~||||−<br>~~re ~~<br>~~re~~<br>~~re~~|1.70<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|2.30<br> ~~es~~<br>~~ee~~<br>~~ee~~|s<br>~~ee~~<br>~~ee~~|
|tc(off)<br>~~_——~~||||−<br>~~re~~<br>~~re~~|0.25<br>~~ee~~<br>~~ee~~|0.75<br>~~ee~~<br>~~ee~~|s<br>~~ee~~<br>~~ee~~|
|trr<br>~~_——~~||||−<br>~~re~~<br>~~a~~|0.25<br>~~ee~~<br>~~a~~|−<br>~~ee~~<br>~~a~~|s<br>~~ee~~<br>~~a~~|



**www.onsemi.com** 

**Share Feedback** Your Opinion Matters 

**6** 

## **NFAM5065L4BT** 

**ELECTRICAL CHARACTERISTICS** (TC = 25 ° C, VDD = 15 V, VBS = 15 V, unless otherwise specified.) (Note 7) (continued) 

|IQDDH<br>~~jj~~|Quiescent VDD Supply<br>Current<br>~~jj~~<br>~~ff~~|VDD(UH,VH,WH) = 15 V,<br>HIN(U,V,W) = 0 V<br>~~ff~~|VDD(UH)−VSS<br>VDD(VH)−VSS<br>VDD(WH)−VSS<br>~~fffit~~|−<br>~~fit~~|−<br>~~fit~~|0.30<br>~~te~~|mA<br>~~te~~|
|---|---|---|---|---|---|---|---|
|IQDDL<br>~~jj~~||VDD(L) = 15 V,<br>LIN(U,V,W) = 0 V<br>~~ff~~|VDD(L)−VSS<br>~~fffit~~|−<br>~~fit~~|−<br>~~fit~~|3.50<br>~~te~~|mA<br>~~te~~|
|IPDDH<br>~~jj~~<br>~~eee~~|Operating VCC Supply<br>Current<br>~~jj~~<br>~~ff~~<br>~~eee~~|VDD(UH,VH,WH) = 15 V,<br>fPWM= 20 kHz, Duty = 50%,<br>Applied to one PWM Signal<br>Input for High-Side<br>~~ff~~<br>~~eee~~|VDD(UH)−VSS<br>VDD(VH)−VSS<br>VDD(WH)−VSS<br>~~ff fit~~<br>~~eee~~|−<br>~~fit~~<br>~~eee~~|−<br>~~fit ~~<br>~~eee~~|0.40<br> ~~te~~<br>~~eee~~|mA<br>~~te~~<br>~~eee~~|
|IPDDL<br>~~eee~~||VDD(L) = 15 V,<br>fPWM= 20 kHz, Duty = 50%,<br>Applied to one PWM Signal<br>Input for Low-Side<br>~~eee~~<br>~~ee~~|VDD(L)−VSS<br>~~eee~~<br>~~eee~~|−<br>~~eee~~<br>~~eee~~|−<br>~~eee~~<br>~~eee~~|6.00<br>~~eee~~<br>~~eee~~|mA<br>~~eee~~<br>~~eee~~|
|IQBS<br>~~ee~~|Quiescent VBS Supply<br>Current<br>~~ee~~|VBS = 15 V,<br>HIN(U,V,W) = 0 V<br>~~ee~~<br>~~ee~~|VB(U)−VS(U)<br>VB(V)−VS(V)<br>VB(W)−VS(W)<br>~~ee~~<br>~~eee~~|−<br>~~ee~~<br>~~eee~~|−<br>~~ee~~<br>~~eee~~|0.30<br>~~ee~~<br>~~eee~~|mA<br>~~ee~~<br>~~eee~~|
|IPBS<br>~~rs~~|Operating VBS Supply<br>Current|VDD = VBS = 15 V,<br>fPWM= 20 kHz, Duty = 50%,<br>Applied to one PWM Signal<br>Input for High-Side<br>~~ee ~~<br>~~A~~|VB(U)−VS(U)<br>VB(V)−VS(V)<br>VB(W)−VS(W)<br> ~~eee~~|−<br>~~eee~~<br>~~er~~|−<br>~~eee~~<br>~~er ee~~|5.00<br>~~eee~~<br>~~ee~~|mA<br>~~eee~~<br>~~ee~~|
|VIN(ON)<br>~~es~~<br>~~rs~~<br>~~a~~|ON Threshold Voltage<br>~~es~~|HIN(U,V,W)−VSS, LIN(U,V,W)−VSS<br>~~es~~<br>~~A~~||−<br>~~es~~<br>~~er~~<br>~~es~~|−<br>~~es~~<br>~~er ee~~|2.6<br>~~es~~<br>~~ee~~|V<br>~~es~~<br>~~ee~~|
|VIN(OFF)<br>~~es~~<br>~~rs~~<br>~~a~~|OFF Threshold Voltage<br>~~es~~|||0.8<br>~~es~~<br>~~er~~<br>~~es~~|−<br>~~es~~<br>~~er ee~~|−<br>~~es~~<br>~~ee~~|V<br>~~es~~<br>~~ee~~|
|VCIN(ref)<br>~~rs~~<br>~~a—~~|Short Circuit Trip Level<br>~~SS —_~~|VDD = 15 V, CIN−VSS<br>~~A~~<br>~~—_~~||0.46<br>~~er~~<br>~~es~~<br>~~—_~~|0.48<br>~~er ee~~|0.50<br>~~ee~~|V<br>~~ee~~|
|UVDDD<br>~~—~~|Supply Circuit<br>Under-Voltage Protection<br>~~SS —_~~<br>~~I~~<br>~~I~~<br>~~a~~|Detection Level<br>~~—_~~||10.3<br>~~—_~~|−|12.5|V|
|UVDDR<br>~~—~~<br>~~I~~||Reset Level<br>~~—_~~<br>~~I~~<br>~~a~~||10.8<br>~~—_~~<br>~~I~~<br>~~a~~|−<br>~~I~~<br>~~a~~|13.0<br>~~I~~<br>~~a~~|V<br>~~I~~<br>~~a~~|
|UVBSD<br>~~—~~<br>~~I~~||Detection Level<br>~~—_~~<br>~~I~~<br>~~a~~||10.0<br>~~—_~~<br>~~I~~<br>~~a~~|−<br>~~I~~<br>~~a~~|12.0<br>~~I~~<br>~~a~~|V<br>~~I~~<br>~~a~~|
|UVBSR<br>~~—~~<br>~~a~~||Reset Level<br>~~—_~~<br>~~a~~<br>~~a~~||10.5<br>~~—_~~<br>~~a~~<br>~~a~~|−<br>~~a~~<br>~~a~~|12.5<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|VTS<br>~~—~~<br>~~a~~|Voltage Output for LVIC<br>Temperature Sensing Unit<br>~~SS —_~~<br>~~a~~<br>~~ee~~|VTS−VSS = 10 nF, Temp. = 25°C<br>~~—_~~<br>~~a~~<br>~~ee~~||0.905<br>~~—_~~<br>~~a~~<br>~~ee~~|1.030<br>~~a~~<br>~~ee~~|1.155<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|VFOH<br>~~eee~~|Fault Output Voltage<br>~~eee~~|VDD = 0 V, CIN = 0 V,<br>VFO Circuit: 10 k to 5 V Pull-up<br>~~eee~~||4.9<br>~~eee~~|−<br>~~eee~~|−<br>~~eee~~|V<br>~~eee~~|
|VFOL<br>~~eee~~<br>~~|~~||VDD = 0 V, CIN = 1 V,<br>VFO Circuit: 10 k to 5 V Pull-up<br>~~eee~~<br>~~poe~~||−<br>~~eee~~<br>~~poe~~|−<br>~~eee~~<br>~~poe~~|0.95<br>~~eee~~<br>~~poe~~|V<br>~~eee~~<br>~~poe~~|
|tFOD<br>~~a~~|Fault-Output Pulse Width|CFOD = 22 nF||1.6|2.4|−|ms|



8. The fault−out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation: tFOD = 0.11 × 10[6] × CFOD (s). 

9. Values based on design and/or characterization. 

> **www.onsemi.com Share Feedback** 

> **7** © Your Opinion Matters 

**NFAM5065L4BT** 

## **Temperature of LVIC versus VTS Characteristics** 

**==> picture [361 x 210] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.0<br>Po<br>a ss ss sD (<br>po<br>a Dell<br>3.5 ee<br>a OD et et<br>eeee<br>a OQce Des Dee<br>3.0 eG<br>2.5 aeepoaa aaaessscescee eeaceeeaeeceee eeelee eeee eeee eee<br>aaacca ee eaee eeee eees eeeeee ee eeeeee<br>2.0 a ee ee ee es es es<br>a aa aee ek akes Pk ee a esee essssese<br>0Baae Hae aa a es es ee es es ee ee ee<br>1.5 aeekk a Ia aaa a a a a eeaee ee essses ee eeee eeee<br>DE a a a<br>aQOa a a ss es es ee<br>1.0 GGCN SC<br>40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130<br>LVIC Temperature ( C)<br>VTS Output Voltage (V)<br>**----- End of picture text -----**<br>


**Figure 4. Temperature of LVIC versus VTS Characteristics** 

**Table 1. THERMISTOR CHARACTERISTICS (INCLUDED ONLY IN NFAM5060L4BT)** 

|**Parameter**<br>~~a~~|**Symbol**<br>~~es~~|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Resistance<br>~~a~~<br>~~a~~|R25<br>~~es~~<br>~~es~~|Tc = 25°C|46.530|47|47.47|k|
|Resistance<br>~~a~~<br>~~a~~|R125<br>~~es~~<br>~~es~~|Tc = 100°C|1.344|1.406|1.471|k|
|B-Constant (25−50°C)<br>~~a~~|−<br>~~es~~|B|4009.5|4050|4090.5|K|
|Temperature range|−|−|−40|−|+125|°C|



**==> picture [376 x 226] intentionally omitted <==**

**----- Start of picture text -----**<br>
10000<br>a<br>aSSSS<br>po<br>1000 wo] ft | | | | EE |PT<br>aa aaa ee a es es ee min |_||_|<br>a ee typ |_|<br>100 | | | |] NET | max |<br>SS SS | EE SS SS SS SS SS SS<br>a<br>poa a<br>a a a s,s<br>10<br>| |} | |<br>eeee ee ee— ee Se<br>a COpS<br>1 pt tT | Pt Et<br>−40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 120 130<br>Case Temperature Tc ( C)<br>]<br>Thermistor Resistance [k<br>**----- End of picture text -----**<br>


**Figure 5. Thermistor Resistance versus Case Temperature** 

**www.onsemi.com** 

**Share Feedback** Your Opinion Matters 

**8** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [357 x 68] intentionally omitted <==**

**----- Start of picture text -----**<br>
DIP39, 54.50x31.00x5.60, 1.78P<br>CASE MODGC<br>ISSUE C<br>DATE 05 MAY 2025<br>12 . DIMENSIONCONTROLL ING  ANDDIMENSION:TOLERANCING PERMILLIMETERSASME Y14.5M,_ 2009. , Low ||_mi._|MILIMETERS Lowa | MNSMETERS<br>**----- End of picture text -----**<br>


**==> picture [482 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
GENERIC<br>MARKING DIAGRAM*<br>XXXXXXXXXXXXXXXXX<br>ZZZATYWW<br>2D<br>CODE<br>XXXXX = Specific Device Code<br>ZZZ      = Assembly Lot Code *This information is generic. Please refer to device data<br>AT        = Assembly & Test Location sheet for actual part marking. Pb−Free indicator, “G” or<br>Y          = Year microdot “ ”, may or may not be present. Some products<br>WW     = Work Week may not follow the Generic Marking.<br>Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98AON91300G Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: DIP39, 54.50x31.00x5.60, 1.78P PAGE 1 OF 1<br>**----- End of picture text -----**<br>


**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba onsemi **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2018 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

**TECHNICAL PUBLICATIONS** : **ONLINE SUPPORT** : www.onsemi.com/support **Technical Library:** www.onsemi.com/design/resources/technical−documentation **For additional information, please contact your local Sales Representative at onsemi Website:** www.onsemi.com www.onsemi.com/support/sales 

**==> picture [232 x 43] intentionally omitted <==**

