NFAM3512L7B

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## Intelligent Power Module (IPM) 

## **Inverter, 1200 V, 35 A** 

## NFAM3512L7B 

NFAM3512L7B is an advanced IPM module providing a fully−featured, high−performance inverter output stage for AC Induction, BLDC and PMSM motors. These modules integrate optimized gate drive of the built−in IGBTs to minimize EMI and losses, while also providing multiple on−module protection features including under−voltage lockouts, over−current shutdown, thermal monitoring of drive IC, and fault reporting. The built−in, high−speed HVIC requires only a single supply voltage and translates the incoming logic−level gate inputs to the high−voltage, high−current drive signals required to properly drive the module’s internal IGBTs. Separate negative IGBT terminals are available for each phase to support the widest variety of control algorithms. 

## **Features** 

- 1200 V 35 A 3−Phase FS7 IGBT Inverter, Including Control ICs for Gate Drive and Protections 

**CASE MODGX DIP39, 54.5x31.0 EP−2** 

## **MARKING DIAGRAM** 

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NFAM3512L7B<br>ZZZATYWW<br>2D<br>code<br>**----- End of picture text -----**<br>


- Very Low Thermal Resistance Using Al2O3 DBC Substrate 

- Active Logic Interface 

- Built−in Under−voltage Protection (UVP) 

- Built−In Bootstrap Diodes/Resistors 

- Separate Low−side IGBT Emitter Connections for Individual Current Sensing of Each Phase 

- Temperature Sensor (TSU Output by LVIC) 

NFAM3512L7B = Specific Device Code ZZZ = Assembly Lot Code A = Assembly Location T = Test Location Y = Year WW = Work Week Device marking is on package top side 

- UL Certification: E209204 

- This is a Pb−Free Device 

## **Typical Application** 

- Industrial Drives 

- Industrial Pumps 

## **ORDERING INFORMATION** 

|**Device**|**Package**|**Shipping**<br>**(Qty / Packing)**|
|---|---|---|
|NFAM3512L7B|DIP39,<br>31.0 x 54.5|90 / BOX|



- Industrial Fans 

- Industrial Automation 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2023 **December, 2023 − Rev. 1** 

**NFAM3512L7B/D** 

**NFAM3512L7B** 

## **PIN CONFIGURATION** 

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(1) VS(U)<br>(3) VB(U)<br>do OQ OLE<br>N.C (4) VDD(UH)<br>(6) HIN(U)<br>(7) VS(V)<br>P (37) a (9) VB(V)<br>E<br>(10) VDD(VH)<br>(12) HIN(V)<br>U (36) =i.<br>Case Temperature (Tc)<br>(13) VS(W)<br>Detecting point<br>(15) VB(W)<br>V (35) = aon ren<br>_ (16) VDD(WH)<br>(18) HIN(W)<br>(20) VTS<br>W (34)<br>(21) LIN(U)<br>E = (22) LIN(V)<br>(23) LIN(W)<br>NU (33) =a Nwh =—= (24) VFO<br>(25) CFOD<br>NV (32) (26) CIN<br>(27) VSS<br>NW (31) (28) VDD(L)<br>“10 OQ O| B<br>**----- End of picture text -----**<br>


**Figure 1. Pin Configuration – Top View** 

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**NFAM3512L7B** 

## **PIN DESCRIPTION** 

|**PIN DESCRIPTION**|||
|---|---|---|
|**Pin**|**Name**|**Description**|
|1|VS(U)|High−Side Bias Voltage GND for U Phase IGBT Driving|
|(2)|−|Dummy|
|3|VB(U)|High−Side Bias Voltage for U Phase IGBT Driving|
|4|VDD(UH)|High−Side Bias Voltage for U Phase IC|
|(5)|−|Dummy|
|6|HIN(U)|Signal Input for High−Side U Phase|
|7|VS(V)|High−Side Bias Voltage GND for V Phase IGBT Driving|
|(8)|−|Dummy|
|9|VB(V)|High−Side Bias Voltage for V Phase IGBT Driving|
|10|VDD(VH)|High−Side Bias Voltage for V Phase IC|
|(11)|−|Dummy|
|12|HIN(V)|Signal Input for High−Side V Phase|
|13|VS(W)|High−Side Bias Voltage GND for W Phase IGBT Driving|
|(14)|−|Dummy|
|15|VB(W)|High−Side Bias Voltage for W Phase IGBT Driving|
|16|VDD(WH)|High−Side Bias Voltage for W Phase IC|
|(17)|−|Dummy|
|18|HIN(W)|Signal Input for High−Side W Phase|
|(19)|−|Dummy|
|20|VTS|Voltage Output for LVIC Temperature Sensing Unit|
|21|LIN(U)|Signal Input for Low−Side U Phase|
|22|LIN(V)|Signal Input for Low−Side V Phase|
|23|LIN(W)|Signal Input for Low−Side W Phase|
|24|VFO|Fault Output|
|25|CFOD|Capacitor for Fault Output Duration Selection|
|26|CIN|Input for Current Protection|
|27|VSS|Low−Side Common Supply Ground|
|28|VDD(L)|Low−Side Bias Voltage for IC and IGBTs Driving|
|(29)|−|Dummy|
|(30)|−|Dummy|
|31|NW|Negative DC−Link Input for W Phase|
|32|NV|Negative DC−Link Input for V Phase|
|33|NU|Negative DC−Link Input for U Phase|
|34|W|Output for W Phase|
|35|V|Output for V Phase|
|36|U|Output for U Phase|
|37|P|Positive DC−Link Input|
|38|N.C|No Connection|
|(39)|−|Dummy|



NOTE: Pins of ( ) are the dummy for internal connection. These pins should be no connection. 

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**NFAM3512L7B** 

## **INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS** 

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VS(U) (1)<br>P (37)<br>VB(U) (3)<br>VDD(UH) (4) VDD VB<br>HO<br>HIN(U) (6) HIN<br>VSS VS<br>U (36)<br>VS(V) (7)<br>VB(V) (9)<br>VDD(VH) (10) VDD VB<br>HIN(V) (12) HIN HO<br>VSS VS V (35)<br>VS(W) (13)<br>VB(W) (15)<br>VDD(WH) (16) VDD VB<br>HO<br>HIN(W) (18) HIN<br>VSS VS<br>W (34)<br>VTS (20) VTS<br>LO<br>LIN(U) (21) LIN(U)<br>LIN(V) (22) LIN(V)<br>NU (33)<br>LIN(W) (23) LIN(W)<br>VFO (24) VFO<br>LO<br>CFOD (25) CFOD<br>CIN (26) CIN<br>NV (32)<br>VSS (27) VSS<br>VDD(L) (28) VDD<br>LO<br>NW (31)<br>**----- End of picture text -----**<br>


**Figure 2. Internal Block Diagram** 

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## **NFAM3512L7B** 

## **ABSOLUTE MAXIMUM RATINGS** (VDD = 15 V and Tj = 25 ° C, Unless Otherwise Specified) 

|**ABSOLUTE**|**MAXIMUM RATINGS**(VDD= 15 V and|Tj = 25°C, Unless Otherwise Specified)|||
|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Condition**|**Max**|**Unit**|
|**INVERTER PART**|||||
|VPN|Supply Voltage|Applied between P − NU, NV, NW|900|V|
|VPN (surge)|Supply Voltage (Surge)|Applied between P − NU, NV, NW (Note 1)|1000|V|
|Vces|Collector − Emitter Voltage||1200|V|
|VRRM|Maximum Repetitive Reverse Voltage||1200|V|
|�Ic|Each IGBT Collector Current||35|A|
|�Icp|Each IGBT Collector Current (Peak)|Tc = 25°C, Tj ≤150°C, under 1 ms Pulse Width|70|A|
|Pc|Collector Dissipation|Tc = 25°C per One Chip (Note 2)|167|W|
|Tj|Operating Junction Temperature||−40 ~ 150|°C|
|**CONTROL PART**|||||
|VDD|Control Supply Voltage|Applied between VDD(H), VDD(L) − VSS|20|V|
|VBS|High−Side Control Bias Voltage|Applied between VB(U) – VS(U),<br>VB(V) – VS(V), VB(W) – VS(W)|20|V|
|VIN|Input Signal Voltage|Applied between HIN(U), HIN(V), HIN(W),<br>LIN(U), LIN(V), LIN(W) − VSS|−0.3 ~ VDD + 0.3|V|
|VFO|Fault Output Supply Voltage|Applied between VFO – VSS|−0.3 ~ VDD + 0.3|V|
|IFO|Fault Output Current|Sink Current at VFO pin|2|mA|
|VCIN|Current Sensing Input Voltage|Applied between CIN − VSS|−0.3 ~ VDD + 0.3|V|
|**TOTAL SYSTEM**|||||
|VPN(PROT)|Self−Protection Supply Voltage Limit<br>(Short Circuit Protection Capability)|VDD = VBS = 13.5 ~ 16.5 V, Tj = 150°C,<br>Non−repetitive, < 2�s|800|V|
|Tc|Case Operation Temperature|See Figure 1|−40 ~ 125|°C|
|Tstg|Storage Temperature||−40 ~ 125|°C|
|Viso|Isolation Voltage|60 Hz, Sinusoidal, AC 1 minute,<br>Connection Pins to Heat Sink Plate|2500|Vrmc|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL RESISTANCE** 

|**Symbol**|**Rating**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Rth(j−c)Q|Junction to Case Thermal<br>Resistance (Note 3)|Inverter IGBT Part (per 1/6 Module)|−|−|0.75|°C/W|
|Rth(j−c)F||Inverter FRD Part (per 1/6 Module)|−|−|1.00|°C/W|



1. Surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal. 

2. Calculation value considered to design factor. 

3. For the measurement point of case temperature (Tc), please refer to Figure 1. 

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**NFAM3512L7B** 

## **ELECTRICAL CHARACTERISTICS** (VDD = 15 V and Tj = 25 ° C, Unless Otherwise Specified) 

|**Symbol**|**Symbol**|**Description**|**Conditions**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|**INVERTER PART**|||||||||
|Ices||Collector − Emitter<br>Leakage Current|Tj = 25°C, VCE = VCES||−|−|1|mA|
||||Tj = 150°C, VCE = VCES||−|−|10|mA|
|VCE(sat)||Collector − Emitter<br>Saturation Voltage|VDD = VBS = 15 V, Ic = 30 A, Tj = 25°C||−|1.6|2.0|V|
||||VDD = VBS = 15 V, Ic = 30 A,  Tj = 150°C||−|1.9|−|V|
||VF|FWDi Forward Voltage|VIN = 0 V, IF = 30A, Tj = 25°C||−|1.7|2.1|V|
||||VIN = 0 V, IF = 30A, Tj = 150°C|||1.8|−|V|
|HS|ton|High Side Switching Times|VPN = 600 V, VDD = 15 V, Ic = 30 A<br>Tj = 25°C,Inductive Load Switching<br>See Figure 3, 23, 24<br>(Note 1)||1.00|1.30|1.90|�s|
||tc(on)||||−|0.17|0.55|�s|
||toff||||−|1.60|2.00|�s|
||tc(off)||||−|0.23|0.30|�s|
||trr||||−|0.22|−|�s|
|LS|ton|Low Side Switching Times|||1.00|1.30|1.90|�s|
||tc(on)||||−|0.22|0.55|�s|
||toff||||−|1.70|2.00|�s|
||tc(off)||||−|0.24|0.30|�s|
||trr||||−|0.28|−|�s|
|**CONTROL PART**|||||||||
|IQDDH||Quiescent VDD Suppl<br>Current|VDD(UH, VH, WH) = 15 V,<br>HIN(U,V,W) = 0 V|VDD(UH) − VSS<br>VDD(VH) − VSS<br>VDD(WH) − VSS|−|−|0.30|mA|
|IQDDL|||VDD(L) = 15 V,<br>LIN(U, V, W) = 0 V|VDD(L) − VSS|−|−|2.0|mA|
|IPDDH||Operating VDD Supply<br>Current|VDD(UH, VH, WH) = 15 V,<br>fPWM = 20 kHz, duty = 50%,<br>applied to one PWM Signal Input for<br>High−Side|VDD(UH) – VSS<br>VDD(VH) – VSS<br>VDD(WH) – VSS|−|−|0.4|mA|
|IPDDL|||VDD(L) = 15 V, fPWM = 20 kHz,<br>duty = 50%, applied to one PWM<br>Signal Input for Low−Side|VDD(L) − VSS|−|−|5.0|mA|
|IQBS||Quiescent VBS Supply<br>Current|VBS(U, V, W) = 15 V,<br>HIN(U, V, W) = 0V|VB(U) – VS(U),<br>VB(V) – VS(V),<br>VB(W) – VS(W)|−|−|0.3|mA|
|IPBS||Operating VBS Supply<br>Current|VDD(UH,VH,WH) = VBS(U, V, W) =<br>15 V, fPWM = 20 kHz, duty = 50%,<br>applied to one PWM Signal Input for<br>High−Side|VB(U) – VS(U),<br>VB(V) – VS(V),<br>VB(W) – VS(W)|−|−|3.5|mA|
|VIN(ON)||ON Threshold Voltage|HIN(U, V, W) − VSS, LIN(U, V, W) − VSS||−|−|2.6|V|
|VIN(OFF)||OFF Threshold Voltage|||0.8|−|−|V|
|VCIN(ref)||Over current trip level|VDD = 15 V|CIN − VSS|0.46|0.48|0.50|V|
|UVDDD||Supply Circuit Under−<br>Voltage Protection|Detection Level||10.3|−|12.5|V|
|UVDDR|||Reset Level||10.8|−|13.0|V|
|UVBSD||Supply Circuit Under− Volt-<br>age Protection|Detection Level||10.0|−|12.0|V|
|UVBSR|||Reset Levelp||10.5|−|12.5|V|
|VTS||Voltage Output for LVIC<br>Temperature Sensing Unit|VTS − VSS = 5.1 k�, Temp. = 25°C (Note 5)||1.12|1.25|1.38|mV|



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**NFAM3512L7B** 

## **ELECTRICAL CHARACTERISTICS** (VDD = 15 V and Tj = 25 ° C, Unless Otherwise Specified) 

|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**CONTROL PART**|||||||
|VFOH|Fault Output Voltage|VDD(L) = 0 V, CIN = 0 V,<br>VFO Circuit: 10 k�to 5 V Pull−up|4.9|−|−|V|
|VFOL||VDD(L) = 0 V, CIN = 1 V,<br>VFO Circuit: 10 k�to 5 V Pull−up|−|−|0.95|V|
|tFOD|Fault−Out Pulse Width|CFOD = 22 nF (Note 6)|1.6|2.4|−|ms|
|**BOOTSTRAP**|**SECTION**||||||
|VF|Bootstrap Diode Forward<br>Current|If = 0.1 A (See Figure 6)|2.1|2.5|2.9|V|
|RBOOT|Built−in Limiting Resistance||12.5|15.5|18.5|Ω|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

NOTES: Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at Tj = Ta = 25 ° C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. Values based on design and/or characterization. 

4. ton and toff include the propagation delay of the internal drive IC. tc(on) and tc(off) are the switching times of IGBT under the given gate−driving condition internally. For the detailed information, please see Figure 3. 

5. TLVIC is the temperature of LVIC itself. VTS is only for sensing temperature of LVIC and cannot shutdown IGBTs automatically. The relationship between VTS voltage output and LVIC temperature is described in Figure 4. It is recommended to add 5.1k � pull down resistor between VTS and VSS (Signal Ground) as described in Figure 5 for linear output characteristics at low temperature. To reduce noise, 10 nF cap is recommended as well. Refer to the application note for usage of VTS. 

6. The fault−out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation: tFOD = 0.11 x 10[6] x CFOD [s]. 

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ton toff<br>VIN trr VIN<br>100% Ic<br>90% Ic<br>Vce Vce<br>10% Ic 10% Vce 10% Vce 10% Ic<br>Ic Ic<br>tc(on) tc(off)<br>**----- End of picture text -----**<br>


**Figure 3. Switching Time Definitions** 

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**NFAM3512L7B** 

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3.0<br>|<br>ee<br>ota<br>2.0 er<br>a<br>LVIC Temperature ( ° C)<br>VTS Ouptput Voltage (V)<br>**----- End of picture text -----**<br>


**Figure 4. Temperature of LVIC versus VOT Characteristics** 

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Inside LVIC of IPM “<br>|<br>|<br>|<br>Temperature | 10 nF<br>sensing voltage VTS<br>MCU<br>Ref rd |<br>~ Tt VSS 5.1 k5.1<br>~ L =E _ =_] ~<br>Figure 5. Internal Block Diagram and Interface Circuit of VTS<br>0.80 FSR0000 080 Seseen 0.05<br>0.70<br>EEEEEEECEEEEEEEEEEE 0.04 EERE CEE<br>0.60<br>PEC EECEEE EEE EEE EEE PEA<br>0.50<br>0.03<br>PEEEEEEEEEEE TEESE EEE EEE Pett tee At<br>0.40<br>PCE Pi Tee Ty Pe<br>0.30 0.02<br>PEECEEEECOCOCHEE EEEEEE tttPAtt<br>PT TT TT tt<br>0.20<br>PEER EEE EEE EE EEE EEE EEE 0.01 PCAyA<br>0.10 20en07 400 Senee SEGeeee Zee<br>0.00 EEE EEE EEE EE EEE EEE EH 0.00 PTT PerTT<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.6<br>VF (V) VF (V)<br>If (A) If (A)<br>**----- End of picture text -----**<br>


**Figure 6. Characteristics of Bootstrap Diode/Resistor (Right Figure is Enlarged Figure)** 

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**NFAM3512L7B** 

## **RECOMMENDED OPERATING CONDITIONS** 

|**Symbol**|**Rating**|**Conditions**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|VPN|Supply Voltage|Applied between P − NU, NV, NW||−|600|800|V|
|VDD|Control Supply Voltage|Applied between VDD(UH, VH, WH),<br>VDD(L) − VSS||13.5|15|16.5|V|
|VBS|High−Side Bias Voltages|Applied between VB(U) − VS(U), VB(V) −<br>VS(V), VB(W) − VS(W)||13.0|15|18.5|V|
|dVDD / dt<br>dVBS / dt|Supply Voltage Variation|||−1|−|1|V /�s|
|Tdead|Blanking Time for Preventing<br>Arm − Short|For Each Input Signal||2.0||−|�s|
|fPWM|PWM Frequency|−40°C≤Tc≥125°C, −40°C≤Tj≤150°C||2.0||20|kHz|
|Io|Allowable r.m.s. Current|VPN =  600 V,<br>VDD = VBS = 15 V,<br>P.F. = 0.8,<br>Tc≤125°C, Tj≤150°C,<br>(Note 7)|fPWM = 5 kHz|−|−|27.5|A rms|
||||fPWM = 15 kHz|−|−|18.2||
|PWIN (ON)|Minimum Input Pulse Width|VDD = VBS = 15 V, Wiring Inductance<br>between NU,V,W and DC Link N < 10nH<br>(Note 8)||1.0|−|−|�s|
|PWIN (OFF)||||2.0|−|−||
|Package Mounting Torque||M3 Type Screw||0.6|0.7|0.9|Nm|



Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 

Flatness tolerance of the heatsink should be within −50 � m to +100 � m. 

7. Allowable output current value is the reference data for the safe operation of this product. This may be different from the actual application and operating condition. 

8. Product might not make response if input pulse width is less than the recommended value. 

## **TIME CHARTS OF PROTECTIVE FUNCTION** 

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Input Signal<br>Protection<br>Circuit State Reset Set Reset<br>a6<br>UVDDR<br>Control Supply a1 UVDDD<br>a3<br>Voltate<br>a2 a4 a7<br>Output Current<br>a5<br>Fault Output Signal<br>**----- End of picture text -----**<br>


- a1 : Control supply voltage rises: After the voltage rises UVDDR, the circuits start to operate when next input is applied. a2 : Normal operation: IGBT ON and carrying current. 

> a3 : Under voltage detection (UVDDD). 

> a4 : IGBT OFF in spite of control input condition. 

> a5 : Fault output operation starts with a fixed pulse width. 

> a6 : Under voltage reset (UVDDR). 

- a7 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH. 

**Figure 7. Under−Voltage Protection (Low−Side)** 

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**NFAM3512L7B** 

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Input Signal<br>Protection Set<br>Circuit State Reset Reset<br>UVBSR b5<br>Control Supply b1 UVBSD<br>Voltate b3<br>b2 b4 b6<br>Output Current<br>Fault Output Signal<br>High−level (No fault output)<br>**----- End of picture text -----**<br>


- b1 : Control supply voltage rises: After the voltage reaches UVBSR, the circuits start to operate when next input is applied. b2 : Normal operation: IGBT ON and carrying current. b3 : Under voltage detection (UVBSD). b4 : IGBT OFF in spite of control input condition, but there is no fault output signal. b5 : Under voltage reset (UVBSR). b6 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH. 

**Figure 8. Under−Voltage Protection (High−Side)** 

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c6<br>c7<br>Input Signal<br>Protection Set Reset<br>Circuit State<br>c4<br>Internal IGBT c3<br>Gate −Emitter Voltage<br>SC current c2 Internal delay<br>trip level at protection circuit c8<br>c1<br>Output Current<br>SC reference<br>Sensing Voltage of voltage<br>Sense Resistor<br>RC filter circuit time<br>c5 constant delay<br>Fault Output Signal<br>**----- End of picture text -----**<br>


(with the external sense resistance and RC filter connection) 

- c1 : Normal operation: IGBT ON and carrying current. 

- c2 : Short circuit current detection (SC trigger). 

- c3 : All low−side IGBT’s gate are hard interrupted. c4 : All low−side IGBTs turn OFF. 

- c5 : Fault output operation starts with a fixed pulse width. 

- c6 : Input HIGH: IGBT ON state, but during the active period of fault output the IGBT doesn’t turn ON. c7 : Fault output operation finishes, but IGBT doesn’t turn on until triggering next signal from LOW to HIGH. c8 : Normal operation: IGBT ON and carrying current. 

## **Figure 9. Short−Circuit Current Protection (Low−Side Operation only)** 

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**NFAM3512L7B** 

## **TYPICAL APPLICATION CIRCUIT** 

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#15 (1) VS(U)<br>#13 (3) VB(U) P (37)<br>VDD Line #16 (4) VDD(UH) VDD VB<br>(6) HIN(U) HIN HO<br>#15 (7) VS(V) VSS VS U (36)<br>#13 (9) VB(V)<br>VDD Line #16 (10) VDD(VH) VDD VB #12<br>#9 (12) HIN(V) HIN HO<br>#15 (13) VS(W) VSS VS V (35) AC motor3−phase<br>#13 (15) VB(W)<br>VDD Line #16 (16) VDD(WH) VDD VB<br>(18) HIN(W) HIN HO<br>W (34)<br>MCU VSS VS<br>Input Signal<br>Temperature sensing<br>(20) VTS<br>VTS<br>(21) LIN(U) LO #10<br>LIN(U)<br>#9 (22) LIN(V) LIN(V) NU (33)<br>(23) LIN(W)<br>LIN(W)<br>(24) VFO<br>VFO<br>5 V line #17 (25) CFOD LO<br>Protection Signal #18 (26) CIN CFODCIN NV (32)<br>(27) VSS VSS<br>VDD Line (28) VDD VDD<br>LO<br>#13 #14 #16<br>NW (31)<br>U−phase current sensing<br>Protection Signal V−phase current sensing<br>W−phase current sensing<br>#11<br>**----- End of picture text -----**<br>


To avoid malfunction, the wiring of each input should be as short as possible (less than 2−3 cm). Each capacitor should be mounted as close to the pins of the product as possible. VFO output is open−drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor that makes IFO up to 1 mA. Please refer to Figure 5. 

## NOTES: 

9. Input signal is active−HIGH type. There is a 5 k � resistor inside the IC to pull−down each input signal line to GND. RC coupling circuits should be adopted for the prevention of input signal oscillation. RC time constant should be selected in the range 50 ~ 150 ns. (Recommended R = 100 � , C = 1 nF) 

- 10.Each wiring pattern inductance should be minimized (Recommend less than 10 nH). Use the shunt resistor of surface mounted (SMD) type to reduce wiring inductance. To prevent malfunction, wiring should be connected to the terminal of the shunt resistor as close as possible. 

- 11. In the short−circuit protection circuit, please select the RC time constant in the range 1.5 ~ 2 � s. Do enough evaluation on the real system because short−circuit protection time may vary wiring pattern layout and value of the RC time constant. 

- 12.To prevent surge destruction, the wiring between the snubber capacitor and the P & GND pins should be as short as possible. The use of a high−frequency non−inductive capacitor of around 0.1 ~ 0.22 � F between the P & GND pins is recommended. 

- 13.The zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each pair of control supply terminals (Recommended zener diode is 22 V / 1 W, which has the lower zener impedance characteristic than about 15 � ). 

- 14.VDD electrolytic capacitor is recommended around 7 times larger than VBS electrolytic bootstrap capacitor. 

15.Please choose the VBS electrolytic bootstrap capacitor with good temperature characteristic. 

- 16.0.1 ~ 0.2 � F R−category ceramic capacitors with good temperature and frequency characteristics is recommended. 

- 17.Fault out pulse width can be adjusted by capacitor connected to the CFOD terminal. 

- 18.To prevent protection function errors, CIN capacitor should be placed as close to CIN and VSS pins as possible. 

## **Figure 10. Typical Application Circuit** 

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**11** 

**NFAM3512L7B** 

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70<br>VDD = 13 V<br>60 VDD = 15 V<br>VDD = 20 V<br>50<br>40<br>30<br>20<br>10<br>0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5<br>Vce(sat), Collector−Emitter Voltage [V]<br>Figure 11. Typ. Collector–Emitter saturation<br>voltage<br>70<br>Tj = 25 ° C<br>60 Tj = 150 ° C<br>50<br>40<br>30<br>20<br>10<br>0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5<br>VF, Emitter−Collector Voltage [V]<br>Figure 13. Typ. Emitter–Collector Forward<br>Voltage<br>6<br>High side, Tj = 25 ° C<br>5 High side, Tj = 150 ° C<br>Low side, Tj = 25 ° C<br>4 Low side, Tj = 150 ° C<br>3<br>2<br>1<br>VPN = 600 V<br>VDD = 15 V<br>0<br>0 10 20 30 40 50 60 70<br>Ic, Collector Current [A]<br>Ic, Collector−Emitter Current [A]<br>IF, Emitter−Collector Current [A]<br>Loss [mJ]<br>Eoff, Turn−off Switching Energy<br>**----- End of picture text -----**<br>


**Figure 15. Typ. Turn−off Switching Energy Loss** 

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70<br>Tj = 25 ° C<br>60 Tj = 150 ° C<br>50<br>40<br>30<br>20<br>10<br>VDD = 15 V<br>0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5<br>Vce(sat), Collector−Emitter Voltage [V]<br>Ic, Collector−Emitter Current [A]<br>**----- End of picture text -----**<br>


**Figure 12. Typ. Collector–Emitter Saturation Voltage** 

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16<br>15 High side, Tj = 25 ° C<br>14 High side, Tj = 150 ° C<br>13 °<br>Low side, Tj = 25 C<br>1211 Low side, Tj = 150 ° C<br>10<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2 VPN = 600 V<br>1 VDD = 15 V<br>0<br>0 10 20 30 40 50 60 70<br>Ic, Collector Current [A]<br>Figure 14.  Typ. Turn−on Switching Energy<br>Loss<br>3000 High side, Tj = 25 ° C<br>2700 High side, Tj = 150 ° C<br>Low side, Tj = 25 ° C<br>2400 Low side, Tj = 150 ° C<br>2100<br>1800<br>1500<br>1200<br>900<br>600<br>VPN = 600 V<br>300 VDD = 15 V<br>0<br>0 10 20 30 40 50 60 70<br>Ic, Collector Current [A]<br>Loss [mJ]<br>Eon, Turn−on Switching Energy<br>J]<br>�<br> Loss [<br>Erec, Reverse Recovery Energy<br>**----- End of picture text -----**<br>


**Figure 16. Typ. Reverse Recovery Energy Loss** 

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**12** 

**NFAM3512L7B** 

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**----- Start of picture text -----**<br>
1800<br>High side, Tj = 25 ° C<br>1700 High side, Tj = 150 ° C<br>1600 Low side, Tj = 25 ° C<br>Low side, Tj = 150 ° C<br>1500<br>1400<br>1300<br>1200<br>1100<br>1000<br>VPN = 600 V<br>900<br>VDD = 15 V<br>800<br>0 10 20 30 40 50 60 70<br>Ic, Collector Current [A]<br>Figure 17. Typ. Turn−on Propagation Delay<br>Time<br>2500<br>High side, Tj = 25 ° C<br>2400 High side, Tj = 150 ° C<br>2300 Low side, Tj = 25 ° C<br>2200 Low side, Tj = 150 ° C<br>2100<br>2000<br>1900<br>1800<br>1700<br>VPN = 600 V<br>1600<br>VDD = 15 V<br>1400<br>0 10 20 30 40 50 60 70<br>Ic, Collector Current [A]<br>Time [ns]<br>ton, Turn−on Propagation Delay<br>Time [ns]<br>Toff, Turn−off Propagation Delay<br>**----- End of picture text -----**<br>


**Figure 19. Typ. Turn off Propagation Delay Time** 

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800<br>700 High side, Tj = 25High side, Tj = 150 ° C ° C<br>600 Low side, Tj = 25 ° C<br>Low side, Tj = 150 ° C<br>500<br>400<br>300<br>200<br>100 VPN = 600 V<br>VDD = 15 V<br>0<br>0 10 20 30 40 50 60 70<br>Ic, Collector Current [A]<br>trr, Reverse Recovery Time [ns]<br>**----- End of picture text -----**<br>


**Figure 21. Typ. Reverse Recovery Time** 

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**----- Start of picture text -----**<br>
600 High side, Tj = 25 ° C<br>High side, Tj = 150 ° C<br>500 Low side, Tj = 25 ° C<br>Low side, Tj = 150 ° C<br>400<br>300<br>200<br>100<br>VPN = 600 V<br>VDD = 15 V<br>0<br>0 10 20 30 40 50 60 70<br>Ic, Collector Current [A]<br>Figure 18. Turn−on Switching Time<br>900<br>High side, Tj = 25 ° C<br>800 High side, Tj = 150 ° C<br>Low side, Tj = 25 ° C<br>700 Low side, Tj = 150 ° C<br>600<br>500<br>400<br>300<br>VPN = 600 V<br>200<br>VDD = 15 V<br>100<br>0 10 20 30 40 50 60 70<br>Ic, Collector Current [A]<br>Figure 20. Typ. Turn off Switching Time<br>0.8<br>0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>0.1<br>0<br>1,E−06 1,E−05 1,E−04 1,E−03 1,E−02 1,E−01 1,E+00<br>tp, Pulse Width [s]<br>tc(on), Turn−on Switching Time [ns]<br>tc(of), Turn−on Switching Time [ns]<br>Resistance [K/W]<br>ZthJC, IGBT Transient Thermal<br>**----- End of picture text -----**<br>


**Figure 22. IGBT Transient Thermal Resistance** 

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**13** 

**NFAM3512L7B** 

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1.1<br>1 ee ee ee ee ee<br>0.9 ee ee eeee<br>0.8 ee ee ee ee<br>0.7 ee ee ee eeee<br>0.6 ee ee ee ee<br>0.5 ee ee ee ee ee<br>0.4 ee eeee<br>0.3 ee ee ee ee<br>0.2 ee ee ee eeeee<br>0.1 a ee ee ee ee<br>0 PpEs<br>1,E−06 1,E−05 1,E−04 1,E−03 1,E−02 1,E−01 1,E+00<br>tp, Pulse Width [s]<br>Resistance [K/W]<br>ZthJC, FRDi Transient Thermal<br>**----- End of picture text -----**<br>


**Figure 23. FRDi Transient Thermal Resistance** 

**TURN−ON/OFF SWITCHING WAVEFORM** 

SWITCHING CONDITION: VDC = 600 V, VDD = 15 V, TJ = 25 ° C, IC = 30 A. 

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VIN [5V/div]<br>VIN [5V/div]<br>Ic [10A/div]<br>VCE [200V/div]<br>Ic [10A/div] VCE [200V/div]<br>Time [0.2us/div] Time [0.2us/div]<br>Sacre Sezai tescs<br>**----- End of picture text -----**<br>


**Figure 24. Turn−on Switching Waveform** 

**Figure 25. Turn−off Switching Waveform** 

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**14** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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DIP39, 54.5x31.0 EP−2<br>CASE MODGX<br>ISSUE O<br>**----- End of picture text -----**<br>


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DATE 02 APR 2019<br>**----- End of picture text -----**<br>


**GENERIC MARKING DIAGRAM*** XXXXXXXXXXXXXXXXX ZZZATYWW XXXXX = Specific Device Code ZZZ      = Assembly Lot Code AT        = Assembly & Test Location Y          = Year WW     = Work Week *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may not follow the Generic Marking. 

## **DOCUMENT NUMBER: 98AON05290H** 

## **DESCRIPTION: DIP39, 54.5x31.0 EP−2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

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