NFAM1012L5B

## Intelligent Power Module (IPM) 1200 V, 10 A 

## _Advance Information_ NFAM1012L5B 

The NFAM1012L5B is a fully−integrated inverter power module consisting of an independent High side gate driver, LVIC, six IGBT’s and a temperature sensor (TSU by LVIC), suitable for driving permanent magnet synchronous (PMSM) motors, brushless DC (BLDC) motors and AC asynchronous motors. The IGBT’s are configured in a three−phase bridge with separate emitter connections for the lower legs for maximum flexibility in the choice of control algorithm. 

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The power stage has under−voltage lockout protection (UVP). Internal boost diodes are provided for high side gate boost drive. 

## **Features** 

- Three−phase 1200 V, 10 A IGBT Module with Independent Drivers 

- Active Logic Interface 

**CASE MODGX DIP39, 54.5x31.0 EP−2** 

- Built−in Under−voltage Protection (UVP) 

- Integrated Bootstrap Diodes and Resistors 

## **MARKING DIAGRAM** 

- Separate Low−side IGBT Emitter Connections for Individual Current Sensing of Each Phase 

- Temperature Sensor (TSU Output by LVIC) 

- UL Certification: E339285 

- This is a Pb−Free Device 

NFAM1012L5B ZZZATYWW 

## **Typical Application** 

- Industrial Drives 

- Industrial Pumps 

- Industrial Fans 

- Industrial Automation 

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P U V W<br>VS(U)<br>VDD(UH)VB(U) High SideHVIC1 HS1<br>HIN(U)<br>VS(V)<br>VDD(VH)VB(V) High SideHVIC2 HS2 HS1 HS2 HS3<br>HIN(V)<br>VS(W)<br>VDD(WH)VB(W) p e High SideHVIC3 HS3 a kG<br>HIN(W)<br>VTS LS1 LS2 LS3<br>LIN(U)<br>LIN(V) Low Side LS1<br>LIN(W) LVIC<br>VFO with LS2<br>CFOD Protection<br>CIN LS3<br>VSS<br>VDD(L)<br>NU NV NW<br>**----- End of picture text -----**<br>


NFAM1012L5B = Specific Device Code ZZZ = Assembly Lot Code A = Assembly Location T = Test Location Y = Year WW = Work Week Device marking is on package top side 

## **ORDERING INFORMATION** 

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Shipping [†]<br>Device Package (Qty / Packing)<br>NFAM1012L5B DIP39, 31.0x54.5 90 / BOX<br>(Pb−Free)<br>**----- End of picture text -----**<br>


**Figure 1. Application Schematic** 

This document contains information on a new product. Specifications and information herein are subject to change without notice. 

Publication Order Number: **NFAM1012L5B/D** 

**1** 

© Semiconductor Components Industries, LLC, 2019 **December, 2019 − Rev. P0** 

**NFAM1012L5B** 

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VB(U) (3)<br>N.C (38)<br>VS(U) (1) P (37)<br>CS + C1<br>HIN (U) (6) VB<br>HIN HOUT<br>VDD(UH) (4) HVIC 1<br>VDD<br>U (36)<br>VSS VS<br>VB(V) (9)<br>VS(V) (7)<br>HIN (V) (12) VB<br>HIN HOUT<br>VDD(VH) (10) VDD HVIC 2 V (35)<br>VSS VS Motor<br>VB(W) (15)<br>VS(W) (13)<br>MCU HIN (W) (18) VB<br>HIN HOUT<br>VDD(WH) (16) HVIC 3<br>VDD W (34)<br>VSS VS<br>VTS (20)<br>VTS<br>LIN(U) (21) OUT(U)<br>LIN(U)<br>LIN(V) (22) NU (33)<br>LIN(V)<br>LIN(W) (23)<br>LIN(W)<br>5V line<br>LVIC<br>VFO (24)<br>VFO OUT(V)<br>CFOD (25)<br>CFOD NV (32)<br>CIN (26) CIN<br>15V line<br>VDD(L) (28) VDD<br>VSS (27) VSS OUT(W)<br>NW (31)<br>Signal for short circuit trip<br>Phase current<br>**----- End of picture text -----**<br>


**Figure 2. Application Schematic − Adjustable Option** 

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**2** 

**NFAM1012L5B** 

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N.C (38)<br>VS(U) (1)<br>P (37)<br>VB(U) (3)<br>VB<br>VDD(UH) (4) VDD HOUT<br>HVIC 1<br>HIN(U) (6) HIN<br>VSS VS U (36)<br>VS(V) (7)<br>VB(V) (9)<br>VB<br>VDD(VH) (10) VDD HOUT<br>HVIC 2<br>HIN(V) (12) HIN<br>VSS VS V (35)<br>VS(W) (13)<br>VB(W) (15)<br>VB<br>VDD(WH) (16) VDD HOUT<br>HVIC 3<br>HIN(W) (18) HIN<br>VSS VS W (34)<br>OUT(U)<br>VTS (20) VTS<br>LIN(U) (21) LIN(U)<br>NU (33)<br>LIN(V) (22) LIN(V)<br>LIN(W) (23) LIN(W)<br>VFO (24) VFO LVIC OUT(V)<br>CFOD (25) CFOD<br>NV (32)<br>CIN (26) CIN<br>VSS (27) VSS<br>VDD(L) (28) VDD OUT(W)<br>NW (31)<br>**----- End of picture text -----**<br>


**Figure 3. Equivalent Block Diagram** 

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**3** 

**NFAM1012L5B** 

## **Table 1. PIN FUNCTION DESCRIPTION** 

|**Pin**|**Name**|**Description**|
|---|---|---|
|1|VS(U)|High−Side Bias Voltage GND for U Phase IGBT Driving|
|(2)|−|Dummy|
|3|VB(U)|High−Side Bias Voltage for U Phase IGBT Driving|
|4|VDD(UH)|High−Side Bias Voltage for U Phase IC|
|(5)|−|Dummy|
|6|HIN(U)|Signal Input for High−Side U Phase|
|7|VS(V)|High−Side Bias Voltage GND for V Phase IGBT Driving|
|(8)|−|Dummy|
|9|VB(V)|High−Side Bias Voltage for V Phase IGBT Driving|
|10|VDD(VH)|High−Side Bias Voltage for V Phase IC|
|(11)|−|Dummy|
|12|HIN(V)|Signal Input for High−Side V Phase|
|13|VS(W)|High−Side Bias Voltage GND for W Phase IGBT Driving|
|(14)|−|Dummy|
|15|VB(W)|High−Side Bias Voltage for W Phase IGBT Driving|
|16|VDD(WH)|High−Side Bias Voltage for W Phase IC|
|(17)|−|Dummy|
|18|HIN(W)|Signal Input for High−Side W Phase|
|(19)|−|Dummy|
|20|VTS|Voltage Output for LVIC Temperature Sensing Unit|
|21|LIN(U)|Signal Input for Low−Side U Phase|
|22|LIN(V)|Signal Input for Low−Side V Phase|
|23|LIN(W)|Signal Input for Low−Side W Phase|
|24|VFO|Fault Output|
|25|CFOD|Capacitor for Fault Output Duration Selection|
|26|CIN|Input for Current Protection|
|27|VSS|Low−Side Common Supply Ground|
|28|VDD(L)|Low−Side Bias Voltage for IC and IGBTs Driving|
|(29)|−|Dummy|
|(30)|−|Dummy|
|31|NW|Negative DC−Link Input for U Phase|
|32|NV|Negative DC−Link Input for V Phase|
|33|NU|Negative DC−Link Input for W Phase|
|34|W|Output for U Phase|
|35|V|Output for V Phase|
|36|U|Output for W Phase|
|37|P|Positive DC−Link Input|
|38|N.C|No Connection|
|(39)|−|Dummy|



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**4** 

**NFAM1012L5B** 

**Table 2. ABSOLUTE MAXIMUM RATINGS** TC = 25 ° C (Notes 1) 

|**Table 2. ABSOLUTE MAXIMUM R**|**ATINGS**TC= 25°C|(Notes 1)|||
|---|---|---|---|---|
|**Rating**|**Symbol**|**Conditions**|**Value**|**Unit**|
|Supply Voltage|VPN|P − NU, NV, NW|900|V|
|Supply Voltage (Surge)|VPN(Surge)|P − NU, NV, NW, (Note 2)|1000|V|
|Self Protection Supply Voltage Limit<br>(Short−Circuit Protection Capability|VPN(PROT)|VDD = VBS = 13.5 V ~ 16.5 V,<br>Tj = 150°C, Vces < 1200 V,<br>Non−Repetitive, < 2�s|800|V|
|Collector−Emitter Voltage|Vces||1200|V|
|Maximum Repetitive Revers Voltage|VRRM||1200|V|
|Each IGBT Collector Current|±Ic||±10|A|
|Each IGBT Collector Current (Peak)|±Icp|Under 1 ms Pulse Width|±20|A|
|Control Supply Voltage High−Side<br>Control Bias Voltage|VDD|VDD(UH, VH, WH), VDD(L) − VSS|−0.3 to 20|V|
||VBS|VB(U) − VS(U), VB(V) − VS(V),<br>VB(W) − VS(W)|−0.3 to 20|V|
|Input Signal Voltage|VIN|HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),<br>LIN(W) − VSS|−0.3 to VDD|V|
|Fault Output Supply Voltage|VFO|VFO − VSS|−0.3 to VDD|V|
|Fault Output Current|IFO|Sink Current at VFO pin|2|mA|
|Current Sensing Input Voltage|VCIN|CIN − VSS|−0.3 to VDD|V|
|Corrector Dissipation|Pc|Per One Chip|83|W|
|Operating Junction Temperature|Ti||−40 to +150|°C|
|Storage Temperature|Tstg||−40 to +125|°C|
|Module Case Operation Temperature|Tc||−40 to +125|°C|
|Isolation Voltage|Viso|60 Hz, Sinusoidal, AC 1 minute, Connec-<br>tion Pins to Heat Sink Plate|2500|V rms|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 

2. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal. 

**Table 3. THERMAL CHARACTERISTICS** 

|**Rating**|**Symbol**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Junction to Case Thermal<br>Resistance|Rth(j−c)Q|Inverter IGBT Part  (per 1/6 Module)|−|−|1.5|°C/W|
||Rth(j−c)F|Inverter FRD Part  (per 1/6 Module)|−|−|1.8|°C/W|



3. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 

**Table 4. RECOMMENDED OPERATING RANGES** (Note 4) 

|**Rating**|**Symbol**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Supply Voltage|VPN|P − NU, NV, NW|−|600|800|V|
|Gate Driver Supply Voltages|VDD|VDD(UH, VH, WH), VDD(L) − VSS|13.5|15|16.5|V|
||VBS|VB(U) − VS(U), VB(V) − VS(V),<br>VB(W) − VS(W)|13.0|15|18.5|V|
|Supply Voltage Variation|dVDD / dt<br>dVBS / dt||−1|−|1|V/�s|
|PWM Frequency|fPWM||1||20|kHz|
|Dead Time|DT|Turn−off to Turn−on (external)|3|−|−|�s|



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**5** 

**NFAM1012L5B** 

**Table 4. RECOMMENDED OPERATING RANGES** (Note 4) (continued) 

|**Rating**|**Symbol**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|Allowable r.m.s. Current|Io|VPN =  600 V,<br>VDD = VBS = 15 V,<br>P.F. = 0.8,<br>Tc≤125°C, Tj≤150°C,<br>(Note 5)|fPWM=<br>5 kHz|−|−|11.2|A rms|
||||fPWM=<br>15 kHz|−|−|6.3||
|Allowable Input Pulse Width|PWIN (on)|400 V≤VPN≤800 V,<br>13.5 V≤VDD≤16.5 V,<br>13.0 V≤VBS≤18.5 V,<br>−40°C≤Tc≤150°C||2.0<br>2.5|−|−|�s|
||PWIN (off)||||−|−||
|Package Mounting Torque||M3 Type Screw||0.6|0.7|0.9|Nm|



Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4. Allowable r.m.s Current depends on the actual conditions. 5. Flatness tolerance of the heatsink should be within −50 � m to +100 � m. 

**Table 5. ELECTRICAL CHARACTERISTICS** (Tc = 25 ° C, VD = 15 V, unless otherwise noted) (Note 6) 

|**Parameter**|**Parameter**|**Test Conditions**|**Test Conditions**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|**INVERTER SECTION**|||||||||
|Collector−Emitter Leakage<br>Current||Vce = Vces, Tj = 25°C||Ices|−|−|1|mA|
|||Vce = Vces, Tj = 150°C|||−|−|10|mA|
|Collector−Emitter Saturation<br>Voltage||VDD = VBS = 15 V, IN = 5 V<br>Ic = 10 A, Tj = 25°C||VCE(sat)|−|1.85|2.5|V|
|||VDD = VBS = 15 V, IN = 5 V<br>Ic = 10 A, Tj = 150°C|||−|2.0||V|
|FWDi Forward Voltage||IN = 0 V, If = 10 A, Tj = 25°C||VF|−|1.80|2.6|V|
|||IN = 0 V, If = 10 A, Tj = 150°C|||−|1.70||V|
|High Side|Switching Times|VPN = 600 V, VDD(H) = VDD(L) = 15 V<br>Ic = 10 A, Tj = 25°C, IN = 0⇔5 V<br>Inductive Load||ton|0.80|1.40|2.00|�s|
|||||tc (on)|−|0.30|0.60|�s|
|||||toff|−|1.70|2.50|�s|
|||||tc (off)|−|0.20|0.60|�s|
|||||trr|−|0.40|−|�s|
|Low Side|Switching Times|VPN = 600 V, VDD(H) = VDD(L) = 15 V<br>Ic = 10 A, Tj = 25°C, IN = 0⇔5 V<br>Inductive Load||ton|0.90|1.50|2.10|�s|
|||||tc (on)|−|0.30|0.60|�s|
|||||toff|−|1.70|2.50|�s|
|||||tc (off)|−|0.20|0.60|�s|
|||||trr|−|0.40|−|�s|
|**DRIVER SECTION**|||||||||
|Quiescent VDD Supply Current||VDD(UH,VH,WH) = 15 V,<br>HIN(U,V,W) = 0 V|VDD(UH) − VSS<br>VDD(VH) − VSS<br>VDD(WH) − VSS|IQDDH|−|−|0.30|mA|
|||VDD(L) = 15 V,<br>LIN(U, V, W) = 0 V|VDD(L) − VSS|IQDDL|−|−|3.50|mA|
|Operating VDD Supply Current||VDD(UH, VH, WH) = 15 V,<br>fPWM= 20 kHz, Duty = 50%,<br>Applied to one PWM Signal Input<br>for High−Side|VDD(UH) − VSS<br>VDD(VH) − VSS<br>VDD(WH) − VSS|IPDDH|−|−|0.40|mA|
|||VDD(L) = 15 V,<br>fPWM= 20 kHz, Duty = 50%,<br>Applied to one PWM Signal Input<br>for Low−Side|VDD(L) − VSS|IPDDL|−|−|7.00|mA|



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**6** 

**NFAM1012L5B** 

**Table 5. ELECTRICAL CHARACTERISTICS** (Tc = 25 ° C, VD = 15 V, unless otherwise noted) (Note 6) (continued) 

|**Parameter**|**Test Conditions**|**Test Conditions**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**DRIVER SECTION**||||||||
|Quiescent VBS Supply Current|VBS = 15 V<br>HIN(U, V, W) = 0 V|VB(U) − VS(U)<br>VB(V) − VS(V)<br>VB(W) − VS(W)|IQBS|−|−|0.30|mA|
|Operating VBS Supply Current|VDD = VBS = 15 V,<br>fPWM= 20 kHz, Duty = 50%,<br>Applied to one PWM Signal Input<br>for High−Side|VB(U) − VS(U)<br>VB(V) − VS(V)<br>VB(W) − VS(W)|IPBS|−|−|6.00|mA|
|ON Threshold Voltage|HIN(U, V, W) − VSS, LIN(U, V, W) − VSS||VIN(ON)|||2.6|V|
|OFF Threshold Voltage|||VIN(OF)|0.8|||V|
|Short Circuit Trip Level|VDD = 15 V, CIN−VSS||VCIN(ref)|0.46|0.48|0.50|V|
|Supply Circuit Under−Voltage<br>Protection|Detection Level||UVDDD|10.3||12.5|V|
||Reset Level||UVDDR|10.8||13.0|V|
||Detection Level||UVBSD|10.0||12.0|V|
||Reset Level||UVBSR|10.5||12.5|V|
|Voltage Output for LVIC<br>Temperature Sensing Unit|VTS−VSS = 10 nF, Temp. = 25°C||VTS|(0.905)|(1.030)|(1.155)|V|
|Fault Output Voltage|VDD = 0 V, CIN = 0 V,<br>VFO Circuit: 10 k�to 5 V Pull−up||VFOH|4.9|−|−|V|
||VDD = 0 V, CIN = 1 V,<br>VFO Circuit: 10 k�to 5 V Pull−up||VFOL|−|−|0.95|V|
|Fault−Output Pulse Width|CFOD = 22 nF||tFOD|1.6|2.4|−|ms|
|**BOOTSTRAP SECTION**||||||||
|Bootstrap Diode Forward Current|If = 0.1 A||VF|3.4|4.6|5.8|V|
|Built−in Limiting Resistance|||RBOOT|30|38|46|�|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

6. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25 � C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 

7. The fault−out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation: tFOD = (TBD) x 10[6] x CFOD (s) 

8. Values based on design and/or characterization. 

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4.0<br>3.5<br>3.0<br>2.5<br>2.0<br>1.5<br>1.0<br>40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130<br>LVIC Temperature ( ° C)<br>VTS Output Voltage (V)<br>**----- End of picture text -----**<br>


**Figure 4. Temperature of LVIC versus VOT Characteristics** 

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**7** 

**NFAM1012L5B** 

## **PACKAGE DIMENSIONS** 

**DIP39, 54.5x31.0 EP−2** CASE MODGX ISSUE O 

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**NFAM1012L5B** 

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