NDS9952A

## **Is Now Part of** 

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February 1996 

## **NDS9952A Dual N & P-Channel Enhancement Mode Field Effect Transistor** 

## **General Description** 

**Features** 

These dual N- and P-channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management  and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. 

N-Channel 3.7A, 30V,  RDS(ON)=0.08Ω @ VGS=10V. P-Channel -2.9A, -30V, RDS(ON)=0.13Ω @ VGS=-10V. 

High density cell design or extremely low RDS(ON). 

- High power and current handling capability in a widely used surface mount package. 

Dual (N & P-Channel) MOSFET in surface mount package. 

## ________________________________________________________________________________ 

**==> picture [110 x 77] intentionally omitted <==**

**----- Start of picture text -----**<br>
5 4<br>6 3<br>7 2<br>8 1<br>**----- End of picture text -----**<br>


|**Absolute Maximum Ratings**<br> TA= 25°C unless otherwise noted|= 25°C unless otherwise noted||
|---|---|---|
|**Parameter**|**N-Channel**|**P-Channel**|
|Drain-Source Voltage|30|-30|
|Gate-Source Voltage|± 20|± 20|
|Drain Current - Continuous(Note 1a)<br>-  Pulsed|± 3.7|± 2.9|
||± 15|± 10|
|Power Dissipation for Dual Operation|2||
|Power Dissipation for Single Operation(Note 1a)<br> (Note 1b)<br> (Note 1c)|1.6||
||1||
||0.9||
|Operating and Storage Temperature Range|-55 to 150||



© 1997 Fairchild Semiconductor Corporation 

NDS9952A.SAM 

**Electrical Characteristics** (TA = 25°C unless otherwise noted) 

|**Electrica**|**l Characteristics **(TA= 25°C unle|ss otherwise noted)|||||||
|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**||**Type**|**Min**|**Typ**|**Max**|**Units**|
|**OFF CHARACTERISTICS**|||||||||
|BVDSS|Drain-Source Breakdown Voltage|V**GS**= 0 V, I**D**= 250 µA||N-Ch|30|||V|
|||V**GS**= 0 V, I**D**= -250 µA||P-Ch|-30|||V|
|IDSS|Zero Gate Voltage  Drain Current|V**DS**= 24 V, V**GS**= 0 V||N-Ch|||2|µA|
||||T**J**= 55°C||||25|µA|
|||V**DS**= -24 V, V**GS**= 0 V||P-Ch|||-2|µA|
||||T**J**= 55°C||||-25|µA|
|IGSSF|Gate - Body Leakage, Forward|V**GS**= 20 V, V**DS**= 0 V||All|||100|nA|
|IGSSR|Gate - Body Leakage, Reverse|V**GS**= -20 V, V**DS**= 0 V||All|||-100|nA|
|**ON CHARACTERISTICS**(Note 2)|||||||||
|VGS(th)|Gate Threshold Voltage|V**DS **= V**GS**,  I**D **=  250 µA||N-Ch|1|1.7|2.8|V|
||||T**J**= 125°C||0.7|1.2|2.2||
|||V**DS **= V**GS**,  I**D **= -250 µA||P-Ch|-1|-1.6|-2.8||
||||T**J**= 125°C||-0.85|-1.25|-2.5||
|RDS(ON)|Static Drain-Source On-Resistance|V**GS**= 10 V,  I**D**= 1.0 A||N-Ch||0.06|0.08|Ω|
||||T**J**= 125°C|||0.08|0.13||
|||V**GS**=  4.5 V,  I**D**=  0.5 A||||0.08|0.11||
||||T**J**= 125°C|||0.11|0.18||
|||V**GS**= -10 V,  I**D**= -1.0  A||P-Ch||0.11|0.13||
||||T**J**= 125°C|||0.15|0.21||
|||V**GS**= -4.5 V,  I**D**= -0.5 A||||0.17|0.2||
||||T**J**= 125°C|||0.24|0.32||
|ID(on)|On-State Drain Current|VGS= 10 V, VDS= 5 V||N-Ch|15|||A|
|||VGS= -10 V, VDS= -5 V||P-Ch|-10||||
|gFS|Forward Transconductance|V**DS**=  15 V, I**D**=  3.7 A||N-Ch||6||S|
|||V**DS**= -15 V, I**D**= -2.9 A||P-Ch||4|||
|**DYNAMIC CHARACTERISTICS**|||||||||
|Ciss|Input Capacitance|N-Channel<br>V**DS**= 10 V,  V**GS**= 0 V,<br>f  = 1.0 MHz<br>P-Channel<br>V**DS**= -10 V,  V**GS**= 0 V,<br>f  = 1.0 MHz||N-Ch||320||pF|
|||||P-Ch||350|||
|Coss|Output Capacitance|||N-Ch||225||pF|
|||||P-Ch||260|||
|Crss|Reverse Transfer Capacitance|||N-Ch||85||pF|
|||||P-Ch||100|||



NDS9952A.SAM 

|**Electrical Characteristics **(TA= 25°C unless otherwise noted)|**Electrical Characteristics **(TA= 25°C unless otherwise noted)|**Electrical Characteristics **(TA= 25°C unless otherwise noted)||||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Type**|**Min**|**Typ**|**Max**|**Units**|
|**SWITCHING  CHARACTERISTICS** (Note 2)||||||||
|tD(on)|Turn - On Delay Time|N-Channel|N-Ch||10|15|ns|
|||VDD= 10 V,  ID=  1 A,|P-Ch||9|40||
|tr|Turn - On Rise Time|VGEN= 10 V, RGEN= 6Ω|N-Ch||13|20|ns|
|||P-Channel|P-Ch||21|40||
|tD(off)|Turn - Off Delay Time|VDD= -10 V,  ID= -1 A,<br>VGEN= -10 V, RGEN= 6Ω|N-Ch||21|50|ns|
||||P-Ch||21|90||
|tf|Turn - Off Fall Time||N-Ch||5|50|ns|
||||P-Ch||8|50||
|Qg|Total Gate Charge|N-Channel|N-Ch||9.5|27|nC|
|||VDS=  10 V,<br>ID=   3.7 A,  VGS=  10 V|P-Ch||10|25||
|Qgs|Gate-Source Charge||N-Ch||1.5||nC|
|||P-Channel|P-Ch||1.6|||
|Qgd|Gate-Drain Charge|VDS= -10 V,<br>ID=  -2.9 A,  VGS= -10 V|N-Ch||3.3||nC|
||||P-Ch||3.4|||
|**DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS**||||||||
|IS|Maximum Continuous Drain-Source Diode Forward Current||N-Ch|||1.2|A|
||||P-Ch|||-1.2||
|VSD|Drain-Source Diode Forward|V**GS**= 0 V,  I**S**=  1.25 A (Note 2)|N-Ch||0.8|1.3|V|
||Voltage|V**GS**= 0 V,  I**S**= -1.25 A (Note 2)|P-Ch||-0.8|-1.3||
|trr|Reverse Recovery Time|VGS= 0 V, IF= 1.25 A, dIF/dt = 100 A/µs|N-Ch|||75|ns|
|||VGS= 0 V, IF= -1.25 A, dIF/dt = 100 A/µs|P-Ch|||100||



Notes: 

1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. 

**==> picture [429 x 197] intentionally omitted <==**

**----- Start of picture text -----**<br>
PD ( t ) = RT θ J − J TA ( At ) = R θ JTC + J − RT θ ACA ( t ) =  I D 2 ( t ) ×  RDS ( ON ) TJ<br>Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:<br>a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.<br>b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.<br>c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.<br>1a 1b 1c<br>Scale 1 : 1 on letter size paper<br>**----- End of picture text -----**<br>


2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. 

NDS9952A.SAM 

## **Typical Electrical Characteristics:  N-Channel** 

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**----- Start of picture text -----**<br>
20<br>V    =10VGS  8.0 6.0<br> 5.0<br>15<br> 4.5<br>10  4.0<br> 3.5<br>5<br> 3.0<br>0<br>0 1 2 3<br>V     , DRAIN-SOURCE VOLTAGE (V)DS<br>I    , DRAIN-SOURCE CURRENT (A)D<br>**----- End of picture text -----**<br>


**Figure 1. N-Channel On-Region Characteristics.** 

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**----- Start of picture text -----**<br>
3<br>V    = 3.5VGS<br>2.5<br> 4.0<br>2<br> 4.5<br>1.5  5.0<br> 6.0<br> 8.0<br>1  10<br>0.5<br>0 3 6 9 12 15<br>I    , DRAIN CURRENT (A)D<br>Figure 2. N-Channel On-Resistance Variation with<br>Gate Voltage and Drain Current.<br>DS(on)<br>R           , NORMALIZED<br>DRAIN-SOURCE ON-RESISTANCE<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
1.6 2<br>I   = 3.7AD  V     = 10 V GS<br>1.4 V     = 10V GS<br>1.5 T  = 125°C J<br>1.2<br>1  25°C<br>1<br> -55°C<br>0.8<br>0.6 0.5<br>-50 -25 0 25 50 75 100 125 150 0 3 6 9 12 15<br>T  , JUNCTION TEMPERATURE (°C)J I   , DRAIN CURRENT (A)D<br>Figure 3. N-Channel On-Resistance Variation with Figure 4. N-Channel On-Resistance Variation with<br>Temperature. Drain Current and Temperature.<br>10 1.2<br>V     = 10VDS T  = -55°CJ 125°C<br>1.1 V     DS = V GS<br>8 25°C I    = 250µAD<br>1<br>6<br>0.9<br>4<br>0.8<br>2<br>0.7<br>0 0.6<br>1 2 3 4 5 -50 -25 0 25 50 75 100 125 150<br>V     , GATE TO SOURCE VOLTAGE (V)GS T  , JUNCTION TEMPERATURE (°C)J<br>Figure 5. N-Channel Transfer Figure 6. N-Channel Gate Threshold Variation<br>Characteristics. with Temperature.<br>DS(ON) DS(on)<br>R            , NORMALIZED R           , NORMALIZED<br>DRAIN-SOURCE ON-RESISTANCE DRAIN-SOURCE  ON-RESISTANCE<br>th<br>I   , DRAIN CURRENT (A) V   , NORMALIZED<br>GATE-SOURCE THRESHOLD VOLTAGE<br>D<br>**----- End of picture text -----**<br>


NDS9952A.SAM 

## **Typical Electrical Characteristics: N-Channel (continued)** 

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**----- Start of picture text -----**<br>
1.12 10<br>I    = 250µAD 5 V     = 0VGS<br>1.08<br>0.51 T  J = 125°C<br>1.04 25°C<br> -55°C<br>0.1<br>1<br>0.96 0.01<br>0.92<br>-50 -25 0 25 50 75 100 125 150 0.001<br>T    , JUNCTION TEMPERATURE (°C) J 0.2 0.4V     , BODY DIODE FORWARD VOLTAGE (V)SD 0.6 0.8 1 1.2 1.4<br>Figure 7. N-Channel Breakdown Voltage Variation Figure 8.  N-Channel Body Diode Forward Voltage<br>with Temperature. Variation with Current and Temperature .<br>1000 10<br>800 I   = 3.7AD V     = 10VDS 20V<br>8<br>500<br>C  iss 15V<br>300 6<br>200 C  oss<br>4<br>100 f = 1 MHz 2<br>V     GS = 0V C   rss<br>50 0<br>0.1 0.2 0.5 1 2 5 10 30 0 2 4 6 8 10 12<br>V     , DRAIN TO SOURCE VOLTAGE (V)DS Q    , GATE CHARGE (nC)g<br>Figure 9. N-Channel Capacitance Characteristics. Figure 10. N-Channel Gate Charge Characteristics.<br>10<br>V    =10VDS T  = -55°CJ<br>8<br> 25°C<br>6  125°C<br>4<br>2<br>0<br>0 2 4 6 8 10<br>I   , DRAIN CURRENT (A)D<br>BV        , NORMALIZED<br>DRAIN-SOURCE BREAKDOWN VOLTAGE<br>I   , REVERSE DRAIN CURRENT (A)<br>CAPACITANCE (pF)<br>GS<br>V      , GATE-SOURCE VOLTAGE (V)<br>FS<br>g    , TRANSCONDUCTANCE (SIEMENS)<br>DSS<br>S<br>**----- End of picture text -----**<br>


**Figure 8.  N-Channel Body Diode Forward Voltage Variation with Current and Temperature** . 

**Figure 11. N-Channel Transconductance Variation with Drain Current and Temperature.** 

NDS9952A.SAM 

## **Typical Electrical Characteristics:  P-Channel (continued)** 

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**----- Start of picture text -----**<br>
-20 3<br> V    = -10VGS  -8.0  -7.0  V    = -3.5VGS  -4.0<br>-15  -6.0 2.5  -4.5<br> -5.0<br> -5.5<br> -5.0 2  -5.5<br>-10  -6.0<br> -4.5<br>1.5<br> -7.0<br> -4.0  -8.0<br>-5  -3.5 1 -10<br> -3.0<br>0 0.5<br>0 -1 -2 -3 -4 -5 0 -3 -6 -9 -12 -15<br>V     , DRAIN-SOURCE VOLTAGE (V)DS I    , DRAIN CURRENT (A)D<br>Figure 12. P-Channel On-Region Characteristics. Figure 13. P-Channel On-Resistance Variation with<br>Gate Voltage and Drain Current.<br>1.6 2<br>I   = -2.9AD  V     = -10V GS<br>1.4 V     = -10VGS<br>1.5 T  = 125°CJ<br>1.2<br>1  25°C<br>1<br>0.8   -55°C<br>0.6-50 -25 0 25 50 75 100 125 150 0.5 0 -3 -6 -9 -12 -15<br>T  , JUNCTION TEMPERATURE (°C)J I    , DRAIN CURRENT (A)D<br>Figure 14. P-Channel On-Resistance Variation with Figure 15. P-Channel On-Resistance Variation with<br>Temperature. Drain Current and Temperature.<br>-10 1.2<br>V     = -10VDS T   = -55°CJ 25°C 125°C V    = VDS GS<br>-8 1.1 I    = -250µA D<br>-6 1<br>-4 0.9<br>-2 0.8<br>0 -1 -2 -3 -4 -5 -6 0.7-50 -25 0 25 50 75 100 125 150<br>V     , GATE TO SOURCE VOLTAGE (V)GS T  , JUNCTION TEMPERATURE (°C)J<br>Figure 16. P-Channel Transfer Characteristics. Figure 17. P-Channel Gate Threshold Variation<br>DS(on)<br>R           , NORMALIZED<br>I    , DRAIN-SOURCE CURRENT (A)D DRAIN-SOURCE ON-RESISTANCE<br>DS(ON)<br>R            , NORMALIZED<br>DS(on)<br>R           , NORMALIZED<br>DRAIN-SOURCE ON-RESISTANCE DRAIN-SOURCE ON-RESISTANCE<br>th<br>V    , NORMALIZED<br>I   , DRAIN CURRENT (A)<br>GATE-SOURCE THRESHOLD VOLTAGE<br>D<br>**----- End of picture text -----**<br>


**Figure 13. P-Channel On-Resistance Variation with Gate Voltage and Drain Current.** 

**Figure 17. P-Channel Gate Threshold Variation with Temperature.** 

NDS9952A.SAM 

## **Typical Electrical Characteristics: P-Channel (continued)** 

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**----- Start of picture text -----**<br>
1.1 10<br>I    = -250µAD 5 V     = GS 0V<br>1.08<br>1.06 1<br>1.04 0.5 T  = 125J °C 25°C<br>1.02 0.1 -55°C<br>1<br>0.98<br>0.01<br>0.96<br>0.94<br>-50 -25 0 25 50 75 100 125 150 0.001<br>T    , JUNCTION TEMPERATURE (°C)J 0.2 0.4-V     , BODY DIODE FORWARD VOLTAGE (V)SD 0.6 0.8 1 1.2 1.4<br>BV        , NORMALIZED<br>-I   , REVERSE DRAIN CURRENT (A)<br>DRAIN-SOURCE BREAKDOWN VOLTAGE<br>DSS<br>S<br>**----- End of picture text -----**<br>


**Figure 18. P-Channel Breakdown Voltage Variation with Temperature.** 

**Figure 19.  P-Channel Body Diode Forward Voltage Variation with Current and Temperature** . 

**==> picture [206 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>800<br>500<br>C  iss<br>300<br>200 C   oss<br>100 f = 1 MHz<br>V     = 0V GS C  rss<br>50<br>0.1 0.2 0.5 1 2 5 10 30<br>-V     , DRAIN TO SOURCE VOLTAGE (V)DS<br>CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 20. P-Channel Capacitance Characteristics.** 

**==> picture [207 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>I    = -2.9AD V     = -10VDS -20V<br>8<br>-15V<br>6<br>4<br>2<br>0<br>0 2 4 6 8 10 12<br>Q    , GATE CHARGE (nC)g<br>GS<br>-V      , GATE-SOURCE VOLTAGE (V)<br>**----- End of picture text -----**<br>


**Figure 21. P-Channel Gate Charge Characteristics.** 

**==> picture [207 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>V     = -15VDS T   = -55°CJ<br>5<br> 25°C<br>4<br> 125°C<br>3<br>2<br>1<br>0<br>0 -2 -4 -6 -8 -10<br>I     , DRAIN CURRENT (A)D<br>g      , TRANSCONDUCTANCE (SIEMENS)<br>FS<br>**----- End of picture text -----**<br>


**Figure 22. P-Channel Transconductance Variation with Drain Current and Temperature.** 

NDS9952A.SAM 

## **Typical Thermal Characteristics: N & P-Channel** 

**==> picture [441 x 530] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.5 5<br> Total Power for Dual Operation<br>2 4<br>1a<br>1a<br>1.5  Power for Single Operation  3 1b<br>1c<br>1 1c1b 2 4.5"x5" FR-4 Board<br>4.5"x5" FR-4 BoardT   = 25  CA o T   = 25  CStill AirA o<br>0.5 Still Air 1 V    = 10VGS<br>0 0.2 0.4 0.6 0.8 1 0 0.1 0.2 0.3 0.4 0.5<br>2oz COPPER MOUNTING PAD AREA (in   )2 2oz COPPER MOUNTING PAD AREA (in   )2<br>Figure 23. SO-8 Dual Package Maximum Figure 24. N-Ch Maximum Steady- State<br>Steady-State Power Dissipation versus Drain Current versus Copper Mounting<br>Copper Mounting Pad Area. Pad Area.<br>5 30<br>10<br>4 3<br>1<br>3 1a<br>0.3<br>V     = 10V GS<br>1b 0.1 SINGLE PULSE<br>2 1c 4.5"x5" FR-4 Board R      = See Note 1c<br>T   = 25  CStill AirA o 0.03 θ [JA] T    = 25°CA<br>1 0 0.1 0.2 0.3 V    = -10VGS 0.4 0.5 0.010.1 0.2 0.5 1 2 5 10 30 50<br>2oz COPPER MOUNTING PAD AREA (in   )2  V     , DRAIN-SOURCE VOLTAGE (V)DS<br>Figure 25. P-Ch Maximum Steady- State Figure 26.  N-Channel Maximum Safe Operating<br>Drain Current versus Copper Mounting Area.<br>Pad Area.<br>30<br>10<br>3<br>1<br>0.3<br>0.1 V     = -10VGS<br>SINGLE PULSE<br>R      = See Note 1c<br>0.03 θ [JA] T    = 25A ° C<br>0.01<br>0.1 0.2 0.5 1 2 5 10 30 50<br>- V     , DRAIN-SOURCE VOLTAGE (V)DS<br>10ms<br>100ms<br> 100us<br> 1 m s<br>10ms<br>100ms<br> 1s<br>10s<br> DC<br> 1s<br>100us<br>1ms<br>10s<br> DC<br>RDS(ON) LIMIT<br>RDS(ON) LIMIT<br>I   , STEADY-STATE DRAIN CURRENT (A)D<br>STEADY-STATE POWER DISSIPATION (W)<br>I   , DRAIN CURRENT (A)D<br>I   , STEADY-STATE DRAIN CURRENT (A)D<br>D<br>-I   , DRAIN CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 27.  P-Channel Maximum Safe Operating Area.** 

NDS9952A.SAM 

## **Typical Thermal Characteristics: N & P-Channel** 

**==> picture [410 x 127] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>0 .5  D = 0.5<br>0 .2   0.2   R       (t) = r(t)  *  R          θ [JA] θ [JA]<br>0 .1  0.1     R        = See Note 1c θ [JA]<br>0 .05  0.05<br> 0.02  P(pk)<br>0 .02<br> 0.01<br>0 .01  Single Pulse   t  1  t   2<br>0 .005 T  J - T    A = P  * R       (t)θ [JA]<br>0 .002 Duty Cycle, D = t   / t 1 2<br>0 .001<br>0 .0001 0 .001 0 .01 0 .1 1 10 100 300<br>t  , TIME (sec)1<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


## **Figure 28. Transient Thermal Response Curve** . 

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design. 

**==> picture [423 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD t o n toff<br>t d(on) t r t d(off) t f<br>VIN R L 90% 90%<br>D V OUT<br>V<br>OUT<br>VGS 10% 10%<br>R<br>GEN G DUT 90%<br>V IN 50% 50%<br>S<br>10%<br> PULSE WIDTH<br>**----- End of picture text -----**<br>


**Figure 29. N or P-Channel Switching Test Circuit** . 

**Figure 30. N or P-Channel Switching Waveforms** . 

NDS9952A.SAM 

## **TRADEMARKS** 

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 

|ACEx™|HiSeC™|SuperSOT™-8|
|---|---|---|
|Bottomless™|ISOPLANAR™|SyncFET™|
|CoolFET™|MICROWIRE™|TinyLogic™|
|CROSSVOLT™|POP™|UHC™|
|E2CMOSTM|PowerTrench<br>|VCX™|
|FACT™|QFET™||
|FACT Quiet Series™|QS™||
|FAST<br>|Quiet Series™||
|FASTr™|SuperSOT™-3||
|GTO™|SuperSOT™-6||



## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 

## **LIFE SUPPORT POLICY** 

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 

1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. 

## **PRODUCT STATUS DEFINITIONS** 

**Definition of Terms** 

|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative or<br>In Design|This datasheet contains the design specifications for<br>product development. Specifications may change in<br>any manner without notice.|
|Preliminary|First Production|This datasheet contains preliminary data, and<br>supplementary data will be published at a later date.<br>Fairchild Semiconductor reserves the right to make<br>changes at any time without notice in order to improve<br>design.|
|No Identification Needed|Full Production|This datasheet contains final specifications. Fairchild<br>Semiconductor reserves the right to make changes at<br>any time without notice in order to improve design.|
|Obsolete|Not In Production|This datasheet contains specifications on a product<br>that has been discontinued by Fairchild semiconductor.<br>The datasheet is printed for reference information only.|



Rev. E 

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