NCP1370BDR2G

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## Dimmable Quasi-Resonant Primary Side Current-Mode Controller for LED TV Backlight 

## _Product Preview_ NCP1370 

The NCP1370 is a PWM current mode controller targeting isolated flyback and non−isolated constant current topologies. The controller operates in a quasi−resonant mode to provide high efficiency. Thanks to a novel control method, the device is able to precisely regulate a constant LED current from the primary side. This removes the need for secondary side feedback circuitry, biasing and an opto−coupler. 

The device is highly integrated with a minimum number of external components. A robust suite of safety protection is built in to simplify the design. This device supports analog/digital dimming and both modes can be combined to enhance dimming precision. The NCP1370 has a programmable peak current limit to optimize design compatibility over a wide range of applications. The controller features a standby mode with reduced current consumption. 

## **Features** 

- Quasi−resonant Peak Current−mode Control Operation 

- Primary Side Sensing (no opto−coupler needed) 

## **QUASI−RESONANT PWM CONTROLLER FOR LED DRIVERS** 

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MARKING<br>DIAGRAM<br>8<br>SOIC−8<br>8 NCP1370x<br>D SUFFIX<br>ALYW<br>1 CASE 751<br>1 j-<br>NCP1370 = Specific Device Code<br>x = Device Option (A or B)<br>A = Assembly Location<br>L = Wafer Lot<br>Y = Year<br>W = Work Week<br>= Pb−Free Package<br>**----- End of picture text -----**<br>


## **PIN CONNECTIONS** 

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1<br>ILIM DIM<br>ZCD VIN<br>CS VCC<br>GND DRV<br>(Top View)<br>**----- End of picture text -----**<br>


- Wide VCC Range 

- Source 300 mA / Sink 500 mA Totem Pole Driver with 12 V Gate Clamp 

- Precise LED Constant Current Regulation  1% Typical 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 19 of this data sheet. 

- Line Feed−forward for Enhanced Regulation Accuracy 

- Low LED Current Ripple 

- 500 mV  1.2% Guaranteed Voltage Reference for Current Regulation 

- Programmable Cycle−by−Cycle Peak Current Limit 

- Low VCC(on) Allowing to use a Standby Power Supply to Power the Device 

- Analog or Digital Dimming 

- Wide Temperature Range of −40 to + 125  C 

- Robust Protection Features 

   - LED Open Circuit Protection 

   - Secondary Diode Short Protection 

   - Output Short Circuit Protection 

   - Shorted Current Sense Pin Fault Detection 

   - Brown−out 

   - VCC Under Voltage Lockout 

   - Thermal Shutdown 

- Pb−free, Halide−free MSL1 Product 

## **Typical Applications** 

   - TV Backlight 

   - Lighting with Auxiliary Power Supply 

- VCC Over Voltage Protection 

This document contains information on a product under development. **onsemi** reserves the right to change or discontinue this product without notice. 

Publication Order Number: **NCP1370/D** 

**1** 

 Semiconductor Components Industries, LLC, 2016 **July, 2024 − Rev. P2** 

**NCP1370** 

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Aux .<br>.<br>: I .<br>VDIM<br>1 8<br>2 7 VBIAS<br>3 6<br>4 5<br>H y ) t apes<br>**----- End of picture text -----**<br>


**Figure 1. Typical Application Schematic for NCP1370** 

**Table 1. PRODUCTS TABLE** 

|**Block or Electrical Parameter**<br>**NCP1370B**<br>**NCP1370A**<br>Brown−out blanking time tBO(blank)<br>100 s<br>2 ms<br>~~nnn~~<br>~~ne~~<br>~~Pf~~|
|---|
|Blanking circuit for leakage inductance reset detection<br>ON<br>ON<br>~~Pe~~|
|VCCOVP<br>Auto−recovery<br>Latched<br>Switching cycles count before activating the output diode short circuit<br>protection: VCS> VCS(stop)<br>4 cycles<br>4 cycles<br>Output Diode Short Circuit protection<br>Auto−recovery<br>Latched<br>~~Pee~~<br>~~ee~~<br>~~ee~~<br>~~Pee~~|
|Adjustable OVP Auto−recovery timer<br>1 second<br>4 seconds<br>~~Pee~~|
|CS short circuit protection (impedance measurement before startup)<br>ON<br>OFF<br>High mains valley switching<br>3rd<br>(all HL valleys incremented by 1)<br>2nd<br>Propagation delay from ZCD to DRV high state tZCD(DEM)<br>ON<br>ON<br>~~Pee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ey~~<br>~~nn~~|
|**Table 2. PIN FUNCTION DESCRIPTION**|
|**Pin N**<br>**Pin Name**<br>**Function**<br>**Pin Description**<br>1<br>ILIM<br>Peak current limit and 2nd<br>over current protection<br>This pin sets the cycle−by−cycle peak current limit threshold and the threshold for<br>secondary diode short detection<br>2<br>ZCD<br>Zero Crossing Detection<br>Connected to the auxiliary winding, this pin detects the core reset event.<br>3<br>CS<br>Current sense<br>This pin monitors the primary peak current.<br>4<br>GND<br>−<br>The controller ground<br>5<br>DRV<br>Driver output<br>The driver’s output to an external MOSFET<br>6<br>VCC<br>Supplies the controller<br>This pin is connected to an external power supply.<br>7<br>VIN<br>Brown−Out<br>Input voltage sensing<br>Over Voltage Protection<br>This pin observes the HV rail and protects the circuit in case of low main<br>conditions.<br>This pin also sense the line voltage for the valley selection and the line feed−forward<br>A Zener diode can also be used to pull−up the pin and stop the controller for<br>adjustable OVP protection<br>~~a a~~<br>~~esGe~~<br>~~a ee~~<br>~~ee~~<br>~~eeee~~<br>~~ee a~~<br>~~eeenn~~<br>~~ee a~~<br>~~eee~~<br>~~ee ee~~<br>~~es~~<br>~~Th~~|
|8<br>DIM<br>Analog / PWM dimming<br>This pin is used for analog or PWM dimming control. An analog signal than can be|
|varied between VDIM(EN)and VDIM100can be used to vary the current, or a PWM|
|signal with an amplitude greater than VDIM100.|
|This pin is also used for the OFF mode|



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**NCP1370** 

## **INTERNAL CIRCUIT ARCHITECTURE** 

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Internal CS_NOK Disable STOP VDD VREF<br>Thermal<br>Shutdown OFF<br>OVP2 VCC<br>Fault UVLO<br>VCC Management<br>Management<br>Aux_SCP Standby<br>ILIM Peak Current Limits fe VILIMIT a<br>Threshold VCC_OVP VCC Over Voltage<br>Generation VCS(stop) Ipkmax Protection<br>fe CS_STOP<br>BO_NOK<br>Qdrv VVIN VREF VCC<br>Clamp<br>ZCD Zero Crossing Detection Circuit<br>Valley Selection<br>Aux. Winding<br>S Short Circuit Prot. e Aux_SCP S Q Qdrv - DRV<br>VVIN<br>VVLY<br>Line R<br>Feedforward STOP VREF<br>SP T oS<br>OFF Mode<br>Standby Detection<br>DIM<br>CS Leading Constant−Current CS_reset<br>Edge Control<br>Blanking<br>Dimming<br>Ipkmax STOP VDIMA Type<br>Detection<br>Enable VDIMA<br>Max. Peak Disable<br>Current Ipkmax VVIN<br>VILIMIT Limit<br>VIN<br>CS Short BO_NOK Brown−Out<br>Protection CS_NOK<br>= “ L y<br>Over Voltage<br>Winding and OVP2 Protection<br>Output diode CS_STOP S S<br>GND Short Circuit<br>VCS(stop) Protection<br>**----- End of picture text -----**<br>


**Figure 2. Internal Circuit Architecture** 

**Table 3. MAXIMUM RATINGS TABLE** 

|**Symbol**|**Rating**|**Value**|**Unit**|
|---|---|---|---|
|VCC(MAX)<br>ICC(MAX)|Maximum Power Supply voltage, VCC pin, continuous voltage<br>Maximum current for VCC pin|−0.3, +35<br>Internally limited|V<br>mA|
|VDRV(MAX)<br>IDRV(MAX)|Maximum driver pin voltage, DRV pin, continuous voltage<br>Maximum current for DRV pin|−0.3, VDRV(Note 1)<br>−500, +800|V<br>mA|
|VMAX<br>IMAX|Maximum voltage on low power pins (except pins DIM, DRV and VCC)<br>Current range for low power pins (except pins DRV and VCC)|−0.3, +5.5<br>−2, +5|V<br>mA|
|VDIM(MAX)|Maximum voltage for DIM pin|−0.3, +7|V|
|RJ−A|Thermal Resistance Junction−to−Air|289|C/W|
|TJ(MAX)|Maximum Junction Temperature|150|C|



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**NCP1370** 

## **Table 3. MAXIMUM RATINGS TABLE** 

|**Symbol**|**Rating**|**Value**|**Unit**|
|---|---|---|---|
||Operating Temperature Range|−40 to +125|C|
||Storage Temperature Range|−60 to +150|C|
||ESD Capability, HBM model (Note 2)|4|kV|
||ESD Capability, MM model (Note 2)|200|V|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC unless otherwise noted. 

2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015. 

3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 

**Table 4. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V) 

For min/max values TJ = −40C to +125C, Max TJ = 150C, VCC = 12 V) 

|**Description**<br>**Test Condition**<br>**Symbol**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**STARTUP AND SUPPLY CIRCUITS**<br>~~a~~|
|---|
|Supply Voltage<br>V|
|Startup Threshold<br>Minimum Operating Voltage<br>VCCincreasing<br>VCCdecreasing<br>VCC(on)<br>VCC(off)<br>11<br>9<br>12<br>9.5<br>13<br>10|
|Hysteresis VCC(on)– VCC(off)<br>VCCdecreasing<br>VCC(HYS)<br>1.8<br>−<br>–|
|Internal logic reset equal to VCC(off)<br>VCC(reset)<br>9<br>9.5<br>10|
|Over Voltage Protection<br>VCC OVP threshold<br>VCC(OVP)<br>26<br>28<br>30<br>V<br>VCC(off)noise filter<br>VCC(reset)noise filter<br>tVCC(off)<br>tVCC(reset)<br>–<br>–<br>5<br>20<br>–<br>–<br>s<br>Startup current<br>ICC(start)<br>–<br>−<br>100<br>A<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~a~~|
|Starting time from exiting OFF Mode to 1stDRV pulse<br>tCC(start)<br>−<br>250<br>s|
|Supply Current<br>mA|
|Device Disabled/Fault<br>Device Enabled/No output load on pin 5<br>VCC> VCC(off)<br>Fsw= 65 kHz<br>ICC1<br>ICC2<br>0.8<br>–<br>1.2<br>2.3<br>1.4<br>4.0|
|Device Switching (Fsw= 65 kHz)<br>CDRV= 470 pF,<br>ICC3<br>–<br>2.7<br>5.0|
|Fsw= 65 kHz|
|Supply Current in OFF mode<br>ICC(off)<br>50<br>A<br>~~a~~|
|**CURRENT SENSE AND ILIM PIN**|
|Reference current for maximum peak current limit threshold<br>ILIM(REF)<br>190<br>200<br>210<br>A<br>~~a~~|
|Minimum value for internal VILIMIT<br>VpinILIM< 0.5 V<br>VILIMIT(MIN)<br>0.5<br>V<br>~~a~~|
|Maximum value for internal VILIMIT<br>Pin ILIM open<br>VILIMIT(MAX)<br>2.34<br>2.6<br>2.86<br>V<br>~~a~~|
|Difference between internal VILIMITand ILIM pin voltage<br>VpinILIM= 1.5 V<br>VILIMIT(offset)<br>−30<br>30<br>mV<br>~~a~~|
|VCS(stop)at VpinILIM= 1.5 V<br>VpinILIM= 1.5 V<br>VCS(stop)1<br>2.037<br>2.1<br>2.163<br>V<br>~~a~~|
|Leading Edge Blanking Duration for VILIM(Tj= −40C to<br>125C)<br>tLEB<br>280<br>330<br>380<br>ns<br>~~ee~~|
|Minimum on−time (equal to tLEB)<br>ton(MIN)<br>280<br>330<br>380<br>ns<br>~~a~~|
|Propagation delay from current detection to gate off−state<br>tILIM<br>–<br>50<br>150<br>ns<br>~~a~~|
|Maximum on−time<br>ton(MAX)<br>37.5<br>50<br>62.5<br>s<br>Minimum threshold value for immediate fault protection acti-<br>vation<br>VpinILIM< 0.5 V<br>VCS(stop)MIN<br>0.7<br>V<br>Minimum threshold value for immediate fault protection acti-<br>vation<br>Pin ILIM open<br>VCS(stop)MAX<br>3.64<br>V<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|Ratio between internal VCS(stop)and internal VILIMIT<br>KSTOP/ILIMIT<br>140<br>%<br>~~a~~|
|Leading Edge Blanking Duration for VCS(stop)<br>tBCS<br>–<br>200<br>–<br>ns<br>~~a~~|
|4. Guaranteed by design|



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## **NCP1370** 

**Table 4. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V) For min/max values TJ = −40C to +125C, Max TJ = 150C, VCC = 12 V) 

|**Description**<br>**Unit**<br>**Max**<br>**Typ**<br>**Min**<br>**Symbol**<br>**Test Condition**<br>**CURRENT SENSE AND ILIM PIN**<br>~~ee~~|
|---|
|Current source for CS to GND short detection<br>ICS(short)<br>400<br>500<br>600<br>A|
|Timer for measuring CS to GND short<br>tCS(short)<br>12<br>17<br>22<br>s<br>~~a~~|
|**GATE DRIVE**|
|Drive Resistance<br>DRV Sink<br>DRV Source<br>RSNK<br>RSRC<br>–<br>–<br>13<br>30<br>–<br>–<br>Drive current capability<br>mA<br>~~ee~~<br>~~ee~~|
|DRV Sink (Note 4)<br>ISNK<br>–<br>500<br>–|
|DRV Source (Note 4)<br>ISRC<br>–<br>300<br>–|
|Rise Time (10 % to 90 %)<br>CDRV= 470 pF<br>tr<br>–<br>40<br>–<br>ns<br>~~a~~|
|Fall Time (90 % to 10 %)<br>CDRV= 470 pF<br>tf<br>–<br>30<br>–<br>ns<br>~~a~~|
|DRV Low Voltage<br>VCC= VCC(off)+0.2 V<br>CDRV= 470 pF,<br>RDRV=33 k<br>VDRV(low)<br>8<br>–<br>–<br>V<br>~~a~~<br>~~ee~~|
|DRV High Voltage<br>VCC= 30 V<br>CDRV= 470 pF,<br>RDRV=33 k<br>VDRV(high)<br>10<br>12<br>14<br>V<br>~~a~~<br>~~ee~~|
|**ZERO VOLTAGE DETECTION CIRCUIT**|
|ZCD threshold voltage<br>VZCDincreasing<br>VZCD(THI)<br>30<br>50<br>70<br>mV<br>~~a~~|
|ZCD threshold voltage (Note 4)<br>VZCDdecreasing<br>VZCD(THD)<br>20<br>40<br>60<br>mV<br>~~a~~|
|ZCD hysteresis (Note 4)<br>VZCDincreasing<br>VZCD(HYS)<br>8<br>–<br>–<br>mV|
|Threshold voltage for output short circuit or aux. winding<br>short circuit detection<br>VZCD(short)<br>0.8<br>1<br>1.2<br>V<br>~~ee~~|
|Short circuit detection Timer<br>VZCD< VZCD(short)<br>tOVLD<br>70<br>90<br>110<br>ms<br>~~a~~|
|Auto−recovery timer duration<br>trecovery<br>3<br>4<br>5<br>s|
|Input clamp voltage<br>High state<br>Low state<br>Ipin1= 3.0 mA<br>Ipin1= −2.0 mA<br>VZCD(CH)<br>VZCD(CL)<br>–<br>−0.9<br>8<br>−0.6<br>–<br>−0.3<br>V<br>Propagation Delay from valley detection to DRV high<br>VZCDdecreasing<br>tZCD(DEM)<br>−<br>−<br>480<br>ns<br>~~ee~~<br>~~ee~~<br>~~a~~|
|Delay from valley lockout output to DRV latch set<br>VZCDdecreasing<br>tLEB4<br>125<br>250<br>375<br>ns<br>~~a~~|
|Blanking delay after on−time<br>VREF> 100 mV<br>tZCD(BLANK1)<br>1.2<br>1.6<br>2<br>s<br>~~a~~|
|Blanking delay after on−time at light load<br>VREF< 75 mV<br>tZCD(BLANK2)<br>0.6<br>0.8<br>1<br>s<br>~~a~~|
|Timeout after last demag transition<br>tTIMO<br>5<br>6.5<br>8<br>s<br>~~a~~|
|**LINE FEED−FORWARD**|
|VVINto ICS(offset)conversion ratio<br>KLFF<br>15<br>17<br>19<br>A/V<br>~~a~~|
|Offset current maximum value<br>VpinVIN= 4.5 V<br>Ioffset(MAX)<br>67.5<br>76.5<br>85.5<br>A<br>~~a~~|
|**CONSTANT CURRENT CONTROL**|
|Reference Voltage (after division by 2) (Tj= 25C)<br>VREF<br>495<br>500<br>505<br>mV|
|Reference Voltage (after division by 2) (Tj= 0C to 85C)<br>VREF<br>492<br>500<br>508<br>mV|
|Reference Voltage (after division by 2) (Tj=−40C to 125C)<br>VREF<br>488<br>500<br>512<br>mV|
|Current sense lower threshold for detection of the leakage<br>VCS(low)<br>25<br>55<br>85<br>mV|
|inductance reset time|
|Blanking time for leakage inductance reset detection<br>tCS(low)<br>130<br>ns|



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**5** 

## **NCP1370** 

**Table 4. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V) For min/max values TJ = −40C to +125C, Max TJ = 150C, VCC = 12 V) 

|**VALLEY SELECTION**|||||||
|---|---|---|---|---|---|---|
|Threshold for line range detection Vinincreasing<br>(1stto 2ndvalley or 1stto 3rdtransition for VREF> 0.375 V)|VVINincreases|VHL|2.28|2.4|2.52|V|
|Threshold for line range detection Vindecreasing<br>(2ndto 1stvalley or 1stto 3rdtransition for VREF> 0.375 V)|VVINdecreases|VLL|2.18|2.3|2.42|V|
|Blanking time for line range detection||tHL(blank)|15|25|35|ms|
|Valley thresholds (VREF= 500 mV)<br>1stto 2ndvalley transition at LL and 2ndto 3rdvalley HL<br>(3rdto 4thvalley HL for version B) VREFdecreases<br>2ndto 1stvalley transition at LL and 3rdto 2ndvalley HL<br>(4thto 3rdvalley HL for version B), VREFincr.<br>2ndto 4thvalley transition at LL and 3rdto 5thvalley HL<br>(4thto 6thvalley HL for version B), VREFdecr.<br>4thto 2ndvalley transition at LL and 5thto 3rdvalley HL<br>(6thto 4thvalley HL for version B), VREFincr.<br>4thto 7thvalley transition at LL and 5thto 8thvalley HL<br>(6thto 9th valley HL for version B), VREFdecr.<br>7thto 4thvalley transition at LL and 8thto 5thvalley HL<br>(9thto 6th valley HL for version B), VREFincr.<br>7thto 11thvalley transition at LL and 8thto 12thvalley HL<br>(9thto 13th valley HL for version B), VREFdecr.<br>11thto 7thvalley transition at LL and 12thto 8thvalley HL<br>(13thto 9th valley HL for version B), VREFincr.<br>11thto 13thvalley transition at LL and 12thto 15thvalley HL<br>(13thto 16th valley HL for version B), VREFdecr.<br>13thto 11thvalley transition at LL and 15thto 12thvalley HL<br>(16thto 13th valley HL for version B), VREFincr.|VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases|VVLY1−2/2−3<br>VVLY2−1/3−2<br>VVLY2−4/3−5<br>VVLY4−2/5−3<br>VVLY4−7/5−8<br>VVLY7−4/8−5<br>VVLY7−11/8−12<br>VVLY11−7/12−8<br>VVLY11−13/12−1<br>5<br>VVLY13−11/15−1<br>2|350<br>366<br>231<br>249<br>–<br>–<br>–<br>–<br>–<br>–|373<br>390<br>248<br>267<br>150<br>165<br>75<br>100<br>30<br>40|396<br>414<br>265<br>285<br>–<br>–<br>–<br>–<br>–<br>–|mV|
|Valley thresholds in percentage of VREF<br>1stto 2ndvalley transition at LL and 2ndto 3rdvalley HL<br>(3rdto 4thvalley HL for version B) VREFdecreases<br>2ndto 1stvalley transition at LL and 3rdto 2ndvalley HL<br>(4thto 3rdvalley HL for version B), VREFincr.<br>2ndto 4thvalley transition at LL and 3rdto 5thvalley HL<br>(4thto 6thvalley HL for version B), VREFdecr.<br>4thto 2ndvalley transition at LL and 5thto 3rdvalley HL<br>(6thto 4thvalley HL for version B), VREFincr.<br>4thto 7thvalley transition at LL and 5thto 8thvalley HL<br>(6thto 9th valley HL for version B), VREFdecr.<br>7thto 4thvalley transition at LL and 8thto 5thvalley HL<br>(9thto 6th valley HL for version B), VREFincr.<br>7thto 11thvalley transition at LL and 8thto 12thvalley HL<br>(9thto 13th valley HL for version B), VREFdecr.<br>11thto 7thvalley transition at LL and 12thto 8thvalley HL<br>(13thto 9th valley HL for version B), VREFincr.<br>11thto 13thvalley transition at LL and 12thto 15thvalley HL<br>(13thto 16th valley HL for version B), VREFdecr.<br>13thto 11thvalley transition at LL and 15thto 12thvalley HL<br>(16thto 13th valley HL for version B), VREFincr.|VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases|VVLY1−2/2−3<br>VVLY2−1/3−2<br>VVLY2−4/3−5<br>VVLY4−2/5−3<br>VVLY4−7/5−8<br>VVLY7−4/8−5<br>VVLY7−11/8−12<br>VVLY11−7/12−8<br>VVLY11−13/12−1<br>5<br>VVLY13−11/15−1<br>2|70<br>73<br>46<br>50<br>–<br>–<br>–<br>–<br>–<br>–|74.5<br>78<br>49.5<br>53.5<br>30<br>33<br>15<br>20<br>6<br>8|79<br>83<br>53<br>57<br>–<br>–<br>–<br>–<br>–<br>–|%|



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**6** 

## **NCP1370** 

**Table 4. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V) For min/max values TJ = −40C to +125C, Max TJ = 150C, VCC = 12 V) 

|**Description**<br>**Unit**<br>**Max**<br>**Typ**<br>**Min**<br>**Symbol**<br>**Test Condition**<br>**DIMMING SECTION**<br>~~Po~~|
|---|
|VDIM(EN)comparator hysteresis<br>VDIMincreasing<br>VEN(HYS)<br>−<br>50<br>−<br>mV<br>DIM pin voltage for maximum output current (TJ= −40 to<br>125C)<br>VDIM100<br>2.9<br>3<br>3.1<br>V<br>DIM pin voltage for maximum output current at TJ= 25C<br>VDIM100<br>2.94<br>3<br>3.06<br>V<br>Dimming range<br>VDIM(range)<br>–<br>2.3<br>–<br>V<br>Clamping voltage for DIM pin<br>VDIM(CLP)<br>–<br>7<br>–<br>V<br>Dimming pin pull−up current source<br>IDIM(pullup)<br>–<br>5<br>–<br>A<br>~~GC~~<br>~~GO~~<br>~~es~~<br>~~ee ee ee~~<br>~~GG~~<br>~~GO~~<br>~~OO~~<br>~~GC~~<br>~~GO~~<br>~~GO~~<br>~~GC~~<br>~~GO~~<br>~~GO~~<br>~~pT~~|
|**THERMAL SHUTDOWN**|
|Thermal Shutdown (Note 4)<br>Device switching<br>TSHDN<br>130<br>150<br>170<br>C|
|(FSWaround 65 kHz)|
|Thermal Shutdown Hysteresis (Note 4)<br>TSHDN(HYS)<br>–<br>50<br>–<br>C|
|**BROWN−OUT AND OVP**|
|Brown−Out ON level (IC start pulsing)<br>VVINincreasing<br>VBO(on)<br>0.90<br>1<br>1.10<br>V<br>Brown−Out OFF level (IC shuts down)<br>VVINdecreasing<br>VBO(off)<br>0.85<br>0.9<br>0.95<br>V<br>BO comparators delay<br>tBO(delay)<br>–<br>30<br>–<br>s<br>Brown−Out blanking time for version A<br>tBO(blank1)<br>1.4<br>2<br>2.6<br>ms<br>Brown−Out blanking time for version B<br>tBO(blank2)<br>50<br>100<br>150<br>s<br>Brown−out pin bias current<br>IBO(bias)<br>−250<br>–<br>250<br>nA<br>Clamped voltage (VIN pin left open)<br>VIN pin open<br>VVIN(clamp)<br>3.9<br>4.1<br>4.3<br>V<br>VIN pin Clamp series resistor<br>RVIN(clamp)<br>1<br>k<br>VIN pin detection level for OVP<br>VVINincreasing<br>VOVP<br>4.75<br>5<br>5.25<br>V<br>Delay before OVP confirmation<br>tOVP(delay)<br>50<br>s<br>Adjustable OVP auto−recovery timer (version B)<br>tOVP(recovery1)<br>1<br>s<br>Adjustable OVP auto−recovery timer (version A)<br>tOVP(recovery2)<br>4<br>s<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~<br>~~Gc~~<br>~~Ge~~<br>~~GO~~<br>~~GO~~<br>~~GO~~<br>~~co~~<br>~~Ge~~<br>~~GO~~<br>~~GG~~<br>~~GO~~<br>~~eG~~<br>~~Os~~<br>~~eG~~<br>~~GO~~<br>~~GO~~<br>~~Co~~<br>~~a~~<br>~~GO~~<br>~~GO~~<br>~~pT~~|
|4. Guaranteed by design|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

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**NCP1370** 

## **APPLICATION INFORMATION** 

The NCP1370 is a LED driver for flyback and non−isolated buck−boost / SEPIC converters. It implements a current−mode architecture quasi−resonant architecture to prevent valley−jumping instability. A proprietary circuitry ensures accurate regulation of the output current without the need of a secondary side feedback. The circuit features powerful protections to ensure a robust LED driver design without the need of extra external components or overdesign. 

- **Quasi−Resonance Current−Mode Operation:** implementing quasi−resonance operation in peak current−mode control, the NCP1370 optimizes the efficiency by switching in the valley of the MOSFET drain−source voltage. Thanks to smart control algorithm, the controller locks−out in a selected valley and remains locked until the input voltage or the output current set point significantly changes. 

- **Primary Side Constant Current Control:** thanks to a proprietary circuit, the controller accurately controls the output current without requiring a secondary side feedback (no optocoupler needed). An output current deviation below  2% is typically obtained. 

- **VCC Over Voltage Protection:** if the voltage on VCC pin exceeds an internal limit, the controller shuts down and waits 4 seconds before restarting pulsing (version B) or stays latched (A version). 

- **Adjustable peak current limit:** the cycle−by−cycle maximum peak current limit and the second over current protection level can be adjusted externally by connecting a resistor between ILIM pin and ground. 

- **Brown−Out:** the controller includes a brown−out circuit which safely stops the controller in case the input voltage is too low. The device will automatically restart if the line recovers. 

- **Adjustable Over voltage protection:** By connecting a zener diode to the VIN pin, an adjustable over voltage protection can be implemented to protect against open LEDs. Upon detection, the controller waits 4 s (version A) or 1 s (version B) before attempting to restart switching. 

- **Cycle−by−cycle peak current limit:** when the current sense voltage exceeds pin ILIM voltage VILIM, the 

MOSFET is turned off for the rest of the switching cycle. 

- **Winding Short−Circuit Protection (2[nd] over current protection level):** an additional comparator with a short LEB filter (tBCS) senses the CS signal and stops the controller if VCS reaches 140% of VILIMIT). For noise immunity reasons, this comparator is enabled only during the main LEB duration tLEB. 

- **Output Short−circuit protection:** If a very low voltage is applied on ZCD pin for 90 ms (nominal), the controllers assume that the output or the ZCD pin is shorted to ground and enters shutdown. After waiting for 4 seconds, the controller restarts switching. 

- **Linear or PWM dimming:** the DIM pin allows implementing both analog and PWM dimming. 

- **OFF Mode:** The IC enters in OFF mode after detecting a fault and whenever the DIM pin voltage stays low during more than 4 seconds. In this mode, the IC is off and has a reduced current consumption. This allows simplifying the PCB design around the ON/OFF opto−coupler. 

- **Floating or Short pin detection:** The NCP1370 protections help passing safety tests. For instance, the circuit stops operating when the CS pin is grounded or when the GND pin is open. 

## **Constant Current Control** 

Capitalizing on the constant current control technique developed in the NCL3008X product, the NCP1370 accurately regulates the output current of a flyback converter from its primary side. 

By connecting the clamping capacitor of the flyback converter to the sense resistor as shown in the typical application schematic (Figure 1), we have an image of the drain current waveform and of the leakage inductance current waveform. Thus, by looking at the current sense pin waveform, the controller is able to detect the reset of the transformer leakage inductance. Indeed, the leakage inductance limits the output rectifier peak current as shown in Figure 3 where it is shown that: Nsp * ID,pk < IL,pk. 

Also, by monitoring the auxiliary winding voltage through the ZCD pin, we can detect the end of conduction of the secondary rectifier. 

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**NCP1370** 

**==> picture [280 x 237] intentionally omitted <==**

**----- Start of picture text -----**<br>
I<br>L,pk<br>N I<br>sp D,pk<br>Ipri(t)<br>Isec(t)<br>time<br>Zi t1 T2<br>ton t<br>demag<br>Vaux(t)<br>time<br>**----- End of picture text -----**<br>


**Figure 3. Flyback Currents and Auxiliary Winding Voltage in DCM** 

The constant current control block picks up the leakage inductor current, the end of conduction of the output rectifier and controls the drain current to maintain the output current constant. 

We have: 

**==> picture [151 x 24] intentionally omitted <==**

Where: 

- VREF is the output current internal reference 

- Nsp is the secondary to primary transformer turns ratio: Nsp = Ns / Np 

- Rsense is the current sense resistor 

The output current value is set by choosing the sense resistor: 

**==> picture [150 x 24] intentionally omitted <==**

From (Equation 1), the first key point is that the output current is independent of the inductor value. Moreover, the leakage inductance does not influence the output current value as the reset time is taken into account by the controller. 

## **Soft−Start** 

At startup or after recovering from a fault, there is a small internal soft−start of 200 s maximum. 

In addition, during startup, as the output voltage is zero volts, the demagnetization time is long and the constant current control block will slowly increase the peak current towards its nominal value as the output voltage grows. Figure 5 shows a soft−start simulation example for a 9 W LED power supply. 

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**NCP1370** 

**==> picture [487 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
16.0<br>12.0 1 Vout<br>8.00<br>a ee<br>4.00<br>0<br>—— ae<br>800m<br>600m<br>==SS=SSSS== 2 Iout<br>400m<br>200m<br>0<br>===—<br>800m<br>600m<br>4 VControl<br>400m<br>a ea<br>200m<br>0 3 VCS<br>Al<br>604u 1.47m 2.34m 3.21m 4.07m<br>time in seconds<br>(V)<br>(A)<br>(V)<br>**----- End of picture text -----**<br>


**Figure 4. Startup Simulation showing the Natural Soft−start** 

## **Adjustable Cycle−by−Cycle Current Limit** 

The pin ILIM allows adjusting the threshold for maximum peak current limit VILIMIT and also the 2[nd] over current protection (OCP2) threshold VCS(stop) which helps protecting against short circuit of the secondary winding or of the output diode. 

More precisely, the maximum peak current threshold VILIMIT is equal to the ILIM pin voltage and VCS(stop) value is derived from VILIMIT. By connecting a resistor between ILIM and GND pins, the value of internal cycle−by−cycle current limit VILIMIT is: 

VILIMIT VILIM ILIM(REF)RILIM (eq. 3) The threshold for immediate short circuit protection VCS(stop) is given by: 

VCS(stop) 1.4 VILIMIT (eq. 4) Practically, VILIMIT can be adjusted from 0.5 V to 2.6 V, meaning VCS(stop) range is from 0.7 V to 3.64 V. 

When the current sense voltage exceeds the internal threshold VILIMIT, the MOSFET is turned off for the rest of the switching cycle. Figure 5 shows the schematic of ILIM pin. 

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**NCP1370** 

**==> picture [342 x 190] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vdd<br>VILIM(MAX)<br>I<br>LIM(REF)<br>Clamp<br>ILIM Al e e :<br>V<br>ILIM<br>Buffer Gain V<br>CS(stop)<br>on a<br>Clamp<br>RILIM<br>|<br>V ILIM(MIN)<br>V<br>ILIM<br>Figure 5. Block Diagram of ILIM Pin<br>**----- End of picture text -----**<br>


## **Winding and Output diode Short−Circuit Protection (OCP2)** 

The cycle−by−cycle peak current limit threshold _VILIMIT_ also set the maximum duty cycle for a given application. The maximum duty cycle is given by: 

In parallel with the cycle−by−cycle sensing of the CS pin, another comparator with a reduced LEB ( _tBCS_ ) and a higher threshold (VCS(stop)) is able to sense winding short−circuit and stop the controller. In version B, the controller stops the DRV pulses after counting 4 cycles of VCS > VCS(stop). The controller attempts to re−start after waiting 4 seconds. In version A, after counting 4 cycles of VCS > VCS(stop), the controller stays latched. 

**==> picture [169 x 24] intentionally omitted <==**

Where: 

- tv is the valley duration 

- Tsw is the switching period 

For switching frequencies below 100 kHz, the term tv/Tsw can be neglected: 

The controller is unlatched by one of the 3 following events: 

##  VCC < VCC(off) 

**==> picture [433 x 309] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>DMAX 1 V REF (eq. 6)  Standby by VDIM < VDIM(EN) during 4 seconds<br>ILIMIT<br> BO_NOK becomes high<br>After being unlatched, the controller goes into OFF Mode.<br>S<br>Q DRV Vdd UVLO aux<br>Q<br>CS R Vcc VCC<br>LEB1 + PWMreset management<br>Vcontrol −<br>rl<br>4−s timer VCCreset<br>+ Ipkmax<br>−<br>VILIMIT<br>STOP<br>LEB2 + CS_STOP 1 pulse<br>or<br>− 4 pulses<br>S OFF<br>V Q<br>CS(stop)<br>Q<br>R<br>4−s timer<br>from Fault Management Block<br>**----- End of picture text -----**<br>


After being unlatched, the controller goes into OFF Mode. 

**Figure 6. Winding Short Circuit Protection, Max. Peak Current Limit Circuits** 

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## **NCP1370** 

## **PWM or Linear Dimming Detection** 

The pin DIM allows dimming the LED light. Analog dimming or digital (PWM) dimming can be used. 

If the power supply designer apply an analog signal varying from VDIM(EN) to VDIM100 to the DIM pin, the output current will increase or decrease proportionally to the voltage applied. For VDIM = VDIM100, the power supply delivers the maximum output current. 

If a voltage lower than VDIM(EN) is applied to the DIM pin, the DRV pulses are disabled. Thus, for digital dimming, a PWM signal with a low state value lower than VDIM(EN) and a high state value higher than VDIM100 should be applied. 

The DIM pin is pulled up internally by a small current source or resistor. Thus, if the pin is left open, the controller is able to start. 

## **Soft Stop during PWM Dimming** 

The NCP1370 features an internal soft−stop of 200 s maximum in order to compensate the output current decrease caused by the soft−start during PWM dimming. 

Practically, when VDIM < VDIM(EN), the controller decreases the peak current from its current state to nearly zero before stopping the DRV pulses. 

This allows having a very good correlation between the dimming duty−cycle and the output current value when dimming at low duty−cycle. 

Also, it is important to note that for good correlation between the dimming duty−cycle (which represent the expected output current value relative to the nominal value) and the actual measured output current, the high state duration of the dimming signal should not be below 200 s. 

Figure 8 shows the drain source waveform during soft−stop. 

## **OFF Mode with DIM Pin** 

The OFF Mode is entered when VDIM stays below VDIM(EN) for 4 seconds. In this mode, IC consumption is reduced to ICC(off) (below 50 A). The OFF mode is exited only when VDIM becomes higher than VDIM(EN)+VEN(HYS). 

**==> picture [507 x 339] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDIM i [1]<br>Analog dimming 111 PWM dimming 1 [1] 1 Deep PWM dimming<br>| 1 | | 11| fF<br>'1<br>1 [1]<br>1 1<br>3 V VDIM100 100% Iout 111 [1] 111<br>' [1]<br>'1<br>' [1]<br>11<br>1 [1]<br>1 1<br>1 [1]<br>1 1<br>1 [1]<br>1 1<br>1 [1]<br>11<br>1 [1]<br>VDIM(EN) 0% Iout 111 [1]<br>0.7 V ee4 eBi7 _‘|iri1 _ —_—<br>Figure 7. Pin DIM Chronograms<br>|T<br>||<br>||<br>||<br>|| VDIM ||<br>||<br>||<br>||<br>||<br>| |<br>=<br>— so a a ae SPSS eee rn<br>|1<br>||<br>||<br>||<br>||<br>|| V<br>drain<br>**----- End of picture text -----**<br>


**Figure 8. Soft−stop** 

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# **NCP1370** 

## **VCC Over Voltage Protection** 

In order to protect itself against too high supply voltage, the controller features an over voltage protection for the VCC pin. When the VCC voltage reaches the VCC(OVP) threshold, the controller stops the DRV pulses and shutdown. Depending on the version, the controller goes in auto−recovery mode (version B) or in latched mode (version A). 

In the auto−recovery mode, the controller waits 4 s and tries to re−start. In order to restart pulsing, the controller 

goes through a complete sequence OFF Mode  FAULT Mode (see Fault Management section for more information) 

In the latched mode, the controller stops pulsing and waits that one of the 3 following events occurs to reset the latch: 

- VCC < VCC(off) 

- Standby by VDIM < VDIM(EN) during 4 seconds 

- BO_NOK becomes high 

When the OVP Latch is reset, the controller goes into OFF Mode. 

**==> picture [482 x 379] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>CC<br>V<br>CC(OVP)<br>OVP<br>V<br>CC(on)<br>V<br>CC(off)<br>V<br>DIM<br>V<br>DIM(100)<br>V<br>DIM(EN)<br>STATE RESET OFF RUN 4−s Timer RUN<br>FAULT OFF FAULT<br>V<br>DRV CS impedance check ÎÎÎÎÎÎ ÎÎÎÎÎÎ CS impedance check<br>ÎÎÎÎÎÎ ÎÎÎÎÎÎ<br>ÎÎÎÎÎÎ ÎÎÎÎÎÎ<br>Figure 9. VCC Over Voltage Protection Chronograms<br>Valley Selection The input voltage is sensed by the VIN pin. The internal<br>Quasi−Square wave resonant systems have a wide logic selects the operating valley according to VIN pin<br>switching frequency excursion. The switching frequency voltage and DIM pin voltage.<br>**----- End of picture text -----**<br>


## **Valley Selection** 

Quasi−Square wave resonant systems have a wide switching frequency excursion. The switching frequency increases when the output load decreases or when the input voltage increases. The switching frequency of such systems must be limited. 

By default, when the output current is not dimmed, the controller operates in the first valley at low line and in the second valley at high line for version A. For version B, the controller operates in the 3[rd] valley at high line. Table 5 summarizes the valley selected by the controller as a function of the output current and the input voltage. The numbers in blue are the selected valleys for version B. 

The NCP1370 changes valley as the input voltage increases and as the output current set−point is varied during dimming. This limits the switching frequency excursion. Once a valley is selected, the controller stays locked in the valley until the input voltage or the output current set−point varies significantly. 

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**NCP1370** 

**Table 5. VALLEY SELECTION** 

**==> picture [493 x 283] intentionally omitted <==**

**----- Start of picture text -----**<br>
VIN pin voltage for valley change<br>Iout value at which the  Iout value at which the<br>controller changes valley VVIN decreases controller changes valley<br>( Iout  decreasing) ( Iout  increasing)<br>0         −− LL −−      2.3 V      −− HL −−     5 V<br>100% 100%<br>1 [st] 2 [nd]   (3 [rd] )<br>oT<br>75% 78%<br>2 [nd] 3 [rd] (4 [th] )<br>50% 53%<br>4 [th] 5 [th] (6 [th] )<br>30% 33%<br>7 [th] 8 [th] (9 [th] )<br>15% 20%<br>11 [th] 12 [th] (13 [th] )<br>6% 8%<br>0% 13 [th] 15 [th] (16 [th] ) 0%<br>ie<br>0         −− LL −−       2.4 V     −− HL −−     5 V<br>VVIN increases<br>Pf VIN pin voltage for valley change<br>Zero Crossing Detection Block At startup or in case of extremely damped free<br>The ZCD pin allows detecting when the drain−source oscillations, the ZCD comparator may not be able to detect<br>voltage of the power MOSFET reaches a valley. the valleys. To avoid such a situation, the NCP1370 features<br>A valley is detected when the voltage on pin 1 crosses a Time−Out circuit that generates pulses if the voltage on<br>down the 55−mV internal threshold. ZCD pin stays below the 55−mV threshold for 6.5 s.<br>outI<br> decreases<br>Iout  increases<br>**----- End of picture text -----**<br>


**Zero Crossing Detection Block** The ZCD pin allows detecting when the drain−source voltage of the power MOSFET reaches a valley. 

A valley is detected when the voltage on pin 1 crosses down the 55−mV internal threshold. 

In order to decrease the capacitor value needed on ZCD pin to turn−on the MOSFET right in the valley or in some case remove it, a small delay (250 ns) is added internally before turning−on the MOSFET. 

The Time−out also acts as a substitute clock for the valley detection and simulates a missing valley in case of too damped free oscillations (Figure 11). 

**==> picture [469 x 251] intentionally omitted <==**

**----- Start of picture text -----**<br>
Tblank Time−Out<br>ZCD<br>+ Clock<br>V<br>. ZCD(TH)<br>−<br>Tblank<br>+<br>V<br>ZCD(short)<br>−<br>90−ms<br>Timer<br>Enable_b S<br>Q Aux_SCP<br>Q<br>R<br>a i n ane<br>4−s Timer<br>Figure 10. ZCD Block Schematic<br>**----- End of picture text -----**<br>


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**NCP1370** 

**==> picture [485 x 259] intentionally omitted <==**

**----- Start of picture text -----**<br>
VZCD<br>V<br>34 ZCD th ( )<br>The 3rd valley is<br>high validated 14<br>2n [d]  , 3rd<br>—————_———<br>low 12<br>The 2n [d]  valley is detected   The 3rd valley is not detected by<br>By the ZCD comparator the ZCD comp<br>high<br>low 15<br>ZCD<br>high<br>comp<br>low 16<br>TimeOut adds a pulse to account for the  TimeOut<br>missing 3 [rd]  valley<br>high<br>E TT——EE Er ; |] [||] 7<br>low 17 Clock<br>**----- End of picture text -----**<br>


**Figure 11. Time−out Chronograms** 

## **Output Short Circuit Protection** 

Because of the time−out function, if the ZCD pin or the auxiliary winding is shorted, the controller will continue switching leading to improper regulation of the LED current. 

Moreover during an output short circuit, the controller will strive to maintain the constant current operation. 

In order to avoid these scenarios, a secondary timer starts counting when the ZCD voltage is below the VZCD(short) threshold (Figure 10). If this timer reaches 90 ms, the controller detects a fault and enters the auto−recovery fault mode: the controller stops pulsing and waits 4−s before going through a complete startup sequence. 

This protection is disabled when VDIM < VDIM(EN). 

## **Line Feed−Forward** 

Because of the propagation delays, the MOSFET is not turned−off immediately when the current set−point is reached. As a result, the primary peak current is higher than expected and the output current increases. To compensate the peak current increase brought by the propagation delays, a positive voltage proportional to the line voltage is added on the current sense signal. The amount of offset voltage can be adjusted using the RCS resistor as shown in Figure 12. 

**==> picture [236 x 37] intentionally omitted <==**

This offset voltage is always applied over the load range. 

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**NCP1370** 

**==> picture [466 x 290] intentionally omitted <==**

**----- Start of picture text -----**<br>
+ noise delay<br>−<br>S<br>Q OVP2<br>Bulk rail<br>i VOVP Q 2<br>Aux R<br>4−s Timer<br>(1-s Timer version B)<br>. VIN vDD<br>| : I CS(offset) CS RCS<br>Rclamp<br>Rsense<br>Q_drv<br>Vclamp<br>ings<br>+<br>Blanking BO_NOK<br>− time<br>oso<br>1 V if BONOK high<br>0.9 V if BONOK low<br>Clamp<br>**----- End of picture text -----**<br>


**Figure 12. Line Feed−Forward, Adjustable OVP and Brown−out Schematic** 

## **Adjustable Over Voltage Protection** 

A clamping circuit on VIN pin limits the voltage excursion to 4.1 V (Figure 12). This level is high enough to allow good linearity of the line feedforward current for universal mains applications with an input voltage up to 265 V rms. 

When the zener diode starts conducting, it injects current inside the clamping circuit and the voltage on VIN pin increases. When VVIN exceeds VOVP during tOVP(delay), the circuit detects an over voltage condition and stops the DRV pulses. The controller waits until the OVP timer (tOVP(recovery)) has elapsed (4 s for version A, 1 s for version B) and restarts switching. 

## **Brown−out** 

In order to protect the supply against a very low input voltage, the NCP1370 features a brown−out circuit with a fixed ON/OFF threshold (Figure 12). The controller is allowed to start if a voltage higher than 1 V is applied to the VIN pin and shuts−down if the VIN pin voltage decreases and stays below 0.9 V when the BO blanking timer has elapsed (BO_NOK high). When a brown−out condition is detected, the circuit stops pulsing and goes into the OFF mode detailed in the “Fault Management Section”. 

## **Pin Connection Faults** 

##  **CS pin Short to ground** 

The circuit senses the CS pin impedance every time it starts−up. If the measured impedance does not exceed 

110 typically, the circuit does not start pulsing and shutdown. The circuit attempts to restart after waiting 4 seconds. In practice, it is recommended to place a minimum of 250  in series between the CS pin and the current sense resistor to take into account parasitic component effect and electrical parameters tolerance. 

##  **Fault of GND pin connection** 

If the GND pin is properly connected, the current drawn from the positive terminal of the VCC capacitor flows out of the GND pin to return to the negative terminal of the VCC capacitor. If the GND pin is not connected, the circuit ESD diodes offer another return path. The accidental non−connection of the GND pin is monitored by detecting that one of the ESD diode is conduction. Practically, the ESD diode of CS pin is monitored. If such a fault is detected for 200 s, the circuit stops generating DRV pulses. 

## **FAULT MANAGEMENT AND STARTUP SEQUENCE** 

Figure 13 and Figure 14 shows the state diagrams of the NCP1370. 

## **OFF Mode** 

At startup, as long as VCC is not high enough, the controller is reset. Its current consumption is ICC(start). When VCC > VCC(on), the controller goes in OFF mode and waits 

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## **NCP1370** 

for the enable signal (VDIM > VDIM(EN)). In OFF mode, the IC consumption is very low (50 A maximum). 

The OFF mode is exited only if VCC > VCC(on) and VDIM > VDIM(EN). The controller then goes in FAULT mode. 

More generally, the OFF mode is entered upon the following events: 

- VCC > VCC(OVP) 

- An Output / Auxiliary winding Short circuit is detected: “Aux_SCP high” 

- Second OCP level triggered 

When the 4−s timer has elapsed, the controller goes in OFF Mode. 

- VCC < VCC(off) 

- Brown−out edge 

- VDIM < VDIM(EN) after 4 seconds 

- Die over temperature (TSD) 

- The 4−s auto−recovery timer has elapsed 

## **FAULT Mode** 

In this mode, the controller measures CS pin impedance. If CS pin is not shorted the controller is allowed to start the DRV pulses. If CS pin is shorted, the controller starts the 4 seconds timer. No DRV pulse is generated in this mode. 

## **AR Mode** 

In the auto−recovery mode, the 4 seconds timer is counting, DRV is not pulsing. The 4 seconds timer starts counting when: 

- VDIM < VDIM(EN) 

- A short circuit on CS pin is detected 

## **Adjustable OVP Management** 

When the adjustable OVP on VIN pin is triggered, the controller stops the DRV pulses and starts the OVP2 Timer (4 s in version A, 1 s in version B). 

When the OVP2 timer has elapsed, the controller goes in FAULT mode and restart switching if no other fault is detected. 

## **Latched Protection (VCC OVP, Output Diode Short Circuit Protection in Version A)** 

When VCC > VCC(OVP) or when the 2[nd] OCP is triggered, the DRV pulses stop and the controller is latched (Figure 14). 

The Latch resets when one of the 3 following events occurs: 

- VCC < VCC(off) 

- VDIM < VDIM(EN) during 4 seconds 

- BO_NOK becomes high 

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**==> picture [456 x 395] intentionally omitted <==**

**----- Start of picture text -----**<br>
NCP1370<br>RESET<br>Timer ends (AR_end)<br>VCC too VddINT POR or BO_NOK edge<br>low or  TSD_end<br>or  VCC < VCC(off)<br>OFF<br>BO_NOK edge<br>or TSD_end BO_NOK edge VDIM > VDIM(EN)<br>or VCC < VCC(off) or TSD_end and VCC > VCC(on)<br>or VCC < VCC(off)<br>Timer ends TI<br>OVP2 AR<br>FAULT mode<br>Timer mode<br>OVP2 CS_short high<br>or VCC_OVP high<br>CS_OK or VDIM < VDIM(EN)<br>VDIM > VDIM(EN) and<br>all other faults low<br>OVP2<br>RUN<br>PT VCC_OVP high or  VDIM < VDIM(EN)<br>or  CS_stop  or  Aux_SCP<br>With states: RESET Controller is dead<br>OFF Controller is in OFF Mode, ICC = ICC(off) (50 A max.)<br>FAULT Mode No switching, ICC = ICC1<br>RUN Controller is switching<br>AR Mode the 4−s auto−recovery timer is counting, No switching<br>OVP2 Timer The OVP2 Timer (4−s or 1−s) is counting, No DRV pulses<br>**----- End of picture text -----**<br>


**Figure 13. Fault State Diagram with Auto−recovery Faults** 

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**----- Start of picture text -----**<br>
NCP1370<br>RESET<br>VCC < VCC(off)  or  BO_NOK high<br>or  VDIM < VDIM(EN) during 4 s<br>VCC too VddINT POR<br>low<br>in Timer ends (AR_end)  or BO_NOK edge<br>or  TSD_end  or  VCC < VCC(off)<br>OFF<br>BO_NOK edge<br>or TSD_end BO_NOK edge VDIM > VDIM(EN)<br>or VCC < VCC(off) or TSD_end and VCC > VCC(on)<br>or VCC < VCC(off)<br>Timer ends CS_short high<br>OVP2 or VDIM < VDIM(EN) AR LATCH<br>FAULT mode<br>Timer mode<br>ca ee<br>OVP2<br>VCC_OVP high<br>CS_OK VDIM > VDIM(EN) and<br>all other faults low<br>OVP2 VDIM < VDIM(EN)  or  Aux_SCP<br>RUN<br>VCC_OVP high  or  CS_stop<br>ES<br>With states: RESET Controller is dead<br>OFF Controller is in OFF Mode, ICC = ICC(off) (50 A max.)<br>FAULT Mode No switching, ICC = ICC1<br>RUN Controller is switching<br>AR Mode the 4−s auto−recovery timer is counting, No switching<br>OVP2 Timer The OVP2 Timer (4−s or 1−s) is counting, No DRV pulses<br>**----- End of picture text -----**<br>


**Figure 14. Fault State Diagram with Latched Faults** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package Type**|**Shipping**†|
|NCP1370BDR2G|SOIC−8<br>(Pb free)|2500 / Tape & Reel|



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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8<br>1<br>**----- End of picture text -----**<br>


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SCALE 1:1<br>**----- End of picture text -----**<br>


**SOIC−8 NB** CASE 751−07 ISSUE AK 

**==> picture [79 x 7] intentionally omitted <==**

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DATE 16 FEB 2011<br>**----- End of picture text -----**<br>


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NOTES:<br>−X− 1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>4 MAXIMUM MATERIAL CONDITION.<br>−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW<br>STANDARD IS 751−07.<br>G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>A 4.80 5.00 0.189 0.197<br>C N X 45 � B 3.80 4.00 0.150 0.157<br>SEATING C 1.35 1.75 0.053 0.069<br>PLANE D 0.33 0.51 0.013 0.020<br>−Z− G 1.27 BSC 0.050 BSC<br>H 0.10 0.25 0.004 0.010<br>0.10 (0.004) J 0.19 0.25 0.007 0.010<br>H D M J MK 0.400   � 1.278   � 0.0160   � 0.0508   �<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244<br>GENERIC<br>MARKING DIAGRAM*<br>SOLDERING FOOTPRINT*<br>8 8 8 8<br>XXXXX XXXXX XXXXXX XXXXXX<br>1.52 ALYWX ALYWX � AYWW AYWW �<br>0.060<br>1 1 1 1<br>IC IC Discrete Discrete<br>(Pb−Free) (Pb−Free)<br>7.0 4.0<br>XXXXX = Specific Device Code XXXXXX = Specific Device Code<br>0.275 0.155<br>A = Assembly Location A = Assembly Location<br>L = Wafer Lot Y = Year<br>Y = Year WW = Work Week<br>W = Work Week � = Pb−Free Package<br>� = Pb−Free Package<br>0.6 1.270 *This information is generic. Please refer to<br>0.024 0.050 device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ � ”, may<br>or may not be present. Some products may<br>SCALE 6:1<br>� inches [mm] � not follow the Generic Marking.<br>**----- End of picture text -----**<br>


- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

*For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

## **STYLES ON PAGE 2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 1 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**SOIC−8 NB** CASE 751−07 ISSUE AK 

**==> picture [79 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
DATE 16 FEB 2011<br>**----- End of picture text -----**<br>


|STYLE 1:|STYLE 1:|STYLE 2:||STYLE 3:|STYLE 3:||STYLE 4:|STYLE 4:|
|---|---|---|---|---|---|---|---|---|
|PIN 1.|EMITTER|PIN 1.|COLLECTOR, DIE, #1|PIN 1.||DRAIN, DIE #1|PIN 1.|ANODE|
|2.|COLLECTOR|2.|COLLECTOR, #1|2.||DRAIN, #1|2.|ANODE|
|3.|COLLECTOR|3.|COLLECTOR, #2|3.||DRAIN, #2|3.|ANODE|
|4.|EMITTER|4.|COLLECTOR, #2|4.||DRAIN, #2|4.|ANODE|
|5.|EMITTER|5.|BASE, #2|5.||GATE, #2|5.|ANODE|
|6.|BASE|6.|EMITTER, #2|6.||SOURCE, #2|6.|ANODE|
|7.|BASE|7.|BASE, #1|7.||GATE, #1|7.|ANODE|
|8.|EMITTER|8.|EMITTER, #1|8.||SOURCE, #1|8.|COMMON CATHODE|
|STYLE 5:||STYLE 6:||STYLE 7:|||STYLE 8:||
|PIN 1.|DRAIN|PIN 1.|SOURCE|PIN 1.||INPUT|PIN 1.|COLLECTOR, DIE #1|
|2.|DRAIN|2.|DRAIN|2.||EXTERNAL  BYPASS|2.|BASE, #1|
|3.|DRAIN|3.|DRAIN|3.||THIRD STAGE SOURCE|3.|BASE, #2|
|4.|DRAIN|4.|SOURCE|4.||GROUND|4.|COLLECTOR, #2|
|5.|GATE|5.|SOURCE|5.||DRAIN|5.|COLLECTOR, #2|
|6.|GATE|6.|GATE|6.||GATE 3|6.|EMITTER, #2|
|7.|SOURCE|7.|GATE|7.||SECOND STAGE Vd|7.|EMITTER, #1|
|8.|SOURCE|8.|SOURCE|8.||FIRST STAGE Vd|8.|COLLECTOR, #1|
|STYLE 9:||STYLE 10:||STYLE 11:|||STYLE 12:||
|PIN 1.|EMITTER,  COMMON|PIN 1.|GROUND|PIN 1.||SOURCE 1|PIN 1.|SOURCE|
|2.|COLLECTOR, DIE #1|2.|BIAS 1|2.||GATE 1|2.|SOURCE|
|3.|COLLECTOR, DIE #2|3.|OUTPUT|3.||SOURCE 2|3.|SOURCE|
|4.|EMITTER, COMMON|4.|GROUND|4.||GATE 2|4.|GATE|
|5.|EMITTER, COMMON|5.|GROUND|5.||DRAIN 2|5.|DRAIN|
|6.|BASE, DIE #2|6.|BIAS 2|6.||DRAIN 2|6.|DRAIN|
|7.|BASE, DIE #1|7.|INPUT|7.||DRAIN 1|7.|DRAIN|
|8.|EMITTER, COMMON|8.|GROUND|8.||DRAIN 1|8.|DRAIN|
|STYLE 13:||STYLE 14:||STYLE 15:|||STYLE 16:||
|PIN 1.|N.C.|PIN 1.|N−SOURCE|PIN 1.|ANODE 1||PIN 1.|EMITTER, DIE #1|
|2.|SOURCE|2.|N−GATE|2.|ANODE 1||2.|BASE, DIE #1|
|3.|SOURCE|3.|P−SOURCE|3.|ANODE 1||3.|EMITTER, DIE #2|
|4.|GATE|4.|P−GATE|4.|ANODE 1||4.|BASE, DIE #2|
|5.|DRAIN|5.|P−DRAIN|5.|CATHODE, COMMON||5.|COLLECTOR, DIE #2|
|6.|DRAIN|6.|P−DRAIN|6.|CATHODE, COMMON||6.|COLLECTOR, DIE #2|
|7.|DRAIN|7.|N−DRAIN|7.|CATHODE, COMMON||7.|COLLECTOR, DIE #1|
|8.|DRAIN|8.|N−DRAIN|8.|CATHODE, COMMON||8.|COLLECTOR, DIE #1|
|STYLE 17:||STYLE 18:||STYLE 19:|||STYLE 20:||
|PIN 1.|VCC|PIN 1.|ANODE|PIN 1.||SOURCE 1|PIN 1.|SOURCE (N)|
|2.|V2OUT|2.|ANODE|2.||GATE 1|2.|GATE (N)|
|3.|V1OUT|3.|SOURCE|3.||SOURCE 2|3.|SOURCE (P)|
|4.|TXE|4.|GATE|4.||GATE 2|4.|GATE (P)|
|5.|RXE|5.|DRAIN|5.||DRAIN 2|5.|DRAIN|
|6.|VEE|6.|DRAIN|6.||MIRROR 2|6.|DRAIN|
|7.|GND|7.|CATHODE|7.||DRAIN 1|7.|DRAIN|
|8.|ACC|8.|CATHODE|8.||MIRROR 1|8.|DRAIN|
|STYLE 21:||STYLE 22:||STYLE 23:|||STYLE 24:||
|PIN 1.|CATHODE 1|PIN 1.|I/O LINE 1|PIN 1.||LINE 1 IN|PIN 1.|BASE|
|2.|CATHODE 2|2.|COMMON CATHODE/VCC|2.||COMMON ANODE/GND|2.|EMITTER|
|3.|CATHODE 3|3.|COMMON CATHODE/VCC|3.||COMMON ANODE/GND|3.|COLLECTOR/ANODE|
|4.|CATHODE 4|4.|I/O LINE 3|4.||LINE 2 IN|4.|COLLECTOR/ANODE|
|5.|CATHODE 5|5.|COMMON ANODE/GND|5.||LINE 2 OUT|5.|CATHODE|
|6.|COMMON ANODE|6.|I/O LINE 4|6.||COMMON ANODE/GND|6.|CATHODE|
|7.|COMMON ANODE|7.|I/O LINE 5|7.||COMMON ANODE/GND|7.|COLLECTOR/ANODE|
|8.|CATHODE 6|8.|COMMON ANODE/GND|8.||LINE 1 OUT|8.|COLLECTOR/ANODE|
|STYLE 25:||STYLE 26:||STYLE|27:||STYLE 28:||
|PIN 1.|VIN|PIN 1.|GND|PIN 1.||ILIMIT|PIN 1.|SW_TO_GND|
|2.|N/C|2.|dv/dt|2.||OVLO|2.|DASIC_OFF|
|3.|REXT|3.|ENABLE|3.||UVLO|3.|DASIC_SW_DET|
|4.|GND|4.|ILIMIT|4.||INPUT+|4.|GND|
|5.|IOUT|5.|SOURCE|5.||SOURCE|5.|V_MON|
|6.|IOUT|6.|SOURCE|6.||SOURCE|6.|VBULK|
|7.|IOUT|7.|SOURCE|7.||SOURCE|7.|VBULK|
|8.|IOUT|8.|VCC|8.||DRAIN|8.|VIN|
|STYLE 29:||STYLE 30:|||||||
|PIN 1.|BASE, DIE #1|PIN 1.|DRAIN 1||||||
|2.|EMITTER, #1|2.|DRAIN 1||||||
|3.|BASE, #2|3.|GATE 2||||||
|4.|EMITTER, #2|4.|SOURCE 2||||||
|5.|COLLECTOR, #2|5.|SOURCE 1/DRAIN 2||||||
|6.|COLLECTOR, #2|6.|SOURCE 1/DRAIN 2||||||
|7.|COLLECTOR, #1|7.|SOURCE 1/DRAIN 2||||||
|8.|COLLECTOR, #1|8.|GATE 1||||||



Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 2 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

**www.onsemi.com** 

~~**2**~~ 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

**TECHNICAL PUBLICATIONS** : **ONLINE SUPPORT** : www.onsemi.com/support **Technical Library:** www.onsemi.com/design/resources/technical−documentation **For additional information, please contact your local Sales Representative at onsemi Website:** www.onsemi.com www.onsemi.com/support/sales 

**==> picture [232 x 43] intentionally omitted <==**

