NCL30486A1DR2G

## Dimmable Power Factor Corrected LED Driver 

## NCL30486 

The NCL30486 is a power factor corrected flyback controller targeting isolated constant current LED drivers. The controller operates in a quasi−resonant mode to provide high efficiency. Thanks to a novel control method, the device is able to tightly regulate a constant LED current from the primary side. This removes the need for secondary side feedback circuitry, its biasing and for an optocoupler. 

The device is highly integrated with a minimum number of external components. A robust suite of safety protection is built in to simplify the design. This device is specifically intended for very compact space efficient designs and supports analog and digital dimming with two dedicated dimming inputs control ideal for Smart LED Lighting applications. 

## **Features** 

- High Voltage Startup 

- Quasi−resonant Peak Current−mode Control Operation 

- Primary Side Feedback 

- CC / CV Accurate Control Vin up to 320 V rms 

- Tight LED Constant Current Regulation of ±2% Typical 

- Digital Power Factor Correction 

- Analog and Digital Dimming 

- Cycle by Cycle Peak Current Limit 

- Wide Operating VCC Range 

- −40 to + 125°C 

- Robust Protection Features 

   - ♦ Brown−Out 

   - ♦ OVP on VCC 

   - ♦ Constant Voltage / LED Open Circuit Protection 

   - ♦ Winding Short Circuit Protection 

   - ♦ Secondary Diode Short Protection 

   - ♦ Output Short Circuit Protection 

   - ♦ Thermal Shutdown 

   - ♦ Line over Voltage Protection 

- This is a Pb−Free Device 

## **Typical Applications** 

## **www.onsemi.com** 

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9<br>1<br>SOIC−9<br>CASE 751BP<br>MARKING<br>DIAGRAM<br>9<br>L30486XX<br>ALYWX<br>1<br>L30486 = Specific Device Code<br>XX = Version<br>A = Assembly Location<br>L = Wafer Lot<br>YW = Assembly Start Week<br>= Pb−Free Package<br>**----- End of picture text -----**<br>


## **PIN CONNECTIONS** 

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ADIM | 1 | 10 HV<br>COMP | 2<br>ZCD | 3 | | 8 PDIM<br>CS | 4 | 7 VCC<br>GND [ 5 | | 6 DRV<br>**----- End of picture text -----**<br>


- Integral LED Bulbs 

- LED Power Driver Supplies 

- LED Light Engines 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 27 of this data sheet. 

Publication Order Number: **NCL30486/D** 

**1** 

© Semiconductor Components Industries, LLC, 2020 **January, 2021 − Rev. 1** 

**NCL30486** 

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.<br>.<br>Aux<br>.<br>V ADIM<br>NCL30486<br>1 10<br>2 9<br>3 8<br>4 7<br>5 6<br>PWM signal<br>**----- End of picture text -----**<br>


**Figure 1. Typical Application Schematic for NCL30486** 

## **PIN FUNCTION DESCRIPTION NCL30486** 

|**Pin N**�|**Pin Name**|**Function**|**Pin Description**|
|---|---|---|---|
|1|ADIM|Analog dimming|This pin is used for analog control of the output current. Applying a voltage varying<br>between VDIM(EN)and VDIM100will dim the output current from 0% to 100%.|
|2|COMP|OTA output for CV loop|This pin receives a compensation network to stabilize the constant voltage loop|
|3|ZCD|Zero crossing Detection<br>Vauxsensing|This pin connects to the auxiliary winding and is used to detect the core reset event.<br>This pin also senses the auxiliary winding voltage for accurate output voltage control|
|4|CS|Current sense|This pin monitors the primary peak current.|
|5|GND|−|The controller ground|
|6|DRV|Driver output|The driver’s output to an external MOSFET|
|7|VCC|Supplies the controller|This pin is connected to an external auxiliary voltage.|
|8|PDIM|PWM dimming|This pin is used for PWM dimming control. An optocoupler can be connected directly<br>to the pin if the PWM control signal is from the secondary side|
|9|NC|creepage||
|10|HV|High Voltage sensing|This pin connects after the diode bridge to provide the startup current and internal<br>high voltage sensing function.|



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**2** 

**NCL30486** 

## **INTERNAL CIRCUIT ARCHITECTURE** 

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STOP<br>L_OVP VCC<br>COMP<br>Standby Aux_SCP Fault OFF<br>VCC Management<br>Fast_OVP Management UVLO<br>VCV Enable<br>Constant Voltage<br>Control Slow_OVPFast_OVP ShutdownThermal CS_short VCC_OVP VCCOVP StartupHV<br>VREFX VHVdiv Slow_OVP<br>dimCV_mode HV<br>BO_NOK Brown −Out<br>ZCD Zero crossing detection Logic(ZCD blanking, Time−Out,  … ) Valley Selection L_OVP Line OVP<br>Frequency foldback<br>Aux . Winding Short Circuit Prot . Aux_SCP VHVdiv<br>Q_drv<br>feed −forwardLine Q_drvVHVdiv Standby VDIMA VHVdiv dc_DIM S Q Driverand DRV<br>R Q Clamp<br>CS Leading Enable Power factor and VREFX<br>BlankingEdge STOP Constant −current control CS_reset<br>Max. Peak Ipk_max STOP Maximum<br>Current Limit on−time<br>Winding /<br>Output diode WOD_SCP ADIM<br>SCP VDIMA DimmingAnalog<br>dimCV_mode<br>CS Short Enable<br>Protection CS_short<br>GND<br>PDIM<br>PWM<br>dc_DIM<br>Dimming<br>dimCV_mode<br>**----- End of picture text -----**<br>


**Figure 2. Internal Circuit Architecture NCL30486** 

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**3** 

**NCL30486** 

## **MAXIMUM RATINGS TABLE** 

|**Symbol**|**Rating**|**Value**|**Unit**|
|---|---|---|---|
|VCC(MAX)<br>ICC(MAX)|Maximum Power Supply voltage, VCC pin, continuous voltage<br>Maximum current for VCC pin|−0.3 to 30<br>Internally limited|V<br>mA|
|VDRV(MAX)<br>IDRV(MAX)|Maximum driver pin voltage, DRV pin, continuous voltage<br>Maximum current for DRV pin|−0.3, VDRV(Note 1)<br>−300, +500|V<br>mA|
|VHV(MAX)<br>IHV(MAX)|Maximum voltage on HV pin<br>Maximum current for HV pin (dc current self−limited if operated within the allowed range)|−0.3, +700<br>±20|V<br>mA|
|VMAX<br>IMAX|Maximum voltage on low power pins (except pins DRV and VCC)<br>Current range for low power pins (except pins DRV and VCC)|−0.3, 5.5 (Note 2)<br>−2, +5|V<br>mA|
|RθJ−A|Thermal Resistance Junction−to−Air|210|°C/W|
|TJ(MAX)|Maximum Junction Temperature|150|°C|
||Operating Temperature Range|−40 to +125|°C|
||Storage Temperature Range|−60 to +150|°C|
||ESD Capability, HBM model except HV pin (Note 3)|4|kV|
||ESD Capability, HBM model HV pin|1.5|kV|
||ESD Capability, CDM model (Note 3)|1|kV|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise. 

2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages can be applied if the pin current stays within the −2 mA / 5 mA range. 

3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015. Charged Device Model 1000 V per JEDEC Standard JESD22−C101D. 

4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. 

**ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) 

|<br>For min/max values TJ= −40°C to +125°C, Max TJ= 15|<br>0°C, VCC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**HIGH VOLTAGE SECTION**|||||||
|High voltage current source|VCC= VCC(on)– 200 mV|IHV(start2)|3.9|5.1|6.2|mA|
|High voltage current source|VCC= 0 V|IHV(start1)|−|300|−|�A|
|VCClevel for IHV(start1)to IHV(start2)transition||VCC(TH)|−|0.8|−|V|
|Minimum startup voltage|VCC= 0 V|VHV(MIN)|−|17|−|V|
|HV source leakage current|VHV= 450 V|IHV(leak)|−|4.5|10|�A|
|Maximum input voltage (rms) for correct operation of<br>the PFC loop||VHV(OL)|320|−|−|V rms|
|**SUPPLY SECTION**|||||||
|Supply Voltage<br>Startup Threshold<br>Minimum Operating Voltage<br>Hysteresis VCC(on)– VCC(off)<br>Internal logic reset|VCCincreasing<br>VCCdecreasing<br>VCCdecreasing|VCC(on)<br>VCC(off)<br>VCC(HYS)<br>VCC(reset)|16<br>9.3<br>7.6<br>4|18<br>10.2<br>−<br>5|20<br>10.7<br>−<br>6|V|
|Over Voltage Protection<br>VCC OVP threshold||VCC(OVP)|25|26.5|28|V|
|VCC(off)noise filter (Note 5)<br>VCC(reset)noise filter (Note 5)||tVCC(off)<br>tVCC(reset)|−<br>−|5<br>20|−<br>−|�s|
|Supply Current<br>Device Disabled/Fault<br>Device Enabled/No output load on pin 5<br>Device Switching (Fsw= 65 kHz)<br>Device switching (Fsw= 700 Hz)|VCC> VCC(off)<br>Fsw= 65 kHz<br>CDRV= 470 pF, Fsw= 65 kHz<br>VCOMP �0.9 V|ICC1<br>ICC2<br>ICC3<br>ICC4|1.2<br>–<br>−<br>−|1.35<br>3.0<br>3.5<br>1.7|1.6<br>3.5<br>4.0<br>1.88|mA|



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**4** 

## **NCL30486** 

**ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) (continued) 

|<br>For min/max values TJ= −40°C to +125°C, Max TJ= 15|<br>0°C, VCC= 12 V) (continued)||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**CURRENT SENSE**|||||||
|Maximum Internal current limit||VILIM|1.33|1.40|1.47|V|
|Leading Edge Blanking Duration for VILIM||tLEB|283|345|407|ns|
|Propagation delay from current detection to gate<br>off−state||tILIM|−|100|150|ns|
|Maximum on−time (option 1)||ton(MAX)|29|39|49|�s|
|Maximum on−time (option 2)||ton(MAX)|16|20|24|�s|
|Threshold for immediate fault protection activation<br>(140% of VILIM)||VCS(stop)|1.9|2.0|2.1|V|
|Leading Edge Blanking Duration for VCS(stop)||tBCS|−|170|−|ns|
|Current source for CS to GND short detection||ICS(short)|400|500|600|�A|
|Current sense threshold for CS to GND short<br>detection|VCSrising|VCS(low)|20|60|90|mV|
|**GATE DRIVE**|||||||
|Drive Resistance<br>DRV Sink<br>DRV Source||RSNK<br>RSRC|−<br>−|13<br>30|−<br>−|�|
|Drive current capability<br>DRV Sink (Note GBD)<br>DRV Source (Note GBD)||ISNK<br>ISRC|−<br>−|500<br>300|−<br>−|mA|
|Rise Time (10% to 90%)|CDRV= 470 pF|tr|–|30|−|ns|
|Fall Time (90 %to 10%)|CDRV= 470 pF|tf|–|20|−|ns|
|DRV Low Voltage|VCC= VCC(off)+0.2 V<br>CDRV= 470 pF, RDRV= 33 k�|VDRV(low)|8|–|−|V|
|DRV High Voltage|VCC= VCC(MAX)<br>CDRV= 470 pF, RDRV= 33 k�|VDRV(high)|10|12|14|V|
|**ZERO VOLTAGE DETECTION CIRCUIT**|||||||
|Upper ZCD threshold voltage|VZCDrising|VZCD(rising)|−|90|150|mV|
|Lower ZCD threshold voltage|VZCDfalling|VZCD(falling)|35|55|−|mV|
|Threshold to force VREFXmaximum during startup||VZCD(start)|−|0.7|−|V|
|ZCD hysteresis||VZCD(HYS)|15|−|−|mV|
|Propagation Delay from valley detection to DRV high<br>(no tLEB4)|VZCDdecreasing|tZCD(DEM)|−|−|150|ns|
|Additional delay from valley lockout output to DRV<br>latch set (prog option)||tLEB4|125|250|375|ns|
|Equivalent time constant for ZCD input (GBD)||tPAR|−|20|−|ns|
|Blanking delay after on−time (option 1)|VREFX> 0.35 V|tZCD(blank1)|1.1|1.5|1.9|�s|
|Blanking delay after on−time (option 2)|VREFX> 0.35 V|tZCD(blank1)|0.75|1.0|1.25|�s|
|Blanking Delay at light load (option 1)|VREFX< 0.25 V|tZCD(blank2)|0.6|0.8|1.0|�s|
|Blanking Delay at light load (option 2)|VREFX< 0.25 V|tZCD(blank2)|0.45|0.6|0.75|�s|
|Timeout after last DEMAG transition||tTIMO|5|6.5|8|�s|
|Pulling−down resistor|VZCD= VZCD(falling)|RZCD(pd)|−|200|−|k�|
|ZCD pin current source for forcing CV mode when<br>minimum dimming|VADIM= 0.5 V|IZCDdim|145|170|195|�A|



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**5** 

## **NCL30486** 

**ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) (continued) 

|<br>For min/max values TJ= −40°C to +125°C, Max TJ= 15|<br>0°C, VCC= 12 V) (continued)||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**CONSTANT CURRENT CONTROL**|||||||
|Reference Voltage|Tj= 25°C − 85°C|VREF/3|327.9|334.2|341.2|mV|
|Reference Voltage|Tj= −40°C to 125°C|VREF/3|324|334.2|346|mV|
|10% Reference Voltage|Tj= 25°C − 85°C|VREF10/3|30|33.33|36.66|mV|
|10% Reference Voltage|Tj= −40°C to 125°C|VREF10/3|27.33|33.33|39.33|mV|
|5% Reference Voltage|Tj= 25°C − 85°C|VREF05/3|14.17|17|19.17|mV|
|5% Reference Voltage|Tj= −40°C to 125°C|VREF05/3|13.34|17|20|mV|
|Current sense lower threshold for detection of the<br>leakage inductance reset time|VCSfalling|VCS(low)|20|50|100|mV|
|Blanking time for leakage inductance reset detection||tCS(low)|−|120|−|ns|
|**POWER FACTOR CORRECTION**|||||||
|Clamping value for VREF(PFC)|TJ= 0°C to 125°C|VREF(PFC)CLP|2.06|2.2|2.34|V|
|Line range detector for PFC loop|VHVincreases|VHL(PFC)|−|240|−|Vdc|
|Line range detector for PFC loop|VHVdecreases|VLL(PFC)|−|230|−|Vdc|
|**CONSTANT VOLTAGE SECTION**|||||||
|Internal voltage reference for constant voltage<br>regulation||VREF(CV)|3.41|3.52|3.63|V|
|CV Error amplifier Gain||GEA|40|50|60|�S|
|Error amplifier current capability|VREFX= VREF(no dimming)|IEA|−|±60|−|�A|
|COMP pin lower clamp voltage||VCV(clampL)|−|0.6|−|V|
|COMP pin higher clamp voltage|TJ= 0°C to 125°C|VCV(clampH)|4.05|4.12|4.25|V|
|COMP pin higher clamp voltage|TJ= −40°C to 125°C|VCV(clampH)|4.01|4.12|4.25|V|
|Internal ZCD voltage below which the CV OTA is<br>boosted|VREF(CV)* 85%|Vboost(CV)|2.796|2.975|3.154|V|
|Threshold for releasing the CV boost|VREF(CV)* 90%|Vboost(CV)RST|2.96|3.15|3.34|V|
|Internal ZCD voltage below which the CV OTA is<br>boosted (opt.2)|VREF(CV)* 80%|Vboost(CV)2|2.632|2.8|2.968|V|
|Error amplifier current capability during boost phase||IEAboost|−|±140|−|�A|
|ZCD OVP 1stlevel (slow OVP) option 1|VREF(CV)* 115%|VOVP1|3.783|4.025|4.267|V|
|ZCD OVP 1stlevel (slow OVP) option 2|VREF(CV)* 120%|VOVP1|3.948|4.2|4.452|V|
|ZCD voltage at which slow OVP is exit (option 1)|VREF(CV)* 105%|VOVP1rst|−|3.675|−|V|
|ZCD voltage at which slow OVP is exit (option 2)|VREF(CV)* 110%|VOVP1rst|−|3.85|−|V|
|Switching period during slow OVP||Tsw(OVP1)|−|1.5|−|ms|
|ZCD fast OVP option 2|Vref(CV)* 130% + 150 mV|VOVP2|−|4.7|−|V|
|ZCD fast OVP option 1|Vref(CV)* 125% + 150 mV|VOVP2|4.253|4.525|4.797|V|
|Number of switching cycles before fast OVP<br>confirmation||TOVP2_CNT|−|4|−||
|Duration for disabling DRV pulses during ZCD fast<br>OVP||Trecovery|−|4|−|s|
|COMP pin internal pullup resistor (prog option)||Rpullup|−|15|−|k�|
|**LINE FEED FORWARD**|||||||
|VHVto ICS(offset)conversion ratio||KLFF|0.189|0.21|0.231|�A/V|
|Offset current maximum value|VHV> (450 V or 500 V)|Ioffset(MAX)|76|95|114|�A|
|Line feed−forward current|DRV high, VHV= 200 V|IFF|35|40|45|�A|



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**6** 

## **NCL30486** 

**ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) (continued) 

|<br>For min/max values TJ= −40°C to +125°C, Max TJ= 15|<br>0°C, VCC= 12 V) (continued)||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**VALLEY LOCKOUT SECTION**|||||||
|Threshold for line range detection VHVincreasing<br>(1stto 2ndvalley transition for VREFX> 80% VREF)<br>(prog. option: 1stto 3rdvalley transition)|VHVincreases|VHL|228|240|252|V|
|Threshold for line range detection VHVdecreasing<br>(2ndto 1stvalley transition for VREFX> 80% VREF)<br>(prog. option: 3rdto 1stvalley transition)|VHVdecreases|VLL|218|230|242|V|
|Blanking time for line range detection||tHL(blank)|15|25|35|ms|
|Valley thresholds<br>1stto 2ndvalley transition at LL and 2ndto 3rdvalley<br>HL, VREFdecr. (prog. option: 3rdto 4thvalley HL)<br>2ndto 1stvalley transition at LL and 3rdto 2ndvalley<br>HL, VREFincr. (prog. option: 4thto 3rdvalley HL)<br>2ndto 3rdvalley transition at LL and 3rdto 4thvalley<br>HL, VREFdecr. (prog. option: 4thto 5thvalley HL)<br>3rdto 2ndvalley transition at LL and 4thto 3rdvalley<br>HL, VREFincr. (prog. option: 5thto 4thvalley HL)<br>3rdto 4thvalley transition at LL and 4thto 5thvalley<br>HL, VREFdecr. (prog. option: 5thto 6thvalley HL)<br>4thto 3thvalley transition at LL and 5thto 4thvalley<br>HL, VREFincr. (prog. option: 6thto 5thvalley HL)<br>4thto 5thvalley transition at LL and 5thto 6thvalley<br>HL, VREFdecr. (prog. option: 6thto 7thvalley HL)<br>5thto 4thvalley transition at LL and 6thto 5thvalley<br>HL, VREFincr. (prog. option: 7thto 6thvalley HL)|VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases|VVLY1−2/2−3<br>VVLY2−1/3−2<br>VVLY2−3/3−4<br>VVLY3−2/4−3<br>VVLY3−4/4−5<br>VVLY4−3/5−4<br>VVLY4−5/5−6<br>VVLY5−4/6−5|−<br>−<br>−<br>−<br>−<br>−<br>−<br>−|0.80<br>0.90<br>0.65<br>0.75<br>0.50<br>0.60<br>0.35<br>0.45|−<br>−<br>−<br>−<br>−<br>−<br>−<br>−|V|
|VREFvalue at which the FF mode is activated|VREFdecreases|VFFstart|−|0.25|−|V|
|VREFvalue at which the FF mode is removed|VREFincreases|VFFstop|−|0.35|−|V|
|**FREQUENCY FOLDBACK**|||||||
|Added dead time|VREFX= 0.25 V|tFF1LL|0.8|1.0|1.2|�s|
|Added dead time|VREFX= 0.08 V|tFFchg|−|40|−|�s|
|Dead−time clamp ( option 1)|VREFX< 3 mV|tFFend1|−|675|−|�s|
|Dead−time clamp ( option 2)|VREFX< 11.2 mV|tFFend2|−|250|−|�s|
|**DIMMING SECTION**|||||||
|DIM pin voltage for zero output current (OFF voltage)||VADIM(EN)|0.475|0.5|0.525|V|
|ADIM pin voltage for 1% reference voltage||VADIM(MIN)|0.668|0.7|0.732|V|
|Minimum dimming level (option 1)||KDIM(MIN)1|−|0|−|%|
|Minimum dimming level (option 2)||KDIM(MIN)2|−|1|−|%|
|Minimum dimming level (option 3)||KDIM(MIN)3|−|5|−|%|
|Minimum dimming level (option 4)||KDIM(MIN)4|−|8|−|%|
|ADIM pin voltage for maximum output current<br>(VREFX= 1 V)||VADIM100|−|3.0|3.1|V|
|Dimming range||VADIM(range)|−|2.3|−|V|
|Clamping voltage for DIM pin||VADIM(CLP)|−|6.8|−|V|
|Dimming pin pull−up current source||IADIM(pullup)1|8|10|12|�A|
|Current Comparator threshold for PDIM|IPDIMrising|IPDIM(THR)|60|70|80|�A|
|Current Comparator threshold for PDIM|IPDIMfalling|IPDIM(THD)|131|153|175|�A|
|Cascode current limit for PDIM||IPDIM(LIM)|−|1080|−|�A|
|PDIM pin voltage||VPDIM|−|3|−|V|
|Maximum period of the PWM dimming signal|||−|6|−|ms|
|Minimum on−time for PWM signal applied on PDIM|||−|8|−|�s|



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**7** 

## **NCL30486** 

**ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) (continued) 

|<br>For min/max values TJ= −40°C to +125°C, Max TJ= 15|<br>0°C, VCC= 12 V) (continued)||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**FAULT PROTECTION**|||||||
|Thermal Shutdown (Note 5)|Device switching (FSW<br>around 65 kHz)|TSHDN|130|150|170|°C|
|Thermal Shutdown Hysteresis||TSHDN(HYS)|−|20|–|°C|
|Threshold voltage for output short circuit or aux.<br>winding short circuit detection||VZCD(short)|0.6|0.65|0.7|V|
|Short circuit detection Timer|VZCD< VZCD(short)|tOVLD|70|90|110|ms|
|Auto−recovery Timer||trecovery|3|4|5|s|
|Line OVP threshold|VHVincreasing|VHV(OVP)|457|469|485|Vdc|
|HV pin voltage at which Line OVP is reset|VHVdecreasing|VHV(OVP)RST|430|443|465|Vdc|
|Blanking time for line OVP reset||TLOVP(blank)|15|25|35|ms|
|**BROWN−OUT AND LINE SENSING**|||||||
|Brown−Out ON level (IC start pulsing)|VHVincreasing|VHVBO(on)|101.5|108|114.5|Vdc|
|Brown−Out ON level (IC start pulsing) option 2|VHVincreasing|VHVBO(on)2|129.7|138|146.3|Vdc|
|Brown−Out OFF level (IC stops pulsing)|VHVdecreasing|VHVBO(off)|92|98|104|Vdc|
|Brown−Out OFF level (IC stops pulsing) option 2|VHVdecreasing|VHVBO(off)2|121|129|137|Vdc|
|HV pin voltage above which the sampling of ZCD is<br>enabled low line|VHVdecreasing, low line|VsampENLL|−|55|−|V|
|HV pin voltage above which the sampling of ZCD is<br>enabled highline|VHVdecreasing, highline|VsampENHL|−|105|−|V|
|ZCD sampling enable comparator hysteresis|VHVincreasing|VsampHYS|−|5|−|V|
|BO comparators delay||tBO(delay)|−|30|−|�s|
|Brown−Out blanking time||tBO(blank)|15|25|35|ms|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Guaranteed by design. 

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**8** 

**NCL30486** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
5,4<br>309<br>5,3<br>5,2 304<br>5,1<br>5 299<br>4,9<br>294<br>4,8<br>4,7<br>289<br>4,6<br>4,5 284<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br>A)<br>�<br> (mA)  (<br>IHV(start2) IHV(start1)<br>**----- End of picture text -----**<br>


**Figure 3. IHV(start2) vs. Temperature** 

**Figure 4. IHV(start1) vs. Temperature** 

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**----- Start of picture text -----**<br>
361<br>18,34<br>359<br>357 18,29<br>355<br>18,24<br>353<br>18,19<br>351<br>349 18,14<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br>Figure 5. VHV(OL) vs. Temperature Figure 6. VCC(on) vs. Temperature<br>10,25<br>26,96<br>10,23<br>26,91<br>10,21<br>10,19 26,86<br>10,17 26,81<br>10,15 26,76<br>10,13 26,71<br>10,11 26,66<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (V)<br> (V rms)<br>CC(on)<br>HV(OL) V<br>V<br> (V)<br> (V)<br>CC(off)<br>V CC(OVP)<br>V<br>**----- End of picture text -----**<br>


**Figure 7. VCC(off) vs. Temperature** 

**Figure 8. VCC(OVP) vs. Temperature** 

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**9** 

**NCL30486** 

## **TYPICAL CHARACTERISTICS** (continued) 

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**----- Start of picture text -----**<br>
1,41 1,7<br>1,69<br>1,39<br>1,68<br>1,37<br>1,67<br>1,35 1,66<br>1,65<br>1,33<br>1,64<br>1,31<br>1,63<br>1,29 1,62<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (mA)  (mA)<br>ICC1 ICC4<br>**----- End of picture text -----**<br>


**Figure 9. ICC1 vs. Temperature** 

**Figure 10. ICC4 vs. Temperature** 

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**----- Start of picture text -----**<br>
1,2<br>54<br>1,15<br>53,5<br>1,1<br>1,05 53<br>1 52,5<br>0,95<br>52<br>0,9<br>51,5<br>0,85<br>51<br>0,8<br>0,75 50,5<br>0,7 50<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br>Figure 11. VILIM vs. Temperature Figure 12. VCS(low)F vs. Temperature<br>2,06<br>20,24<br>2,04<br>20,19<br>2,02 20,14<br>20,09<br>2<br>20,04<br>1,98 19,99<br>19,94<br>1,96<br>19,89<br>1,94 19,84<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (mV)<br> (V)<br>ILIM<br>V<br>CS(low)F<br>V<br> (V)  (ms)<br>CS(stop)<br>V ton(MAX)2<br>**----- End of picture text -----**<br>


**Figure 13. VCS(stop) vs. Temperature** 

**Figure 14. ton(MAX)2 vs. Temperature** 

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**10** 

**NCL30486** 

## **TYPICAL CHARACTERISTICS** (continued) 

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359<br>354<br>349<br>344<br>339<br>334<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (ns)<br>tLEB<br>**----- End of picture text -----**<br>


**Figure 15. tLEB vs. Temperature** 

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**----- Start of picture text -----**<br>
180<br>179<br>178<br>177<br>176<br>175<br>174<br>173<br>172<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (ns)<br>tBCS<br>**----- End of picture text -----**<br>


**Figure 16. tBCS vs. Temperature** 

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**----- Start of picture text -----**<br>
120<br>110<br>100<br>90<br>80<br>70<br>60<br>50<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (ns)<br>tILIM<br>**----- End of picture text -----**<br>


**Figure 17. tILIM vs. Temperature** 

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**----- Start of picture text -----**<br>
10,5<br>9,5<br>8,5<br>7,5<br>6,5<br>5,5<br>4,5<br>3,5<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br>) �<br> (<br>SNK<br>R<br>**----- End of picture text -----**<br>


**Figure 18. RSNK vs. Temperature** 

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**----- Start of picture text -----**<br>
34<br>15,5<br>32<br>13,5 30<br>11,5 28<br>26<br>9,5<br>24<br>7,5<br>22<br>5,5 20<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br>) �<br> (SRC  (ns)tr<br>R<br>**----- End of picture text -----**<br>


**Figure 19. RSRC vs. Temperature** 

**Figure 20. tr vs. Temperature** 

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**11** 

**NCL30486** 

## **TYPICAL CHARACTERISTICS** (continued) 

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**----- Start of picture text -----**<br>
21,5 83<br>20,5 82,5<br>19,5 82<br>18,5<br>81,5<br>17,5<br>81<br>16,5<br>80,5<br>15,5<br>80<br>14,5<br>13,5 79,5<br>12,5 79<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (mV)<br> (ns)<br>tF<br>ZCD(rising)<br>V<br>**----- End of picture text -----**<br>


**Figure 21. tf vs. Temperature** 

**Figure 22. VZCD(rising) vs. Temperature** 

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**----- Start of picture text -----**<br>
0,672<br>54,5<br>0,67<br>53,5 0,668<br>52,5 0,666<br>0,664<br>51,5<br>0,662<br>50,5<br>0,66<br>49,5 0,658<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br>Figure 23. VZCD(falling) vs. Temperature Figure 24. VZCD(short) vs. Temperature<br>116<br>1,605<br>111<br>106 1,595<br>101<br>1,585<br>96<br>91 1,575<br>86<br>1,565<br>81<br>76 1,555<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (mV)  (V)<br>ZCD(falling) VZCD(short)<br>V<br>s)<br>�<br> (ns)  (<br>tZCD(DEM)<br>tZCD(blank1)OPN1<br>**----- End of picture text -----**<br>


**Figure 25. tZCD(dem) vs. Temperature** 

**Figure 26. tZCD(blank1)OPN1 vs. Temperature** 

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**12** 

**NCL30486** 

## **TYPICAL CHARACTERISTICS** (continued) 

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1,072<br>1,067<br>1,062<br>1,057<br>1,052<br>1,047<br>1,042<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br>s)<br>�<br> (<br>tZCD(blank1)OPN2<br>**----- End of picture text -----**<br>


**Figure 27. tZCD(blank1)OPN2 vs. Temperature** 

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**----- Start of picture text -----**<br>
0,861<br>0,856<br>0,851<br>0,846<br>0,841<br>0,836<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br>s)<br>�<br> (<br>tZCD(blank2)OPN1<br>**----- End of picture text -----**<br>


**Figure 28. tZCD(blank2)OPN1 vs. Temperature** 

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**----- Start of picture text -----**<br>
0,584 6,92<br>0,579 6,87<br>0,574 6,82<br>0,569 6,77<br>0,564 6,72<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br>Figure 29. tZCD(blank2)OPN2 vs. Temperature Figure 30. tTIMO vs. Temperature<br>336,8<br>336,3<br>34,6<br>335,8<br>335,3<br>34,1<br>334,8<br>334,3<br>333,8 33,6<br>333,3<br>332,8 33,1<br>332,3<br>331,8 32,6<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br>s)<br>�<br> (<br>s)<br>�<br> (<br>tTIMO<br>tZCD(blank2)OPN2<br> (mV)<br> (mV)<br>REF/3<br>V REF10/3<br>V<br>**----- End of picture text -----**<br>


**Figure 31. VREF/3 vs. Temperature** 

**Figure 32. VREF10/3 vs. Temperature** 

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**13** 

**NCL30486** 

## **TYPICAL CHARACTERISTICS** (continued) 

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**----- Start of picture text -----**<br>
3,545<br>17,7<br>3,535<br>17,5<br>3,525<br>17,3<br>3,515<br>17,1<br>3,505<br>16,9<br>16,7 3,495<br>16,5 3,485<br>16,3 3,475<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (mV)  (V)<br>REF5/3 REF(CV)<br>V V<br>**----- End of picture text -----**<br>


**Figure 33. VREF5/3 vs. Temperature** 

**Figure 34. VREF(CV) vs. Temperature** 

**==> picture [479 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
4,15<br>4,075<br>4,14<br>4,065<br>4,13 4,055<br>4,12 4,045<br>4,035<br>4,11<br>4,025<br>4,1<br>4,015<br>4,09<br>4,005<br>4,08 3,995<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (V)<br> (V)<br>OVP1<br>V<br>CV(clampH)<br>V<br>**----- End of picture text -----**<br>


**Figure 35. VCV(clampH) vs. Temperature** 

**Figure 36. VOVP1 vs. Temperature** 

**==> picture [479 x 162] intentionally omitted <==**

**----- Start of picture text -----**<br>
0,2095<br>4,54 0,2085<br>0,2075<br>4,53<br>0,2065<br>4,52 0,2055<br>0,2045<br>4,51<br>0,2035<br>0,2025<br>4,5<br>0,2015<br>4,49 0,2005<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (V) A/V)<br>�<br> (<br>OVP2<br>V LFF<br>K<br>**----- End of picture text -----**<br>


**Figure 37. VOVP2 vs. Temperature** 

**Figure 38. KLFF vs. Temperature** 

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**14** 

**NCL30486** 

## **TYPICAL CHARACTERISTICS** (continued) 

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**----- Start of picture text -----**<br>
104<br>41,7<br>103<br>41,5<br>102<br>41,3<br>101<br>41,1<br>100<br>40,9<br>99<br>40,7<br>98 40,5<br>97 40,3<br>96 40,1<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br>A)<br>�<br> ( A)<br>�<br> (<br>IFF<br>Ioffset(MAX)<br>**----- End of picture text -----**<br>


**Figure 39. Ioffset(MAX) vs. Temperature** 

**Figure 40. IFF vs. Temperature** 

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**----- Start of picture text -----**<br>
1,0395<br>1,0385 2,208<br>1,0375 2,203<br>1,0365 2,198<br>1,0355 2,193<br>1,0345 2,188<br>1,0335 2,183<br>1,0325 2,178<br>1,0315 2,173<br>1,0305 2,168<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (V)<br>s)<br>�<br> (<br>tFF1LL<br>REF(PFC)CLP<br>V<br>**----- End of picture text -----**<br>


**Figure 41. tFF1LL vs. Temperature** 

**Figure 42. VREF(PFC)CLP vs. Temperature** 

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**----- Start of picture text -----**<br>
0,5055 0,708<br>0,5045 0,706<br>0,5035<br>0,704<br>0,5025<br>0,702<br>0,5015<br>0,7<br>0,5005<br>0,698<br>0,4995<br>0,696<br>0,4985<br>0,4975 0,694<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br> (V)  (V)<br>ADIM(EN) ADIM(MIN)<br>V V<br>**----- End of picture text -----**<br>


**Figure 43. VADIM(EN) vs. Temperature** 

**Figure 44. VADIM(MIN) vs. Temperature** 

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**15** 

**NCL30486** 

## **TYPICAL CHARACTERISTICS** (continued) 

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**----- Start of picture text -----**<br>
71,6 153,2<br>152,7<br>71,1 152,2<br>151,7<br>70,6 151,2<br>150,7<br>70,1 150,2<br>149,7<br>69,6 149,2<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C) TEMPERATURE ( ° C)<br>A) A)<br>� �<br> (  (<br>IPDIM(THR) IPDIM(THD)<br>**----- End of picture text -----**<br>


**Figure 45. IPDIM(THR) vs. Temperature** 

**Figure 46. IPDIM(THD) vs. Temperature** 

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**----- Start of picture text -----**<br>
1,086<br>1,081<br>1,076<br>1,071<br>1,066<br>1,061<br>1,056<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (mA)<br>IPDIM(LIM)<br>**----- End of picture text -----**<br>


**Figure 47. IPDIM(LIM) vs. Temperature** 

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**----- Start of picture text -----**<br>
3,013<br>3,008<br>3,003<br>2,998<br>2,993<br>2,988<br>2,983<br>2,978<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (V)<br>PDIM<br>V<br>**----- End of picture text -----**<br>


**Figure 48. VPDIM vs. Temperature** 

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**----- Start of picture text -----**<br>
3,011<br>3,006<br>3,001<br>2,996<br>2,991<br>2,986<br>2,981<br>2,976<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (V)<br>ADIM100<br>V<br>**----- End of picture text -----**<br>


**Figure 49. VADIM100 vs. Temperature** 

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**----- Start of picture text -----**<br>
108,9<br>108,7<br>108,5<br>108,3<br>108,1<br>107,9<br>107,7<br>107,5<br>107,3<br>107,1<br>106,9<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (V)<br>HVBO(on)OPN1<br>V<br>**----- End of picture text -----**<br>


**Figure 50. VHVBO(on)ONP1 vs. Temperature** 

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**16** 

**NCL30486** 

## **TYPICAL CHARACTERISTICS** (continued) 

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**----- Start of picture text -----**<br>
99,6<br>99,4<br>99,2<br>99<br>98,8<br>98,6<br>98,4<br>98,2<br>98<br>97,8<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (V)<br>HVBO(off)OPN1<br>V<br>**----- End of picture text -----**<br>


**Figure 51. VHVBO(off)ONP1 vs. Temperature** 

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**----- Start of picture text -----**<br>
472<br>471<br>470<br>469<br>468<br>467<br>466<br>465<br>464<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (V dc)<br>HV(OVP)<br>V<br>**----- End of picture text -----**<br>


**Figure 52. VHV(OVP) vs. Temperature** 

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**----- Start of picture text -----**<br>
446<br>445<br>444<br>443<br>442<br>441<br>440<br>439<br>−50 −25 0 25 50 75 100 125<br>TEMPERATURE ( ° C)<br> (V dc)<br>HV(OVP)RST<br>V<br>**----- End of picture text -----**<br>


**Figure 53. VHV(OVP)RST vs. Temperature** 

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**17** 

**NCL30486** 

## **Application Information** 

The NCL30486 implements a current−mode architecture operating in quasi−resonant mode. Thanks to proprietary circuitry, the controller is able to accurately regulate the secondary side current and voltage of the fly−back converter without using any opto−coupler or measuring directly the secondary side current or voltage. The controller provides near unity power factor correction 

- _Quasi−Resonance Current−Mode Operation:_ implementing quasi−resonance operation in peak current−mode control, the NCL30486 optimizes the efficiency by switching in the valley of the MOSFET drain−source voltage. Thanks to an internal algorithm control, the controller locks−out in a selected valley and remains locked until the input voltage or the output current set point significantly changes. 

- _Primary Side Constant Current Control:_ thanks to a proprietary circuit, the controller is able to take into account the effect of the leakage inductance of the transformer and allows an accurate control of the secondary side current regardless of the input voltage and output load variation. 

- _Primary Side Constant Voltage Regulation:_ By monitoring the auxiliary winding voltage, it is possible to regulate accurately the output voltage. The output voltage regulation is typically within ±2%. 

- _Load Transient Compensation:_ Since PFC has low loop bandwidth, abrupt changes in the load may cause excessive over or under−shoot. The slow Over Voltage Protection contains the output voltage when it tends to become excessive. In addition, the NCL30486 speeds up the constant voltage regulation loop when the output voltage goes below 80% or 85% of its regulation level. 

- _Power Factor Correction:_ A proprietary concept allows achieving high power factor correction and low THD while keeping accurate constant current and constant voltage control. 

- _Line Feed−forward:_ allows compensating the variation of the output current caused by the propagation delay. 

- _VCC Over Voltage Protection:_ if the VCC pin voltage exceeds an internal limit, the controller shuts down and waits 4 seconds before restarting pulsing. 

- _Fast Over Voltage Protection:_ If the voltage of ZCD pin exceeds 130% of its regulation level, the controller shuts down and waits 4 s before trying to restart. 

- _Brown−Out:_ the controller includes a brown−out circuit which safely stops the controller in case the input voltage is too low. The device will automatically restart if the line recovers. 

- _Cycle−by−cycle peak current limit:_ when the current sense voltage exceeds the internal threshold VILIM, the MOSFET is turned off for the rest of the switching cycle. 

if VCS reaches 1.5 x VILIM (after a reduced LEB of tBCS). This additional comparator is enabled only during the main LEB duration tLEB, for noise immunity reason. 

- _Output Under Voltage Protection:_ If a too low voltage is applied on ZCD pin for 90 ms time interval, the controllers assume that the output or the ZCD pin is shorted to ground and shutdown. After waiting 4 seconds, the IC restarts switching. 

- _Analog Dimming:_ the ADIM pin is dedicated to analog dimming. There are several options for the minimum dimming level. Pulling the pin voltage lower than VADIM(EN) disables the controller. 

- _PWM dimming:_ the PDIM pin is dedicated to PWM dimming. The controller measures the duty ratio of a signal applied to the pin and reduces the output current accordingly. If this pin is left open, the controller delivers the maximum output current. If the pin is pulled down, the controller is disabled. 

- _Thermal Shutdown:_ an internal circuitry disables the gate drive when the junction temperature exceeds 150°C (typically). The circuit resumes operation once the temperature drops below approximately 100°C. 

## **POWER FACTOR AND CONSTANT CURRENT CONTROL** 

The NCL30486 embeds an analog/digital block to control the power factor and regulate the output current by monitoring the ZCD, CS and HV pin voltages (signals VZCD, VHV_DIV, VCS). This circuit generates the current setpoint signal and compares it to the current sense signal to turn the MOSFET off. The HV pin provides the sinusoidal reference necessary for shaping the input current. The obtained current reference is further modulated so that when averaged over a half line period, it is equal to the output current reference (VREFX). The modulation and averaging process is made internally by a digital circuit. If the HV pin properly conveys the sinusoidal shape, power factor will be close to 1. Also, the Total Harmonic Distortion (THD) will be low especially if the output voltage ripple is small. 

**==> picture [225 x 24] intentionally omitted <==**

Where: 

- Nsp is the secondary to primary transformer turns ratio: Nsp = NS / NP 

- Rsense is the current sense resistor 

- VREFX is the output current reference: VREFX = VREF if no dimming 

The output current reference (VREFX) is VREF unless the constant voltage mode is activated or ADIM pin voltage is below VADIM(100) or a PWM signal with a duty−cycle below 95% is applied on PDIM. 

- _Winding Short−Circuit Protection:_ an additional comparator senses the CS signal and stops the controller 

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**18** 

**NCL30486** 

## **PRIMARY SIDE CONSTANT VOLTAGE CONTROL** 

The auxiliary winding voltage is sampled internally through the ZCD pin. 

A precise internal voltage reference VREF(CV) sets the voltage target for the CV loop. 

The sampled voltage is applied to the negative input of the constant voltage (CV) operational transconductance amplifier (OTA) and compared to VREFCV. 

A type 2 compensator is needed at the CV OTA output to stabilize the loop. The COMP pin voltage modify the the output current internal reference in order to regulate the output voltage. 

When VCOMP ≥ 4 V, VREFX = VREF. When VCOMP < 0.9 V, VREFX = 0 V. 

**==> picture [409 x 98] intentionally omitted <==**

**----- Start of picture text -----**<br>
RZCDU ZCD V Gm<br>ZCD & signal ZCDsamp<br>COMP<br>sampling<br>.<br>RZCDL OTA R 1<br>VREF(CV) C  2<br>Aux.<br>C  1<br>**----- End of picture text -----**<br>


**Figure 54. Constant Voltage Feedback Circuit** 

## **Secondary Side Regulation Compatible** 

The NCL30486 is able to support secondary−side regulation as well. The controller features an option to provide a pullup resistor Rpullup on COMP pin instead of the CV OTA output. This allows connecting directly an optocoupler collector and properly biases it. The internal voltage biasing Rpullup is around 5 V. 

In secondary side regulation, the slow and fast OVP on ZCD pin are still active thus providing an additional over voltage protection. In this case, the ZCD pin resistors should be calculated to trigger VOVP2 at the output voltage of interest. 

**==> picture [190 x 126] intentionally omitted <==**

**----- Start of picture text -----**<br>
CV OTA Boost<br>VDD<br>Rpullup<br>COMP<br>−<br>+<br>VREF(CV)<br>**----- End of picture text -----**<br>


**Figure 55. COMP Pin Configuration for Secondary Side Regulation** 

## **STARTUP PHASE (HV STARTUP)** 

It is generally requested that the LED driver starts to emit light in less than 1 s and possibly within 300 ms. It is challenging since the start−up consists of the time to charge the VCC capacitor and that necessary to charge the output capacitor until sufficient current flows into the LED string. This second phase can be particularly long in dimming cases where the secondary current is a portion of the nominal one. 

The NCL30486 features a high voltage startup circuit that allows charging VCC capacitor very fast. 

When the power supply is first connected to the mains outlet, the internal current source is biased and charges up the VCC capacitor. When the voltage on this VCC capacitor reaches the VCC(on) level, the current source turns off. At this time, the controller is only supplied by the VCC capacitor, and the auxiliary supply should take over before VCC collapses below VCC(off). 

The HV startup circuitry is made of two startup current levels, IHV(start1) and IHV(start1). This helps to protect the controller against short−circuit between VCC and GND. At power−up, as long as VCC is below VCC(TH), the source delivers IHV(start1) (around 300 �A typical). Then, when VCC reaches VCC(TH), the source smoothly transitions to IHV(start2) and delivers its nominal value. As a result, in case of short−circuit between VCC and GND occurring at high line (Vin = 305 V rms), the maximum power dissipation will be 431 x 300 � = 130 mW instead of 1.5 W if there was only one startup current level. 

To speed−up the output voltage rise, the following is implemented: 

- The digital OTA output is increased until VREF(PFC) signal reaches VREFX. Again, this is to speed−up the control signal rise to their steady state value. 

- At the beginning of each operating phase of a VCC cycle, the digital OTA output is set to 0. Actually, the digital OTA output is set to 0 in the case of a cold start−up or in the case of a start−up sequence following an operation interruption due to a fault. On the other hand, if the VCC hiccups just because the system fails to start−up in one VCC cycle, the digital OTA output is not reset to ease the second (or more) attempt. 

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**19** 

**NCL30486** 

- If the load is shorted, the circuit will operate in hiccup mode with VCC oscillating between VCC(off) and VCC(on) until the output under voltage protection (UVP) trips. UVP is triggered if the ZCD pin voltage does not exceed VZCD(short) within a 90 ms operation of time. This indicates that the ZCD pin is shorted to ground or that an excessive load prevents the output voltage from rising. 

## **HV Startup Power Dissipation** 

At high line (305 V rms and above) the power dissipated by the HV startup in case of fault or when the controller is disabled with PDIM becomes high. Indeed, in case of fault, the NCL30486 is directly supplied by the HV rail. When the controller is disabled with PDIM, the optocoupler collector current is also supplied by the controller, since the NCL30486 allows directly connecting the optocoupler transistor to PDIM pin. Thus, the HV startup circuit also supplies the optocoupler transistor in case of faults. The current flowing through the HV startup will heat the controller. It is highly recommended adding enough copper around the controller to decrease the R JA of the controller. 

Adding a minimum pad area of 215 mm[2] of 35 m copper (1 oz) drops the R JA to around 120°C/W (no air flow, R JA measured at ADIM pin) 

The PCB layout shown in Figure 56 is a layout example to achieve low R JA. 

The application note _ANDXXXX_ gives more details about strategies to decrease the power dissipation of the HV startup circuit. 

## **Cycle−by−Cycle Current Limit** 

When the current sense voltage exceeds the internal threshold VILIM, the MOSFET is turned off for the rest of the switching cycle. 

## **Winding and Output Diode Short−Circuit Protection** 

In parallel to the cycle−by−cycle sensing of the CS pin, another comparator with a reduced LEB ( _tBCS_ ) and a threshold of _(VCS(stop) = 140% x VILIM)_ monitors the CS pin to detect a winding or an output diode short circuit. The controller shuts down if it detects 4 consecutives pulses during which the CS pin voltage exceeds _VCS(stop)_ . 

The controller goes into auto−recovery mode. 

## **PWM Dimming** 

The NCL30486 has a dedicated pin for PWM dimming. The controller directly measures the duty ratio of a PWM signal applied to PDIM. 

Two counters with a high frequency clock are used for this purpose. A first counter measure the high state duration of the PWM signal (ton_PDIM) and the second counter measures its period (Tsw_PDIM). A divider computes (ton_PDIM / Tsw_PDIM) and the result is directly the output current setpoint (VREFX set point). A filter is added after the digital divider to remove the ripple of the signal. A cascode configuration on PDIM pin allows decreasing the fall time of the signal. 

Thanks to this circuit, the LED current is controlled in an analog way, even if a PWM signal is used for dimming. This allows having a good PF during dimming. 

**Figure 56. PCD Layout Example** 

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**20** 

**NCL30486** 

**==> picture [317 x 265] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>DIM_sec<br>IPDIM<br>IPDIM(THD)<br>IPDIM(THR)<br>V<br>PDIM_int<br>Ton<br>Tsw<br>**----- End of picture text -----**<br>


**Figure 57. PDIM Internal Waveforms** 

Practically, the controller extracts the duty−cycle by measuring the current inside PDIM pin which is directly the opto coupler collector current. 

If PDIM pin is left open, the controller delivers 100% of Iout. If the pin is pulled down for longer than 25 ms, the controller is disabled. 

If the PWM dimming signal is removed during dimming, the controller delivers 100% of Iout. 

The NCL30486 set 100% of output current when the duty−cycle of the signal applied on PDIM is above 93%. 

## **Analog Dimming** 

The pin ADIM pin allows implementing analog dimming of the LED light. 

If the power supply designer applies an analog signal varying from VDIM(EN) to VDIM100 to the DIM pin, the output current will increase or decrease proportionally to the voltage applied. For VDIM = VDIM100, the power supply delivers the maximum output current (VREFX = 1 V). 

If a voltage lower than VADIM(MIN) is applied to ADIM pin, the output current is clamped to the selected dimming clamp value (see Dimming clamp section below) 

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**21** 

**NCL30486** 

If a voltage lower than VADIM(EN) is applied to the DIM pin, the DRV pulses are disabled for controllers without the dimming CV mode option. 

The DIM pin is pulled up internally by a small current source or resistor. Thus, if the pin is left open, the controller is able to start. 

NOTE: 

- Interaction between ADIM and PDIM: if ADIM and PDIM are both used at the same time, the resulting dimming set point if a multiplication of VADIM and the duty−ratio of PDIM signal. 

- During dimming, when the “Enable” signal is OK, the controller starts pulsing after 1 time−out pulse, even if a higher valley number is selected by VREFX. This is to avoid too long startup time while dimming at low output current value. 

**==> picture [337 x 196] intentionally omitted <==**

**----- Start of picture text -----**<br>
VREF<br>100% VREF<br>8% VREF<br>5% V REF<br>1% VREF<br>VADIM(EN) VADIM(MIN) VADIM100 VADIM<br>**----- End of picture text -----**<br>


**Figure 58. ADIM Pin Dimming Curves** 

## **Dimming Clamp** 

For smart dimming applications, need to bias the secondary−side MCU. This can be achieved by clamping VREFX when the dimming setpoint is small. 

There are 4 options for the dimming clamp: 

- No dimming clamp 

- 1% 

- 5% 

- 8% 

**==> picture [335 x 193] intentionally omitted <==**

**----- Start of picture text -----**<br>
VREFX (%)<br>100%<br>8%<br>5%<br>1%<br>0.01 0.05 0.08 1.0<br>Scaled dimming voltage or<br>dimming duty−ratio<br>**----- End of picture text -----**<br>


**Figure 59. Dimming Clamp Options** 

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**22** 

**NCL30486** 

## **Dimming Curves** 

By default, there is a linear relationship between the voltage applied on ADIM pin and VREFX setpoint. In the same way, there is a linear relationship between the duty−ratio of the signal applied on PDIM and VREFX setpoint. 

An internal memory allows selecting a root square relationship between dimming and VREFX. 

The square like curve is based on CIE 1931 lightness formula. 

**==> picture [344 x 241] intentionally omitted <==**

**----- Start of picture text -----**<br>
Output Current vs. Dimming<br>100<br>90<br>80<br>70<br>60<br>50<br>linear<br>CIE 1931<br>40<br>30<br>20<br>10<br>0<br>0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1<br>Scaled Dimming Voltage or Dimming Duty Ratio<br>Output Current (%)<br>**----- End of picture text -----**<br>


**Figure 60. Dimming Curves** 

## **Valley Lockout** 

Quasi−Square wave resonant systems have a wide switching frequency excursion. The switching frequency increases when the output load decreases or when the input voltage increases. The switching frequency of such systems must be limited. 

The NCL30486 changes valley as VREFX decreases and as the input voltage increases and as the output current setpoint 

is varied during dimming. This limits the frequency excursion. 

By default, when the output current is not dimmed, the controller operates in the first valley at low line and in the second valley at high line. 

There is an option to have the valley thresholds incremented by 1 at high line for better Iout control at 305 V rms. 

**Table 1. VALLEY SELECTION** 

|**Table 1. VALLEY SELECTION**|||||
|---|---|---|---|---|
|**VREFX value at which the Controller**<br>**Changes Valley (****_Iout_ Decreasing)**|0|**VHV_DIV Voltage for Valley Change**<br>−−LL−−          2.3 V         −−HL−−      5 V||**VREFX Value at Which the Controller**<br>**Changes Valley(****_Iout_ Increasing)**|
|Ioutdecreases<br>100%<br>80%<br>65%<br>50%<br>35%<br>25%<br>0%||1st|2nd (3rd)|100%<br>80%<br>65%<br>50%<br>35%<br>25%<br>0%<br>Ioutdecreases|
|||2nd|3rd (4th)||
|||3rd|4th (5th)||
|||4th|5th (6th)||
|||5th|6th (7th)||
|||FF mode|FF mode||
||0         −−LL−−          2.3 V         −−HL−−      5 V<br>**Internal VHV_DIV Voltage for Valley Change**||||



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**23** 

**NCL30486** 

## **Zero Crossing Detection Block** 

The ZCD pin allows detecting when the drain−source voltage of the power MOSFET reaches a valley. 

A valley is detected when the ZCD pin voltage crosses below the 55 mV internal threshold. 

At startup or in case of extremely damped free oscillations, the ZCD comparator may not be able to detect the valleys. To avoid such a situation, Optimus Prime features a Time−Out circuit that generates pulses if the voltage on ZCD pin stays below the 55 mV threshold for 6.5 �s. 

The Time−out also acts as a substitute clock for the valley detection and simulates a missing valley in case of too damped free oscillations. 

At startup, the output voltage reflected on the auxiliary winding is low. Because of the ZCD resistor bridge setting the constant voltage regulation target, the voltage on the ZCD pin is very low and the ZCD comparator might be unable to detect the valleys. In this condition, setting the DRV latch with the 6.5 �s time−out leads to a continuous conduction mode operation (CCM) at the beginning of the soft−start. This CCM operation only last a few cycles until the voltage on ZCD pin becomes high enough and trips the ZCD comparator. 

**==> picture [465 x 269] intentionally omitted <==**

**----- Start of picture text -----**<br>
VZCD<br>VZCD( th) low<br>34<br>high<br>14<br>Iout  decreases or Vincreasesin high<br>12<br>high ZCD comp<br>low 15<br>low<br>TimeOut<br>16<br>2 [nd]  , 3 [rd]<br>high VVIN<br>increases<br>Clock<br>low 17<br>**----- End of picture text -----**<br>


**Figure 61. Valley Detection and Time−out Chronograms** 

If the ZCD pin or the auxiliary winding happen to be shorted the time−out function would normally make the controller keep switching and hence lead to improper regulation of the LED current. 

The Under Voltage Protection (UVP) is implemented to avoid these scenarios: a secondary timer starts counting when the ZCD voltage is below the VZCD(short) threshold. If this timer reaches 90 ms **,** the controller detects a fault and enters the auto−recovery fault mode. 

## **ZCD Over Voltage Protection** 

Because of the power factor correction, it is necessary to set the crossover frequency of the CV loop very low (target 10 Hz, depending on power stage phase shift). Because the loop is slow, the output voltage can reach high value during startup or during an output load step. It is necessary to limit the output voltage excursion. For this, the NCL30486 features a slow OVP and a fast OVP on ZCD pin. 

## _Slow OVP_ 

If ZCD voltage exceeds VOVP1 for 4 consecutive switching cycles, the controller stops switching during 1.4 ms. The PFC loop is not reset. After 1.4 ms, the controller initiates a new DRV pulse to refresh ZCD sampling voltage. If VZCD is still too high (VZCD > 110% VREF(CV)), the controller continues to switch with a 1.4 ms period. The controller resumes its normal operation when VZCD < 110% VREF(CV). 

During slow OVP, the peak current setpoint is COMP pin voltage scaled down by a fixed ratio. 

## _Fast OVP_ 

If ZCD voltage exceeds VZCD(OVP2) (130% of VREF(CV)) for 4 consecutive switching cycles (slow OVP not triggered) or for 2 switching cycles if the slow OVP has already been triggered, the controller detects a fault and starts the auto−recovery fault mode (cf: Fault Management Section) 

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**NCL30486** 

## **Line Feedforward** 

**==> picture [425 x 204] intentionally omitted <==**

**----- Start of picture text -----**<br>
HV v DD<br>v VS<br>I CS(offset) CS R LFF<br>K LFF R sense<br>Q_drv<br>+ 25 ms BO_NOK<br>Blanking<br>−<br>1 V / 0.9 V<br>**----- End of picture text -----**<br>


**Figure 62. Line Feed−Forward and Brown−out Schematic** 

The line voltage is sensed by the HV pin and converted into a current. By adding an external resistor in series between the sense resistor and the CS pin, a voltage offset proportional to the line voltage is added to the CS signal. The offset is applied only during the MOSFET on−time in order to not influence the detection of the leakage inductance reset. 

The offset is always applied even at light load in order to improve the current regulation at low output load. 

## **Brown−out** 

In order to protect the supply against a very low input voltage, the controller features a brown−out circuit with a fixed ON/OFF threshold. The controller is allowed to start if a voltage higher than VHVBO(on) is applied to the HV pin and shuts−down if the HV pin voltage decreases and stays 

below VHVBO(off) for 25 ms typical. Exiting a brown−out condition overrides the hiccup on VCC (VCC does not wait to reach VCC(off)) and the IC immediately goes into startup mode. 

An option with higher brown−out levels is also available (see ordering table and electricals parameters) 

## **Line OVP** 

In order to protect the power supply in case of too high input voltage, the NCL30486 features a line over voltage protection. When the voltage on HV pin exceeds VHV(OVP) the controller stops switching; VCC hiccups. 

When VHV becomes lower than VHV(OVP)RST for more than 25 ms, the controller initiates a clean startup sequence and re−starts switching. 

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**==> picture [494 x 429] intentionally omitted <==**

**----- Start of picture text -----**<br>
NCL30486<br>V HV<br>V HV(OVP)<br>V HV(OVP)RST<br>V CC t LOVP(blank)<br>V CC(on)<br>V CC(off)<br>V DRV ÎÎÎÎÎÎ ÎÎÎÎÎÎ<br>ÎÎÎÎÎÎ ÎÎÎÎÎÎ<br>ÎÎÎÎÎÎ ÎÎÎÎÎÎ<br>Iout<br>Figure 63. Line OVP Chronograms<br>Protections<br>The circuit incorporates a large variety of protections to • Winding or Output Diode Short Circuit protection<br>make the LED driver very rugged. The circuit detects this failure when 4 consecutive DRV<br>Among them, we can list: pulses occur within which the CS pin voltage exceeds<br>• Fault of the GND connection (VCS(stop) = 140% x VILIM). In this case, the controller<br>If the GND pin is properly connected, the supply current enters auto−recovery mode (4−s operation interruption<br>drawn from the positive terminal of the  VCCCC  capacitor, between active bursts).<br>**----- End of picture text -----**<br>


- If the GND pin is properly connected, the supply current drawn from the positive terminal of the _VCCCC_ capacitor, flows out of the GND pin to return to the negative terminal of the _VCC_ capacitor. If the GND pin is not connected, the circuit ESD diodes offer another return path. The accidental non connection of the GND pin can hence be detected by detecting that one of this ESD diode is conducting. Practically, the ESD diode of CS pin is monitored. If such a fault is detected for 200 �s, the circuit stops generating DRV pin. 

      - VCC Over Voltage Protection 

         - The circuit stops generating pulses if the VCC exceeds VCC(OVP) and enters auto−recovery mode. This feature protects the circuit if output LEDs happen to be disconnected. 

      - ZCD fast OVP 

         - If ZCD voltage exceeds VZCD(OVP2) for 4 consecutive switching cycles (slow OVP not triggered) or for 2 switching cycles if the slow OVP has already been triggered, the controller detects a fault and enters auto−recovery mode (4 s operation interruption between active bursts). 

- Output short circuit situation (Output Under Voltage Protection) 

   - Overload is detected by monitoring the ZCD pin voltage: if it remains below VZCD(short) for 90 ms, an output short circuit is detected and the circuit stops generating pulses for 4 s. When this 4 s delay has elapsed, the circuit attempts to restart. 

- Die Over Temperature (TSD) 

The circuit stops operating if the junction temperature ° (TJ) exceeds 150 C typically. The controller remains off until TJ goes below nearly 130°C. 

- ZCD pin incorrect connection: 

   - ♦ If the ZCD pin grounded, the circuit will detect an output short circuit situation when 90 ms delay has elapsed. 

- Brown−Out Protection (BO) 

The circuit prevents operation when the line voltage is too low to avoid an excessive stress of the LED driver. Operation resumes as soon as the line voltage is high enough and VCC is higher than VCC(on). 

- ♦ A 200 k� resistor pulls down the ZCD pin so that the output short circuit detection trips if the ZCD pin is not connected (floating). 

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**26** 

**NCL30486** 

- CS pin short to ground 

The CS pin is checked at start−up (cold start−up or after a brown−out event). A current source (Ics(short)) is applied to the pin and no DRV pulse is generated until the CS pin exceeds Vcs(low). Ics(short) and Vcs(low) are 500 �A and 60 mV typically (VCS rising). The typical minimum impedance to be placed on the CS pin for operation is then 120 �. In practice, it is recommended to place more than 

250 � to take into account possible parametric deviations. Also, along the circuit operation, the CS pin could happen to be grounded. If it is grounded, the MOSFET conduction time is limited by the 20 �s maximum on−time. If such an event occurs, a new pin impedance test is made. 

- Line overvoltage protection 

(see Line OVP section) 

## **ORDERING TABLE OPTION** 

|**OPN #**<br>**NCL30486_ _**|**Maximum Dead−time**|**Maximum Dead−time**|**Maximum Dead−time**|**VREF**|**VREF**|**Max. On−time**|**Max. On−time**|**ZCD Blanking**|**ZCD Blanking**|**Valley**<br>**Transition**<br>**from LL to HL**|**Valley**<br>**Transition**<br>**from LL to HL**|**Standby Mode**|**Standby Mode**|**Line Range**<br>**Detector**|**Line Range**<br>**Detector**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||250�s|687�s|1.4 ms|200 mV|333 mV|20�s|33�s|1�s|1.5�s|1stto<br>2nd|1stto<br>3rd|On|Off|On|Off|
|NCL30486A1||x|||x|x||x||x|||x|x||
|NCL30486A2||x|||x|x||x||x|||x|x||



|**OPN #**<br>**NCL30486_ _**|**Line OVP**|**Line OVP**|**Frozen Peak Current**<br>**During Standby Mode**<br>**VCS(SBY)**|**Frozen Peak Current**<br>**During Standby Mode**<br>**VCS(SBY)**|**Frozen Peak Current**<br>**During Standby Mode**<br>**VCS(SBY)**|**Brown−out Levels**|**Brown−out Levels**||**Dimming Clamp**|**Dimming Clamp**||**Dimming**<br>**Curve**|**Dimming**<br>**Curve**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||On|Off|380 mV|330 mV|280 mV|On: 108 V<br>Off: 98 V|On: 138 V<br>Off: 129 V|0%|1%|5%|8%|Linear|Square|
|NCL30486A1|x||||NA||x||x|||x||
|NCL30486A2|x||||NA|x|||x|||x||



## **ORDERING INFORMATION** 

|**Device**|**Marking**|**Package type**|**Shipping**†|
|---|---|---|---|
|NCL30486A1|L30486A1|SOIC9 – P7 COMP VHV PBFH<br>(Pb−Free)|2500 / Tape & Reel|
|NCL30486A2|L30486A2|||



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**27** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [482 x 451] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOIC−9 NB<br>CASE 751BP<br>9<br>| 1 ISSUE A DATE 21 NOV 2011<br>SCALE 1:1<br>2X<br>0.10 C A-B NOTES:1. DIMENSIONING AND TOLERANCING PER<br>ASME Y14.5M, 1994.<br>D 2. CONTROLLING DIMENSION: MILLIMETERS.<br>D 3. DIMENSION b DOES NOT INCLUDE DAMBAR<br>A PROTRUSION. ALLOWABLE PROTRUSION<br>0.20 C 2X SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’<br>4 TIPS 0.10 C A-B F 4. AT MAXIMUM MATERIAL CONDITION.DIMENSIONS D AND E DO NOT INCLUDE<br>10 Ti 6 jo ] [I MOLD FLASH, PROTRUSIONS, OR GATE<br>BURRS. MOLD FLASH, PROTRUSIONS, OR<br>oh —_ GATE BURRS SHALL NOT EXCEED 0.15mm<br>H E PER SIDE. DIMENSIONS D AND E ARE DE-<br>TERMINED AT DATUM F.<br>pit 1 5. DIMENSIONS A AND B ARE TO BE DETERM-<br>5<br>L2 INED AT DATUM F.<br>A3<br>ioe L C SEATINGPLANE 6. A1 IS DEFINED AS THE VERTICAL DISTANCEFROM THE SEATING PLANE TO THE LOWEST<br>0.20 C 9X b DETAIL A POINT ON THE PACKAGE BODY.<br>B<br>5 TIPS 0.25 M C A-B D MILLIMETERS<br>He TOP VIEW g or DIMA MIN 1.25 MAX 1.75<br>A1 0.10 0.25<br>9X h A3 0.17 0.25<br>0.10 C 0.10 C X 45 Db 4.800.31 5.000.51<br>M E 3.80 4.00<br>e 1.00 BSC<br>f el 1 m( el H 5.80 6.20<br>A h 0.37 REF<br>L 0.40 1.27<br>A1 SIDE VIEWe C SEATINGPLANE DETAIL A END VIEW L2M 00.25 BSC8<br>GENERIC<br>RECOMMENDED<br>MARKING DIAGRAM*<br>SOLDERING FOOTPRINT*<br>9<br>1.00<br>9X 0.58 PITCH XXXXX<br>ALYWX<br>+" 46<br>1<br> m 7 [|<br>6.50 XXXXX = Specific Device Code<br>A = Assembly Location<br>L = Wafer Lot<br>Y = Year<br>W = Work Week<br>9X 1.18 “n0no0_4 1 | = Pb−Free Package<br>DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>


**==> picture [81 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
DATE 21 NOV 2011<br>**----- End of picture text -----**<br>


*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. 

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

**DOCUMENT NUMBER: 98AON52301E DESCRIPTION: SOIC−9 NB** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

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