NCL30188BDR2G

## NCL30188 

## Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller for LED Lighting with Thermal Foldback 

The NCL30188 is a controller targeting isolated and non−isolated “smart−dimmable” constant−current LED drivers. Designed to support flyback, buck−boost, and SEPIC topologies, its proprietary current−control algorithm provides near−unity power factor and tightly regulates a constant LED current from the primary side, thus eliminating the need for a secondary−side feedback circuitry or an optocoupler. 

Housed in the SOIC8, the NCL30188 is specifically intended for very compact space−efficient designs. The device is highly integrated with a minimum number of external components. A robust suite of safety protections is built in to simplify the design. To ensure reliable operations at elevated temperatures, a user configurable current foldback circuit is also provided. 

Pin−to−pin compatible to the NCL30088, the NCL30188 provides the same benefits with in addition, an increased resolution of the digital current−control algorithm for a 75% reduction in the LED current quantization ripple. 

## **Features** 

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8<br>1<br>SOIC−8 NB<br>CASE 751<br>MARKING DIAGRAM<br>8<br>L30188x<br>ALYW<br>1<br>L30188x = Specific Device Code<br>x = A, B<br>A = Assembly Location<br>L = Wafer Lot<br>Y = Year<br>W = Work Week<br>= Pb-Free Package<br>**----- End of picture text -----**<br>


- Quasi−resonant Peak Current−mode Control Operation 

- Constant Current Control with Primary Side Feedback 

- Tight LED Constant Current Regulation of ±2% Typical 

- Power Factor Correction 

- Line Feedforward for Enhanced Regulation Accuracy 

- Low Start−up Current (13 A typ.) 

- Wide Vcc Range 

- 300 mA / 500 mA Totem Pole Driver with 12 V Gate Clamp 

## **PIN CONNECTIONS** 

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1<br>ZCD VCC<br>VS DRV<br>COMP GND<br>SD CS<br>(Top View)<br>**----- End of picture text -----**<br>


- Robust Protection Features 

   - ♦ OVP on VCC 

   - ♦ Programmable Over Voltage / LED Open Circuit Protection 

   - ♦ Cycle−by−cycle Peak Current Limit 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information in the package dimensions section on page 25 of this data sheet. 

   - ♦ Winding Short Circuit Protection 

   - ♦ Secondary Diode Short Protection 

   - ♦ Output Short Circuit Protection 

   - ♦ Shorted Current Sense Protection 

   - ♦ User Programmable NTC Based Thermal Foldback 

   - ♦ Thermal Shutdown 

   - ♦ Vcc Undervoltage Lockout 

   - ♦ Brown−out Protection 

- Pb−Free, Halide−Free Product 

- Latching−off (NCL30188A) or 4−s Auto−recovery (NCL30188B) Protection Modes (See Table 4) 

## **Typical Applications** 

- Integral LED Bulbs and Tubes 

- LED Light Engines 

- LED Drivers/Power Supplies 

- Electronic Control Gear for LED Lighting 

Publication Order Number: **NCL30188/D** 

**1** 

© Semiconductor Components Industries, LLC, 2016 **March, 2016 − Rev. 0** 

**NCL30188** 

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.<br>Aux<br>. .<br>NCL30188<br>1 8<br>2 7<br>3 6<br>4 5<br>RSENSE<br>**----- End of picture text -----**<br>


**Figure 1. Typical Application Schematic in a Flyback Converter** 

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Aux<br>. .<br>NCL30188<br>1 8<br>2 7<br>3 6<br>4 5<br>RSENSE<br>**----- End of picture text -----**<br>


**Figure 2. Typical Application Schematic in a Buck−Boost Converter** 

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**2** 

**NCL30188** 

## **Table 1. PIN FUNCTION DESCRIPTION** 

|**Pin No.**|**Pin Name**|**Function**|**Pin Description**|
|---|---|---|---|
|1|ZCD|Zero Crossing Detection|Connected to the auxiliary winding, this pin detects the core reset event.|
|2|VS|Input Voltage Sensing|This pin observes the input voltage rail and protects the LED driver in case of<br>too low mains conditions (brown−out).<br>This pin also observes the input voltage rail for:<br>− Power Factor Correction<br>− Valley lockout|
|3|COMP|Filtering Capacitor|This pin receives a filtering capacitor for power factor correction. Typical values<br>ranges from 1 − 4.70�F|
|4|SD|Thermal Foldback and<br>Shutdown|Connecting an NTC to this pin allows the user to program thermal current fold-<br>back threshold and slope. A Zener diode can also be used to pull−up the pin<br>and stop the controller for adjustable OVP protection.|
|5|CS|Current Sense|This pin monitors the primary peak current.|
|6|GND|−|Controller ground pin.|
|7|DRV|Driver Output|The driver’s output to an external MOSFET|
|8|VCC|IC Supply Pin|This pin is the positive supply of the IC. The circuit starts to operate when_VCC_<br>exceeds 18 V and turns off when_VCC_goes below 8.8 V (typical values). After<br>start−up, the operating range is 9.4 V up to 25.5 V (_VCC_(_OVP_)minimum level).|



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**3** 

**NCL30188** 

## **Internal Circuit Architecture** 

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Enable STOP VDD VREF<br>Over Voltage Protection<br>(Auto−recovery or Latched) Aux_SCP OFF<br>VCC<br>Fault UVLO<br>VCC Management<br>Management<br>Over Temp. Protection Latch<br>(Auto−recovery or Latched)<br>Internal<br>SD Thermal ThermalShutdown VCC_max VCC Over VoltageProtection<br>Foldback VTF WOD_SCP<br>BO_NOK<br>DRV FF_mode VVS VREF<br>VCC<br>FF_mode<br>ZCD Zero Crossing Detection Logic (ZCD Blanking, Time−Out, ...) Valley Selection ClampCircuit<br>Frequency Foldback<br>Aux. Winding Short Circuit Prot. Aux_SCP S DRV<br>VVS VTF CS_ok Q<br>Q<br>Line R<br>feed−forward STOP VVS VREF<br>VTF<br>CS Leading Power Factor and CS_reset<br>Edge Constant−Current Maximum<br>Blanking Control on time<br>Ipkmax STOP<br>t<br>Max. Peak Ipkmax on,max COMP<br>Current<br>Limit<br>CS Short CS_ok VVS<br>Protection BO_NOK VS<br>Brown−Out<br>UVLO t<br>on,max<br>Winding and<br>Output diode WOD_SCP GND<br>Short Circuit<br>Protection<br>**----- End of picture text -----**<br>


**Figure 3. Internal Circuit Architecture** 

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**4** 

**NCL30188** 

## **Table 2. MAXIMUM RATINGS TABLE** 

|**Symbol**|**Rating**|**Value**|**Unit**|
|---|---|---|---|
|VCC(MAX)<br>ICC(MAX)|Maximum Power Supply voltage, VCCpin, continuous voltage<br>Maximum current for VCCpin|−0.3 to 30<br>Internally limited|V<br>mA|
|VDRV(MAX)<br>IDRV(MAX)|Maximum driver pin voltage, DRV pin, continuous voltage<br>Maximum current for DRV pin|−0.3, VDRV(Note 1)<br>−300, +500|V<br>mA|
|VMAX<br>IMAX|Maximum voltage on low power pins (except DRV and VCCpins)<br>Current range for low power pins (except DRV and VCCpins)|−0.3, 5.5 (Notes 2 and 5)<br>−2, +5|V<br>mA|
|RθJ−A|Thermal Resistance Junction−to−Air|180|°C/W|
|TJ(MAX)|Maximum Junction Temperature|150|°C|
||Operating Temperature Range|−40 to +125|°C|
||Storage Temperature Range|−60 to +150|°C|
||ESD Capability, HBM model (Note 3)|3.5|kV|
||ESD Capability, MM model (Note 3)|250|V|
||ESD Capability, CDM model (Note 3)|2|kV|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise. 

2. These levels are low enough not to exceed the maximum ratings of the internal ESD 5.5−V Zener diode. More positive and negative voltages can be applied if the pin current stays within the −2−mA / 5−mA range. 

3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E, Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E. 

4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds ± 100 mA 

5. **Recommended maximum VS voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the VS pin recommended range.** 

**Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40 ° C to +125 ° C, VCC = 12 V) 

|VCS= 0 V, VSD= 1.5 V) For min/max values TJ= −40°|C to +125°C, VCC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Description**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**STARTUP AND SUPPLY CIRCUITS**|||||||
|Supply Voltage<br>Startup Threshold<br>Minimum Operating Voltage<br>Hysteresis VCC(on)– VCC(off)<br>Internal logic reset|VCCrising<br>VCCrising<br>VCCfalling|VCC(on)<br>VCC(off)<br>VCC(HYS)<br>VCC(reset)|16.0<br>8.2<br>8<br>4|18.0<br>8.8<br>−<br>5|20.0<br>9.4<br>−<br>6|V|
|VCCOver Voltage Protection Threshold||VCC(OVP)|25.5|26.8|28.5|V|
|VCC(off)noise filter<br>VCC(reset)noise filter||tVCC(off)<br>tVCC(reset)|−<br>−|5<br>20|−<br>−|�s|
|Startup current||ICC(start)|−|13|30|�A|
|Startup current in fault mode||ICC(~~s~~<br>~~F~~ault)||58|75|�A|
|Supply Current<br>Device Disabled/Fault<br>Device Enabled/No output load on pin 7<br>Device Switching (FSW= 65 kHz)|VCC> VCC(off)<br>Fsw= 65 kHz<br>CDRV= 470 pF, Fsw= 65 kHz|ICC1<br>ICC2<br>ICC3|0.8<br>–<br>−|1.0<br>2.6<br>3.0|1.2<br>4.0<br>4.5|mA|
|**CURRENT SENSE**|||||||
|Maximum Internal current limit||VILIM|0.95|1.00|1.05|V|
|Leading Edge Blanking Duration for VILIM||tLEB|240|300|360|ns|



6. Guaranteed by Design 

7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 

8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 � s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. 

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**5** 

## **NCL30188** 

**Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40 ° C to +125 ° C, VCC = 12 V) 

|VCS= 0 V, VSD= 1.5 V) For min/max values TJ= −40°|C to +125°C, VCC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Description**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**CURRENT SENSE**|||||||
|Propagation delay from current detection to gate<br>off−state||tILIM|−|100|150|ns|
|Maximum on−time||ton(MAX)|26|36|46|�s|
|Threshold for immediate fault protection activation||VCS(stop)|1.35|1.50|1.65|V|
|Leading Edge Blanking Duration for VCS(stop)||tBCS|−|150|−|ns|
|Current source for CS to GND short detection||ICS(short)|400|500|600|�A|
|Current sense threshold for CS to GND short de-<br>tection|VCSrising|VCS(low)|30|65|100|mV|
|**GATE DRIVE**|||||||
|Drive Resistance<br>DRV Sink<br>DRV Source||RSNK<br>RSRC|−<br>−|13<br>30|−<br>−|�|
|Drive current capability<br>DRV Sink (Note 6)<br>DRV Source (Note 6)||ISNK<br>ISRC|−<br>−|500<br>300|−<br>−|mA|
|Rise Time (10% to 90%)|CDRV= 470 pF|tr|–|40|−|ns|
|Fall Time (90% to 10%)|CDRV= 470 pF|tf|–|30|−|ns|
|DRV Low Voltage|VCC= VCC(off)+0.2 V<br>CDRV= 470 pF, RDRV=33 k�|VDRV(low)|8|–|−|V|
|DRV High Voltage|VCC= VCC(MAX)<br>CDRV= 470 pF, RDRV=33 k�|VDRV(high)|10|12|14|V|
|**ZERO VOLTAGE DETECTION CIRCUIT**|||||||
|Upper ZCD threshold voltage|VZCDrising|VZCD(rising)|−|90|150|mV|
|Lower ZCD threshold voltage|VZCDfalling|VZCD(falling)|35|55|−|mV|
|ZCD hysteresis||VZCD(HYS)|15|−|−|mV|
|Propagation Delay from valley detection to DRV high|VZCDfalling|TDEM|−|100|300|ns|
|Blanking delay after on−time||TZCD(blank1)|1.12|1.50|1.88|�s|
|Timeout after last DEMAG transition||TTIMO|5.0|6.5|8.0|�s|
|Pulling−down resistor|VZCD= VZCD(falling)|RZCD(PD)|−|200|−|k�|
|**CONSTANT CURRENT AND POWER FACTOR CONTROL**|||||||
|Reference Voltage at TJ= 25°C||VREF|245|250|255|mV|
|Reference Voltage TJ= 25°C to 100°C||VREF|242.5|250.0|257.5|mV|
|Reference Voltage TJ= −40°C to 125°C||VREF|240|250|260|mV|
|Current sense lower threshold|VCSfalling|VCS(low)|20|55|100|mV|
|Vcontrolto current setpoint division ratio||Vratio|−|4|−|−|
|Error amplifier gain|VREFX=VREF|GEA|40|50|60|�S|
|Error amplifier current capability|VREFX=VREF|IEA||±60||�A|
|COMP Pin Start−up Current Source|COMP pin grounded|IEA_STUP||140||�A|



6. Guaranteed by Design 

7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 

8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 � s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. 

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**6** 

## **NCL30188** 

**Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40 ° C to +125 ° C, VCC = 12 V) 

|VCS= 0 V, VSD= 1.5 V) For min/max values TJ= −40°|C to +125°C, VCC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Description**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**LINE FEED FORWARD**|||||||
|VVSto ICS(offset)conversion ratio||KLFF|18|20|22|�S|
|Line feed−forward current on CS pin|DRV high, VVS= 2 V|IFF|35|40|45|�A|
|Offset current maximum value|VVS> 5 V|Ioffset(MAX)|80|100|120|�A|
|**VALLEY LOCKOUT SECTION**|||||||
|Threshold for high− line range (HL) detection|VVSrising|VHL|2.28|2.40|2.52|V|
|Threshold for low−line range (LL) detection|VVSfalling|VLL|2.18|2.30|2.42|V|
|Blanking time for line range detection||tHL(blank)|15|25|35|ms|
|**FAULT PROTECTION**|||||||
|Thermal Shutdown (Note 6)|FSW= 65 kHz|TSHDN|130|150|170|�C|
|Thermal Shutdown Hysteresis||TSHDN(HYS)|−|50|–|�C|
|Threshold voltage for output short circuit or<br>auxiliary winding short circuit detection||VZCD(short)|0.8|1.0|1.2|V|
|Short circuit detection Timer|VZCD< VZCD(short)|tOVLD|70|90|110|ms|
|Auto−recovery timer duration||trecovery|3|4|5|s|
|SD pin Clamp series resistor||RSD(clamp)||1.6||k�|
|Clamped voltage|SD pin open|VSD(clamp)|1.13|1.35|1.57|V|
|SD pin detection level for OVP|VSDrising|VOVP|2.35|2.50|2.65|V|
|Delay before OVP or OTP confirmation (OVP and<br>OTP)||TSD(delay)|22.5|30.0|37.5|�s|
|Reference current for direct connection of an NTC<br>(Note 8)||IOTP(REF)|80|85|90|�A|
|Fault detection level for OTP (Note 7)|VSDfalling|VOTP(off)|0.47|0.50|0.53|V|
|SD pin level for operation recovery after an OTP<br>detection|VSDrising|VOTP(on)|0.66|0.70|0.74|V|
|OTP blanking time when circuit starts operating<br>(Note 8)||tOTP(start)|250||370|�s|
|SD pin voltage at which thermal fold−back starts<br>(VREFis decreased)||VTF(start)|0.94|1.00|1.06|V|
|SD pin voltage at which thermal fold−back stops<br>(VREFis clamped to VREF50)||VTF(stop)|0.64|0.69|0.74|V|
|VTF(start)over IOTP(REF)ratio (Note 7)|TJ= +25°C to +125°C|RTF(start)|10.8|11.7|12.6|k�|
|VTF(stop)over IOTP(REF)ratio (Note 7)|TJ= +25°C to +125°C|RTF(stop)|7.4|8.1|8.8|k�|
|VOTP(off)over IOTP(REF)ratio (Note 7)|TJ= +25°C to +125°C|ROTP(off)|5.4|5.9|6.4|k�|
|VOTP(on)over IOTP(REF)ratio (Note 7)|TJ= +25°C to +125°C|ROTP(on)|7.5|8.1|8.7|k�|
|VREF@ VSD= 600 mV (SD pin falling no OTP<br>detection) (percent of VREF)||VREF(50)|40|50|60|%|
|**BROWN−OUT**|||||||
|Brown−Out ON level (IC start pulsing)|VSrising|VBO(on)|0.95|1.00|1.05|V|
|Brown−Out OFF level (IC shuts down)|VSfalling|VBO(off)|0.85|0.90|0.95|V|



6. Guaranteed by Design 

7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 

8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 � s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. 

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**7** 

**NCL30188** 

**Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40 ° C to +125 ° C, VCC = 12 V) 

|VCS= 0 V, VSD= 1.5 V) For min/max values TJ= −40°|C to +125°C, VCC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Description**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**BROWN−OUT**|||||||
|BO comparators delay||tBO(delay)||30||�s|
|Brown−Out blanking time||tBO(blank)|15|25|35|ms|
|VSpin Pulling−down Current|VS= VBO(on)|IBO(bias)|50|250|450|nA|



6. Guaranteed by Design 

7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 

8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 � s to avoid detecting an OTP fault by allowing the 

- SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. 

## **TYPICAL CHARACTERISTICS** 

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20.0 9.4<br>9.3<br>19.5<br>9.2<br>19.0 9.1<br>9.0<br>18.5<br>8.9<br>18.0 8.8<br>8.7<br>17.5<br>8.6<br>17.0 8.5<br>8.4<br>16.5<br>8.3<br>16.0 8.2<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 4. VCC Start−up Threshold vs. Figure 5. VCC Minimum Operating Voltage vs.<br>Temperature Temperature<br>11.5 6.0<br>5.8<br>11.0<br>5.6<br>10.5<br>5.4<br>10.0<br>5.2<br>9.5 5.0<br>4.8<br>9.0<br>4.6<br>8.5<br>4.4<br>8.0<br>4.2<br>7.5 4.0<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)  (V)<br>CC(on) CC(off)<br>V V<br> (V)  (V)<br>CC(hys) CC(reset)<br>V V<br>**----- End of picture text -----**<br>


**Figure 6. Hysteresis (VCC(on) − VCC(off)) vs. Temperature** 

**Figure 7. VCC(reset) vs. Temperature** 

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**NCL30188** 

## **TYPICAL CHARACTERISTICS** 

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28.0<br>27.8<br>27.6<br>27.4<br>27.2<br>27.0<br>26.8<br>26.6<br>26.4<br>26.2<br>26.0<br>25.8<br>25.6<br>−50 −25 0 25 50 75 100 125 150<br> (V)<br>CC(ovp)<br>V<br>**----- End of picture text -----**<br>


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TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 8. VCC Over Voltage Protection Threshold vs. Temperature** 

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150<br>125<br>100<br>75<br>50<br>25<br>0<br>−50 −25 0 25 50 75 100 125 150<br>A)<br>�<br> (<br>ICC(sfault)<br>**----- End of picture text -----**<br>


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TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 10. Start−up Current in Fault Mode vs. Temperature** 

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40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>A)<br>�<br> (<br>ICC(start)<br>**----- End of picture text -----**<br>


**Figure 9. Start−up Current vs. Temperature** 

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2.0<br>1.8<br>1.6<br>1.4<br>1.2<br>1.0<br>0.8<br>0.6<br>0.4<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (mA)<br>ICC1<br>**----- End of picture text -----**<br>


**Figure 11. ICC1 vs. Temperature** 

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3.8 5.0<br>3.6<br>4.5<br>3.4<br>3.2 4.0<br>3.0<br>2.8 3.5<br>2.6<br>3.0<br>2.4<br>2.2 2.5<br>2.0<br>2.0<br>1.8<br>1.6<br>1.5<br>1.4<br>1.2 1.0<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br> (mA)  (mA)<br>ICC2 ICC3<br>**----- End of picture text -----**<br>


**Figure 12. ICC2 vs. Temperature** 

**Figure 13. ICC3 vs. Temperature** 

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**NCL30188** 

## **TYPICAL CHARACTERISTICS** 

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1.05 400<br>1.04 380<br>1.03 360<br>1.02 340<br>1.01 320<br>1.00 300<br>0.99 280<br>0.98 260<br>0.97 240<br>0.96 220<br>0.95 200<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br> (V)  (ns)<br>ILIM LEB<br>V T<br>**----- End of picture text -----**<br>


TJ, JUNCTION TEMPERATURE ( ° C) 

**Figure 14. Maximum Internal Current Limit vs. Temperature** 

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**----- Start of picture text -----**<br>
150<br>140<br>130<br>120<br>110<br>100<br>90<br>80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>−50 −25 0 25 50 75 100 125 150<br> (ns)<br>ILIM<br>T<br>**----- End of picture text -----**<br>


TJ, JUNCTION TEMPERATURE ( ° C) 

**Figure 16. Current Limit Propagation Delay vs. Temperature** 

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**----- Start of picture text -----**<br>
1.60<br>1.58<br>1.56<br>1.54<br>1.52<br>1.50<br>1.48<br>1.46<br>1.44<br>1.42<br>1.40<br>1.38<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>CS(stop)<br>V<br>**----- End of picture text -----**<br>


**Figure 18. VCS(stop) vs. Temperature** 

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TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 15. Leading Edge Blanking vs. Temperature** 

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**----- Start of picture text -----**<br>
50<br>48<br>46<br>44<br>42<br>40<br>38<br>36<br>34<br>32<br>30<br>−50 −25 0 25 50 75 100 125 150<br>s)<br>�<br> (<br>ON(max)<br>T<br>**----- End of picture text -----**<br>


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TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 17. Maximum On−time vs. Temperature** 

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220<br>210<br>200<br>190<br>180<br>170<br>160<br>150<br>140<br>130<br>120<br>110<br>100<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (ns)<br>BCS<br>T<br>**----- End of picture text -----**<br>


**Figure 19. Leading Edge Blanking Duration for VCS(stop) vs. Temperature** 

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**10** 

**NCL30188** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
600 100<br>580<br>90<br>560<br>80<br>540<br>70<br>520<br>500 60<br>480<br>50<br>460<br>40<br>440<br>30<br>420<br>400 20<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>A)<br>�<br> (  (mV)<br>ICS(short) VCS(low)<br>**----- End of picture text -----**<br>


**Figure 20. ICS(short) vs. Temperature** 

**Figure 21. VCS(low), VCS Rising vs. Temperature** 

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**----- Start of picture text -----**<br>
20 40<br>38<br>18<br>36<br>16 34<br>32<br>14<br>30<br>12 28<br>26<br>10<br>24<br>8 22<br>20<br>6<br>18<br>4 16<br>14<br>2<br>12<br>0 10<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>) � ) �<br> (  (<br>SNK SRC<br>R R<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 22. Sink Gate Drive Resistance vs. Temperature** 

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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 23. Source Gate Drive Resistance vs. Temperature** 

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**----- Start of picture text -----**<br>
50 50<br>45 45<br>40 40<br>35 35<br>30 30<br>25 25<br>20 20<br>15 15<br>10 10<br>5 5<br>0 0<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br> (ns)tr  (ns)tF<br>**----- End of picture text -----**<br>


**Figure 24. Gate Drive Rise Time vs. Temperature** 

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**----- Start of picture text -----**<br>
Figure 25. Gate Drive Fall Time<br>(CDRV = 470 pF) vs. Temperature<br>**----- End of picture text -----**<br>


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**11** 

**NCL30188** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
9.8<br>9.6<br>9.4<br>9.2<br>9.0<br>8.8<br>8.6<br>8.4<br>8.2<br>−50 −25 0 25 50 75 100 125 150<br> (V)<br>DRV(low)<br>V<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 26. DRV Low Voltage vs. Temperature** 

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**----- Start of picture text -----**<br>
15.0<br>14.5<br>14.0<br>13.5<br>13.0<br>12.5<br>12.0<br>11.5<br>11.0<br>10.5<br>10.0<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>DRV(high)<br>V<br>**----- End of picture text -----**<br>


**Figure 27. DRV High Voltage vs. Temperature** 

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**----- Start of picture text -----**<br>
150<br>140<br>130<br>120<br>110<br>100<br>90<br>80<br>70<br>60<br>50<br>40<br>30<br>−50 −25 0 25 50 75 100 125 150<br> (mV)<br>ZCD(rising)<br>V<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 28. Upper ZCD Threshold Voltage vs. Temperature** 

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**----- Start of picture text -----**<br>
80<br>75<br>70<br>65<br>60<br>55<br>50<br>45<br>40<br>35<br>30<br>−50 −25 0 25 50 75 100 125 150<br> (mV)<br>ZCD(falling)<br>V<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 29. Lower ZCD Threshold vs. Temperature** 

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**----- Start of picture text -----**<br>
50 2.0<br>45 1.9<br>40 1.8<br>35 1.7<br>30 1.6<br>25 1.5<br>20 1.4<br>15 1.3<br>10 1.2<br>5 1.1<br>0 1.0<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>s)<br>�<br> (<br> (mV)<br>VZCD(HYS) tZCD(blank1)<br>**----- End of picture text -----**<br>


**Figure 30. ZCD Hysteresis vs. Temperature** 

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**----- Start of picture text -----**<br>
Figure 31. ZCD Blanking Delay vs.<br>Temperature<br>**----- End of picture text -----**<br>


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**12** 

**NCL30188** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
7.8 256<br>7.6 255<br>254<br>7.4<br>253<br>7.2<br>252<br>7.0<br>251<br>6.8 250<br>6.6 249<br>248<br>6.4<br>247<br>6.2<br>246<br>6.0 245<br>5.8 244<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>s)<br>�<br> (<br> (mV)<br>TIMO REF<br>T V<br>**----- End of picture text -----**<br>


**Figure 32. ZCD Time−out vs. Temperature** 

**Figure 33. Reference Voltage vs. Temperature** 

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**----- Start of picture text -----**<br>
110<br>100<br>90<br>80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>−50 −25 0 25 50 75 100 125 150<br> (mV)<br>CS(low)<br>V<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 34. Current Sense Lower Threshold (VCS Falling) vs. Temperature** 

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**----- Start of picture text -----**<br>
60<br>58<br>56<br>54<br>52<br>50<br>48<br>46<br>44<br>42<br>−50 −25 0 25 50 75 100 125 150<br>S)<br>�<br> (<br>EA<br>G<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 35. Error Amplifier Trans−conductance Gain vs. Temperature** 

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**----- Start of picture text -----**<br>
22.0 44<br>21.5 43<br>21.0 42<br>20.5 41<br>20.0 40<br>19.5 39<br>19.0 38<br>18.5 37<br>18.0 36<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>S)<br>� A)<br> ( �<br> (<br>KLFF IFF<br>**----- End of picture text -----**<br>


**Figure 36. Feedforward VVS to ICS(offset) Conversion Ratio vs. Temperature** 

**Figure 37. Line Feedforward Current on CS Pin (@ VVS = 2 V) vs. Temperature** 

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**13** 

**NCL30188** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
120<br>115<br>110<br>105<br>100<br>95<br>90<br>85<br>80<br>−50 −25 0 25 50 75 100 125 150<br>A)<br>�<br> (<br>Ioffset(MAX)<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 38. Ioffset(MAX) vs. Temperature** 

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**----- Start of picture text -----**<br>
2.60<br>2.55<br>2.50<br>2.45<br>2.40<br>2.35<br>2.30<br>2.25<br>2.20<br>−50 −25 0 25 50 75 100 125 150<br> (V)<br>LL<br>V<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 40. Threshold for Low−line Range Detection vs. Temperature** 

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**----- Start of picture text -----**<br>
1.20<br>1.15<br>1.10<br>1.05<br>1.00<br>0.95<br>0.90<br>0.85<br>0.80<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>ZCD(short)<br>V<br>**----- End of picture text -----**<br>


**Figure 42. Threshold Voltage for Output Short Circuit Detection vs. Temperature** 

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**----- Start of picture text -----**<br>
2.55<br>2.50<br>2.45<br>2.40<br>2.35<br>2.30<br>2.25<br>−50 −25 0 25 50 75 100 125 150<br> (V)<br>HL<br>V<br>**----- End of picture text -----**<br>


TJ, JUNCTION TEMPERATURE ( ° C) 

**Figure 39. Threshold for High−line Range Detection vs. Temperature** 

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**----- Start of picture text -----**<br>
40<br>38<br>36<br>34<br>32<br>30<br>28<br>26<br>24<br>22<br>20<br>−50 −25 0 25 50 75 100 125 150<br> (ms)<br>HL(blank)<br>T<br>**----- End of picture text -----**<br>


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TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 41. Blanking Time for Low−line Range Detection vs. Temperature** 

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115<br>110<br>105<br>100<br>95<br>90<br>85<br>80<br>75<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (ms)<br>tOVLD<br>**----- End of picture text -----**<br>


**Figure 43. Short Circuit Detection Timer vs. Temperature** 

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**14** 

**NCL30188** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
5.00 2.20<br>2.10<br>4.75<br>2.00<br>4.50 1.90<br>1.80<br>4.25<br>1.70<br>4.00 1.60<br>1.50<br>3.75<br>1.40<br>3.50 1.30<br>1.20<br>3.25<br>1.10<br>3.00 1.00<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 44. Auto−recovery Timer Duration vs. Figure 45. SD Pin Clamp Series Resistor vs.<br>Temperature Temperature<br>1.60 2.58<br>1.55 2.56<br>1.50 2.54<br>1.45<br>2.52<br>1.40<br>2.50<br>1.35<br>2.48<br>1.30<br>2.46<br>1.25<br>2.44<br>1.20<br>1.15 2.42<br>1.10 2.40<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 46. SD Pin Clamp Voltage vs. Figure 47. SD Pin OVP Threshold Voltage vs.<br>Temperature Temperature<br>38 91<br>90<br>36<br>89<br>34 88<br>87<br>32<br>86<br>30 85<br>84<br>28<br>83<br>26 82<br>81<br>24<br>80<br>22 79<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>) �<br> (s)  (k<br>recovery<br>T SD(clamp)<br>R<br> (V)<br> (V)<br>OVP<br>V<br>SD(clamp)<br>V<br>s) A)<br>� �<br> (  (<br>TSD(delay) IOTP(REF)<br>**----- End of picture text -----**<br>


**Figure 48. TSD(delay) vs. Temperature** 

**Figure 49. IOTP(REF) vs. Temperature** 

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**15** 

**NCL30188** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
12.5<br>12.4<br>12.3<br>12.2<br>12.1<br>12.0<br>11.9<br>11.8<br>11.7<br>11.6<br>11.5<br>11.4<br>11.3<br>11.2<br>11.1<br>11.0<br>−50 −25 0 25 50 75 100 125 150<br>) �<br> (k<br>TF(start)<br>R<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 50. RTF(start) vs. Temperature** 

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8.8<br>8.7<br>8.6<br>8.5<br>8.4<br>8.3<br>8.2<br>8.1<br>8.0<br>7.9<br>7.8<br>7.7<br>7.6<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>) �<br> (k<br>TF(stop)<br>R<br>**----- End of picture text -----**<br>


**Figure 51. RTF(stop) vs. Temperature** 

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**----- Start of picture text -----**<br>
6.4<br>6.3<br>6.2<br>6.1<br>6.0<br>5.9<br>5.8<br>5.7<br>5.6<br>5.5<br>5.4<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>) �<br> (k<br>OTP(off)<br>R<br>**----- End of picture text -----**<br>


**Figure 52. ROTP(off) vs. Temperature** 

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8.8<br>8.7<br>8.6<br>8.5<br>8.4<br>8.3<br>8.2<br>8.1<br>8.0<br>7.9<br>7.8<br>7.7<br>7.6<br>−50 −25 0 25 50 75 100 125 150<br>) �<br> (k<br>OTP(on)<br>R<br>**----- End of picture text -----**<br>


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TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 53. ROTP(on) vs. Temperature** 

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55 1.05<br>54 1.04<br>53 1.03<br>52 1.02<br>51 1.01<br>50 1.00<br>49 0.99<br>48 0.98<br>47 0.97<br>46 0.96<br>45 0.95<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br> (%)  (V)<br>VREF(50) VBO(on)<br>**----- End of picture text -----**<br>


**Figure 54. Ratio VREF(50) over VREF vs. Temperature** 

**Figure 55. Brown−out ON Level vs. Temperature** 

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**16** 

**NCL30188** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
0.95 35<br>34<br>0.94<br>33<br>0.93 32<br>31<br>0.92<br>30<br>0.91 29<br>28<br>0.90<br>27<br>0.89 26<br>25<br>0.88<br>24<br>0.87 23<br>22<br>0.86<br>21<br>0.85 20<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br> (V)  (ms)<br>BO(off)<br>V<br>tBO(blank)<br>**----- End of picture text -----**<br>


TJ, JUNCTION TEMPERATURE ( ° C) 

**Figure 56. Brown−out OFF Level vs. Temperature** 

TJ, JUNCTION TEMPERATURE ( ° C) 

**Figure 57. Brown−out Blanking Time vs. Temperature** 

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500<br>450<br>400<br>350<br>300<br>250<br>200<br>150<br>100<br>50<br>0<br>−50 −25 0 25 50 75 100 125 150<br> (nA)<br>IBO(bias)<br>**----- End of picture text -----**<br>


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TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 58. VS Pin Pulling−down Current vs. Temperature** 

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**17** 

**NCL30188** 

## **Application Information** 

The NCL30188 is a driver for power−factor corrected flyback and non−isolated buck−boost and SEPIC converters. Its current−mode, quasi−resonant architecture optimizes the efficiency by turning on the MOSFET when its drain−source voltage is minimal (valley). At high line, the circuit delays the MOSFET turn on until the second valley is detected to reduce the switching losses. A proprietary circuitry ensures both accurate regulation of the output current (without the need for a secondary−side feedback) and near−unity power factor correction. The circuit contains a suite of powerful protections to ensure a robust LED driver design without the need for extra components or overdesign. 

- **Quasi−Resonance Current−Mode Operation:** implementing quasi−resonance operation in peak current−mode control, the NCL30188 optimizes the efficiency by turning on the MOSFET when its drain−source voltage is minimal (valley). In light−load conditions, the circuit changes valleys to reduce the switching losses. For stable operation, the valley at which the MOSFET switches on remains locked until the input voltage or the output current set−point significantly changes. 

- **Primary−Side Constant−Current Control with Power Factor Correction:** a proprietary circuitry allows the LED driver to achieve both near−unity power factor correction and accurate regulation of the output current without requiring any secondary−side feedback (no optocoupler needed). A power factor as high as 0.99 and an output current deviation below ±2% are typically obtained. 

- **Main protection features:** 

   - ♦ **Over Temperature Thermal Fold−back / Shutdown/ Over Voltage Protection:** the NCL30188 features a gradual current foldback to protect the driver from excessive temperature down to 50% of the programmed current. This represents a power reduction of the LED by more than 50%. If the temperature continues to rise after this point to a second level, the controller stops operating. This mode would only be expected to be reached if there is a severe fault. The first and second temperature thresholds depend on the value of the NTC 

connected to the SD pin. Note, the SD pin can also be used to shutdown the device by pulling this pin below the V min level . A Zener diode can OTP(off) also be used to pull−up the pin and stop the controller for adjustable OVP protection. Both protections are latching−off (A version) or auto−recovery (the circuit can recover operation after 4−s delay has elapsed − B version). 

- ♦ **Cycle−by−cycle peak current limit:** when the current sense voltage exceeds the internal threshold VILIM, the MOSFET is immediately turned off (cycle−by−cycle current limitation). 

- ♦ **Winding or Output Diode Short−Circuit Protection:** an additional comparator senses the CS signal and stops the controller if it exceeds 150% x VILIM for 4 consecutive cycles. This feature can protect the converter if a winding is shorted or if the output diode is shorted or simply if the transformer saturates. This protection is latching−off (A version) or auto−recovery (B version). 

- ♦ **Output Short−circuit protection:** if the ZCD pin voltage remains low for a 90−ms time interval, the controller detects that the output or the ZCD pin is grounded and hence, stops operation. This protection is latching−off (A version) or auto−recovery (B version). 

- ♦ **Open LED protection:** if the VCC pin voltage exceeds the OVP threshold, the controller shuts down and waits 4 seconds before restarting switching operation. 

- ♦ **Floating or Short Pin Detection:** the circuit can detect most of these situations which helps pass safety tests. 

## **Power Factor and Constant Current Control** 

The NCL30188 embeds an analog/digital block to control the power factor and regulate the output current by monitoring the ZCD, VS and CS pin voltages (signals ZCD, VS and VCS of Figure 59). This circuitry generates the current setpoint (VCONTROL/4) and compares it to the current sense signal (VCS) to dictate the MOSFET turning off event when VCS exceeds VCONTROL/4. 

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**----- Start of picture text -----**<br>
ZCD STOP VVS VREFX<br>VCS Power Factor and PWM Latch reset<br>Constant−Current<br>Control<br>COMP<br>C1<br>Figure 59. Power Factor and Constant−Current Control<br>**----- End of picture text -----**<br>


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**18** 

**NCL30188** 

As illustrated in Figure 59, the VS pin provides the sinusoidal reference necessary for shaping the input current. The obtained current reference is further modulated so that when averaged over a half−line period, it is equal to the output current reference (VREFX). This averaging process is made by an internal Operational Trans−conductance Amplifier (OTA) and the capacitor connected to the COMP pin (C1 of Figure 59). Typical COMP capacitance is 1 �F and should not be less than 470 nF to ensure stability. The COMP ripple does not affect the power factor performance as the circuit digitally eliminates it when generating the current setpoint. 

If the VS pin properly conveys the sinusoidal shape, power factor will be close to unity and the Total Harmonic Distortion (THD) will be low. In any case, the output current will be well regulated following the equation below: 

**==> picture [213 x 24] intentionally omitted <==**

Where: 

- NPS is the secondary to primary transformer turns NPS = NS/NP. NPS is 1 in the case of non−isolated buck−boost or SEPIC converter. 

- Rsense is the current sense resistor (see Figure 1). 

- VREFX is the output current internal reference. VREFX = VREF (250 mV, typically) at full load. 

The output current reference (VREFX) is VREF unless the temperature is high enough to activate the thermal fold−back (see “protections” section). 

If a major fault is detected, the circuit enters the latched−off or auto−recovery mode and the COMP pin is grounded (except in an UVLO condition). This ensures a clean start−up when the circuit resumes operation. 

## **Start−up Sequence** 

Generally an LED lamp is expected to emit light in < 1 sec and typically within 300 ms. The start−up phase consists of the time to charge the VCC capacitor, begin switching and the time to charge the output capacitor until sufficient current flows into the LED string. To speed−up this phase, the following defines the start−up sequence: 

- The COMP pin is grounded when the circuit is off. The average COMP voltage needs to exceed the VS pin peak value to have the LED current properly regulated (whatever the current target is). To speed−up the COMP capacitance charge and shorten the start−up phase, an internal 80−�A current source adds to the OTA sourced current (60 �A max typically) to charge up the COMP capacitance. The 80−�A current source remains on until the OTA starts to sink current as a result of the COMP pin voltage sufficient rise. At that moment, the COMP pin being near its steady−state value, it is only driven by the OTA. 

- If VCC drops below the VCC(off) threshold because the circuit fails to start−up properly on the first attempt, a new try takes place as soon as VCC is recharged to VCC(on). The COMP voltage is not reset at that moment. Instead, the new attempt starts with the COMP level obtained at the end of the previous operating phase. 

- If the load is shorted, the circuit will operate in hiccup mode with VCC oscillating between VCC(off) and VCC(on) until the AUX_SCP protection trips (AUX_SCP is triggered if the ZCD pin voltage does not exceed 1 V within a 90−ms operation period of time thus indicating a short to ground of the ZCD pin or an excessive load preventing the output voltage from rising). The NCL30188A latches off in this case. With the B version, the AUX_SCP protection forces the 4−s auto−recovery delay to reduce the operation duty−ratio. Figure 60 illustrates a start−up sequence with the output shorted to ground, in this second case. 

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**19** 

**NCL30188** 

**==> picture [519 x 225] intentionally omitted <==**

**----- Start of picture text -----**<br>
V<br>eeeeee ede beeen CC(on) ened eb<br>VCC<br>iJ iN ii V iiV/ iN ii i<br>CC(off)<br>ii ii il iii ii ii ii<br>iit at bhi bt 1<br>ii ii i iii ii ii ii<br>ii ii i iii i il il<br>ii ii i ) iii ii ii ) ii<br>ii ii i iii ii ii il<br>ii ii i iii ii ii ii<br>ii i i iii i ii ii time<br>AUX_SCPtrips<br>tl 1 | II tll 1 | I i!<br>as t 1 + t 2 + t 3 = tOVLD<br>DRV ( tOVLD ~ 90 ms )<br>[t] 1 ii ii [t] 3 ii [t] 1 iii ii [t] 3 ii il time .<br>rs [t] 2 i i ans Pris [t] 2 i i ors it<br>ii SK i ii i —S€K il ii<br>i trecovery ( s ) i trecovery ( s )<br>**----- End of picture text -----**<br>


**Figure 60. Start−up Sequence in a Load Short−circuit Situation (auto−recovery version)** 

## **Zero Crossing Detection Block** 

The ZCD pin detects when the drain−source voltage of the NCL30188 features a time−out circuit that generates pulses power MOSFET reaches a valley by crossing below the if the voltage on ZCD pin stays below the 55−mV threshold 55−mV internal threshold. At startup or in case of extremely for 6.5 s. The time−out also acts as a substitute clock for the damped free oscillations, the ZCD comparator may not be valley detection and simulates a missing valley in case the able to detect the valleys. To avoid such a situation, the free oscillations are too damped. 

**Figure 61. Zero Current Detection Block** 

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**20** 

**NCL30188** 

If the ZCD pin or the auxiliary winding happen to be shorted, the time−out function would normally make the controller keep switching and hence lead to improper LED current value. The “AUX_SCP” protection prevents such a stressful operation: a secondary timer starts counting that is only reset when the ZCD voltage exceeds the VZCD(short) threshold (1 V typically). If this timer reaches 90 ms (no ZCD voltage pulse having exceeded VZCD(short) for this time period), the controller detects a fault and stops operation for 4 seconds (B version) or latches off (A version). 

The “clock” shown in Figure 61 is used by the “valley selection frequency foldback” circuitry of the block diagram (Figure 3), to generate the next DRV pulse (if no fault prevents it): 

- Immediately when the clock occurs in QR mode at low line or valley 2 at high line (full load) 

- After the appropriate number of “clock” pulses in thermal foldback mode 

**For an optimal operation, the maximum ZCD level should be maintained below 5 V to stay safely below the built in clamping voltage of the pin.** 

## **Line Range Detection** 

As sketched in Figure 62, this circuit detects the low−line range if the VS pin remains below the VLL threshold (2.3 V typical) for more than the 25−ms blanking time. High−line is detected as soon as the VS pin voltage exceeds VHL (2.4 V typical). These levels roughly correspond to 184−V rms and 192−V rms line voltages if the external resistors divider applied to the VS pin is designed to provide a 1−V peak value at 80 V rms. 

**Figure 62. Line Range Detection** 

In the low-line range, conduction losses are generally dominant. Adding a dead-time would further increase these losses. Hence, only a short dead-time is necessary to reach the MOSFET valley. In high-line conditions, switching losses generally are the most critical. It is thus efficient to skip one valley to lower the switching frequency. Hence, under normal operation, the NCL30188 optimizes the 

efficiency over the line range by turning on the MOSFET at the first valley in low-line conditions and at the second valley in the high-line case. This is illustrated by Figure 63 that sketches the MOSFET Drain-source voltage in both cases. In the event that thermal foldback is activated, additional valleys can be skipped as the power is reduced. 

**Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line (right)** 

## **Line Feedforward** 

As illustrated by Figure 64, the input voltage is sensed by the VS pin and converted into a current. By adding an 

external resistor in series between the sense resistor and the CS pin, a voltage offset proportional to the input voltage is added to the CS signal for the MOSFET on−time. 

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**21** 

**NCL30188** 

**==> picture [300 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bulk rail<br>vDD<br>VS<br>I CS(offset) CS RCS<br>Rsense<br>Q_drv<br>**----- End of picture text -----**<br>


**Figure 64. Line Feed−Forward Schematic** 

In Figure 64, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise. 

## **Protections** 

The circuit incorporates a large variety of protections to make the LED driver very rugged. Among them, we can list: 

## **Output Short Circuit Situation** 

An overload fault is detected if the ZCD pin voltage remains below VZCD(short) for 90 ms. In such a situation, the circuit stops generating pulses until the 4−s delay auto−recovery time has elapsed (B version) or latches off (A version). 

## **Winding or Output Diode Short Circuit Protection** 

If a transformer winding happens to be shorted, the primary inductance will collapse leading the current to ramp up in a very abrupt manner. The VILIM comparator (current limitation threshold) will trip to open the MOSFET and eventually stop the current rise. However, because of the 

abnormally steep slope of the current, internal propagation delays and the MOSFET turn−off time will make possible the current rise up to 50% or more of the nominal maximum value set by VILIM. As illustrated in Figure 65, the circuit uses this current overshoot to detect a winding short circuit. The leading edge blanking (LEB) time for short circuit protection (LEB2) is significantly faster than the LEB time for cycle−by−cycle protection (LEB1). Practically, if four consecutive switching periods lead the CS pin voltage to exceed (VCS(stop)=150% *VILIM), the NCL30188B enters the auto−recovery mode (4−s interruption of operation between the active bursts) while the NCL30188A latches off the LED driver until it is reset. Similarly, this function can also protect the power supply if the output diode is shorted or if the transformer simply saturates. 

**==> picture [476 x 231] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>Q DRV Vdd UVLO aux<br>Q<br>TSD<br>CS R BONOK Vcc VCC<br>LEB1 + PWMreset UVLO management<br>Vcontrol / 4 −<br>latch<br>4−s timer VCCreset<br>+ Ipkmax STOP (grandreset)<br>−<br>VILIMIT AUX_SCP<br>SD Pin OVP<br>LEB2 + WOD_SCP 4−pulse (OVP2) VCC(ovp)<br>counter<br>−<br>OTP<br>VCS(stop) S OFF S latch<br>Q Q<br>Q Q<br>AUTO−RECOVERY LATCHING−OFF<br>R (NCL30188B) R (NCL30188A)<br>4−s timer VCCreset<br>**----- End of picture text -----**<br>


**Figure 65. Winding Short Circuit Protection, Max. Peak Current Limit Circuits** 

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**22** 

**NCL30188** 

## **VCC Over Voltage Protection** 

The circuit stops generating pulses if VCC exceeds VCC(OVP) and enters auto−recovery mode. This feature protects the circuit if the output LED string happens to open or is disconnected. 

## **Programmable Over Voltage Protection (OVP2)** 

Connect a Zener diode between VCC and the SD pin to set a programmable VCC OVP (DZ of Figure 66). The triggering level is (VZ+VOVP) where VOVP is the 2.5−V internal threshold. If this protection trips, the NCL30188A latches off while the NCL30188B enters the auto−recovery mode (see Figure 66). 

**==> picture [402 x 304] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vdd<br>NCL30188B<br>IOTP(REF) SD Pin OVP (OVP2) DETECTION (auto−recovery version)<br>S<br>+ Q OFF<br>VCC − Q<br>VOVP<br>DZ TSD(delay) R<br>SD<br>4−s Timer<br>OTP DETECTION<br>NTC<br>NCP30188A<br>TOTP(start) (latching−off version)<br>VOTP(off) / VOTP(on)<br>S<br>Q Latch<br>Q<br>Thermal VTF R<br>Foldback<br>grand reset<br>Rclamp<br>Vclamp<br>Clamp<br>−<br>+<br>**----- End of picture text -----**<br>


**Figure 66. Thermal Foldback and OVP/OTP Circuitry** 

The SD pin is clamped to about 1.35 V ( _Vclamp_ ) through a 1.6−k� resistor ( _Rclamp_ ). It is then necessary to inject about 

circuit gradually reduces the LED current down 50% of its nominal value when VSD reaches VTF(stop), in accordance with the characteristic of Figure 67. 

**==> picture [124 x 79] intentionally omitted <==**

If this thermal foldback cannot prevent the temperature from rising (testified by VSD drop below VOTP), the circuit latches off (NCL30188A) or enters auto−recovery mode (NCL30188B) and cannot resume operation until VSD exceeds VOTP(on) to provide some temperature hysteresis (around 10°C typically). The OTP thresholds nearly correspond to the following resistances of the NTC: 

typically, to trigger the OVP protection. This current helps ensure an accurate detection by using the Zener diode far from its knee region. 

- Thermal foldback starts when RNTC ≤ RTF(start) 

   - (11.7 k�, typically) 

- Thermal foldback stops when RNTC ≤ RTF(stop) (8.0 k�, typically) 

## **Programmable Over Temperature Foldback Protection (OTP)** 

- OTP triggers when RNTC ≤ ROTP(off) (5.9 k�, typically) 

Connect an NTC between the SD pin and ground to detect an over−temperature condition. In response to a high temperature (detected if VSD drops below VTF(start)), the 

      - OTP is removed when RNTC ≥ ROTP(on) (8.0 k�, typically) (Note 9) 

9. This condition is sufficient for operation recovery of the B version. For the A version which latches off when OTP triggers, the circuit further needs to be reset by a VCC drop below VCC(reset). 

   - An online EXCEL[®] −based design tool is available to aid in selecting the appropriate NTC value. 

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**23** 

**NCL30188** 

At startup, when VCC reaches VCC(on), the OTP comparator is blanked for at least 250 s in order to allow the m SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. This avoids flickering of the LED light during turn on. 

## **Brown−Out Protection** 

**Figure 67. Output Current Reduction versus SD Pin Voltage** 

The NCL30188 prevents operation when the line voltage is too low for proper operation. As illustrated in Figure 68, the circuit detects a brown−out situation if the VS pin remains below the VBO(off) threshold (0.9 V typical) for more than the 25−ms blanking time. In this case, the controller stops operating. Operation resumes as soon as the VS pin voltage exceeds VBO(on) (1.0 V typical) and VCC is higher than VCC(on). To ease recovery, the circuit overrides the VCC normal sequence (no need for VCC cycling down below VCC(off)). Instead, its consumption immediately reduces to ICC(start) so that VCC rapidly charges up to VCC(on). Once done, the circuit re−starts operating. 

**Figure 68. Brown−out Circuit** 

## **Die Over Temperature (TSD)** 

The circuit stops operating if the junction temperature (TJ) exceeds 150°C typically. The controller remains off until TJ goes below nearly 100°C. 

## **Pin Connection Faults** 

The circuit addresses most pin connection fault cases: 

## • **CS pin short to ground** 

The circuit senses the CS pin impedance every time it starts−up and after DRV pulses terminated by the 36−s M maximum on−time. If the measured impedance does not exceed 120 ohm typically, the circuit stops operating. In practice, it is recommended to place a minimum of 250−ohm in series between the CS pin and the current sense resistor to take into account possible parametric deviations. 

- **Fault of the GND connection** 

If the GND pin is properly connected, the supply current drawn from the positive terminal of the _VCC_ capacitor, flows out of the GND pin to return to the negative terminal of the _VCC_ capacitor. If the GND pin is not connected, the circuit ESD diodes offer another return path. The accidental non−connection of the GND pin is monitored by detecting that one of the ESD diode is conducting. Practically, the ESD diode of CS pin is monitored. If such a fault is detected for 200 s, the m circuit stops generating DRV pulses. 

**More generally, incorrect pin connection situations (open, grounded, shorted to adjacent pin) are covered by AND9204/D.** 

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**24** 

## **NCL30188** 

## **Fault Modes** 

The circuit turns off whenever a major faulty condition prevents it from operating: 

- Severe OTP (VSD level below VOTP(off)) 

- VCC OVP 

- OVP2 (additional OVP provided by SD pin) 

- Output diode short circuit protection: “WOD_SCP high” 

- Output / Auxiliary winding Short circuit protection: “Aux_SCP high” 

- Die over temperature (TSD) 

In this mode, the DRV pulses generation is interrupted. 

In the case of a latching−off fault, the circuit stops pulsing until the LED driver is unplugged and VCC drops below VCC(reset). At that moment, the fault is cleared and the circuit could resume operation. 

In the auto−recovery case, the circuit cannot generate DRV pulses for the auto−recovery 4−s delay. When this time has elapsed, the circuit recovers operation as soon as the VCC voltage has exceeded VCC(on). 

In the B version, all these protections are auto−recovery. The SD pin OTP and OVP, WOD_SCP and AUX_SCP are latching off in the A version (see Table 4). 

## **Table 4. PROTECTION MODES** 

|**Table 4. PROTECTION**|**MODES**||||
|---|---|---|---|---|
||**AUX_SCP**|**WOD_SCP**|**SD Pin OTP**|**SD Pin OVP**|
|NCL30188A*|Latching off|Latching off|Latching off|Latching off|
|NCL30188B|Auto−recovery|Auto−recovery|Auto−recovery|Auto−recovery|



## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package Type**|**Shipping**|
|NCL30188ADR2G*|SOIC−8<br>(Pb−Free/Halide Free)|2500 / Tape & Reel|
|NCL30188BDR2G|||



*Please contact local sales representative for availability. 

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**25** 

**NCL30188** 

## **PACKAGE DIMENSIONS** 

**==> picture [48 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOIC−8 NB<br>**----- End of picture text -----**<br>


**==> picture [468 x 446] intentionally omitted <==**

**----- Start of picture text -----**<br>
CASE 751−07 NOTES:<br>−X− ISSUE AK 1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>pa 5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>4 MAXIMUM MATERIAL CONDITION.<br>−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW<br>STANDARD IS 751−07.<br>G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>A 4.80 5.00 0.189 0.197<br>C N X 45 B 3.80 4.00 0.150 0.157<br>SEATING C 1.35 1.75 0.053 0.069<br>PLANE D 0.33 0.51 0.013 0.020<br>−Z− G 1.27 BSC 0.050 BSC<br>H 0.10 0.25 0.004 0.010<br>0.10 (0.004) J 0.19 0.25 0.007 0.010<br>H D M J K 0.40 1.27 0.016 0.050<br>M 0  8  0  8<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244<br>SOLDERING FOOTPRINT*<br>1.52<br>0.060<br>p ane<br>7.0 4.0<br>0.275 wal 0.155<br>0.6 1.270<br>0.024 9096 0.050<br>SCALE 6:1 mm<br>inches<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


EXCEL is a registered trademark of Microsoft Corporation. 

ON Semiconductor and the         are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

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## **LITERATURE FULFILLMENT** : 

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**NCL30188/D** 

**26**