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NCL30186ADR2G.
LED Driver, AC / DC, 3A, 1 Output, 9.4V to 26V Input, 200V Output, -40 to 125 °C, SOIC-10
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- Manufacturer: ONSEMI
- Product type: AC / DC LED Driver ICs
- MSL: MSL 1 - Unlimited
- SVHC: No SVHC (15-Jan-2018)
- Topology: Buck-Boost, Flyback, SEPIC
- IC Mounting: Surface Mount
- No. of Pins: 10Pins
- Product Range: -
- Qualification: -
- No. of Outputs: 1Outputs
- Device Topology: Buck-Boost, Flyback, SEPIC
- LED Driver Type: Isolated, Non Isolated
- Driver Case Style: NSOIC
- IC Case / Package: NSOIC
- Input Voltage Max: 26V
- Input Voltage Min: 9.4V
- Output Current Max: 3A
- Output Voltage Max: 200V
- Switching Frequency: 65kHz
- Switching Frequency Typ: 65kHz
- Operating Temperature Max: 125°C
- Operating Temperature Min: -40°C
- Automotive Qualification Standard: -
| Delivery and price | |
|---|---|
| Units per pack | 2500 |
| Price | 0.418 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
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## Analog/Digital Dimmable Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller for LED Lighting NCL30186
The NCL30186 is a controller targeting isolated and non−isolated “smart−dimmable” constant−current LED drivers. Designed to support flyback, buck−boost, and SEPIC topologies, its proprietary current− control algorithm provides near−unity power factor and tightly regulates a constant LED current from the primary side, thus eliminating the need for a secondary−side feedback circuitry or an optocoupler.
Housed in the SOIC10 which has the same body size as a standard SOIC8, the NCL30186 is specifically intended for very compact space−efficient designs. The device is highly integrated with a minimum number of external components. A robust suite of safety protections is built in to simplify the design. To ensure reliable operation at elevated temperatures, a user configurable current foldback circuit is also provided. In addition, it supports analog and PWM dimming with a dedicated dimming input intended to control the average LED current.
Pin−to−pin compatible to the NCL30086, the NCL30186 provides the same benefits with in addition, an increased resolution of the digital current−control algorithm for a 75% reduction in the LED current quantization ripple.
## **Features**
- Quasi−resonant Peak Current−mode Control Operation
- Valley Lockout Optimizes Efficiency over the Line/Load Range
## **SOIC−10 CASE 751BQ**
## **MARKING DIAGRAM**
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L30186x<br>ALYW<br>L30186x = Specific Device Code<br>x = A, B, C, D<br>A = Assembly Location<br>L = Wafer Lot<br>Y = Year<br>W = Work Week<br>= Pb-Free Package<br>**----- End of picture text -----**<br>
## **PIN CONNECTIONS**
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DIM 1 NC<br>ZCD VCC<br>VS DRV<br>COMP GND<br>SD CS<br>(Top View)<br>**----- End of picture text -----**<br>
## **ORDERING INFORMATION**
See detailed ordering and shipping information in the package dimensions section on page 28 of this data sheet. NOTE: Some of the device on this data sheet have been **DISCONTINUED** . Please refer to the table on page 28
- Constant Current Control with Primary Side Feedback
- Tight LED Constant Current Regulation of 2% Typical
- Power Factor Correction
- Analog or PWM dimming
- Line Feedforward for Enhanced Regulation Accuracy
- Low Start−up Current (10 A typ.)
- Wide Vcc Range
- 300 mA / 500 mA Totem Pole Driver with 12 V Gate Clamp
- Robust Protection Features
- Brown−Out Detection
- OVP on VCC
- Programmable Over Voltage / LED Open Circuit Protection
- Cycle−by−cycle Peak Current Limit
- Winding Short Circuit Protection
- Secondary Diode Short Protection
- Output Short Circuit Protection
- Current Sense (CS) Short Detection
- User programmable NTC Based Thermal Foldback
- Thermal Shutdown
- −40 to 125 C Operating Junction Temperature
- Pb−Free, Halide−Free Product
- Four Versions: NCL30186A, B, C and D (See Table 1)
## **Typical Applications**
- Integral LED Bulbs
- LED Light Engines
- LED Driver Power Supplies
- Smart LED Lighting Applications
Publication Order Number: **NCL30186/D**
**1**
Semiconductor Components Industries, LLC, 2016 **January, 2025 − Rev. 4**
**NCL30186**
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.<br>Aux<br>.<br>.<br>sy<br>VDIM NCL30186<br>o><br>Pon 1 10<br>2 9<br>3 8<br>4 7<br>5 6<br>R<br>sense<br>yo<br>[peA |<br>**----- End of picture text -----**<br>
**Figure 1. Typical Application Schematic in a Flyback Converter**
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.<br>Aux<br>.<br>AK Z »<br>VDIM NCL30186<br>: 1 10<br>ao 2 9<br>3 8<br>4 7<br>5 6<br>R<br>sense<br>i?<br>[peA |<br>**----- End of picture text -----**<br>
**Figure 2. Typical Application Schematic in a Buck−Boost Converter**
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**NCL30186**
## **Table 1. FOUR NCL30186 VERSIONS**
|**Part Number**|**Protection Mode**|**Current Regulation**<br>**Reference Voltage**<br>**(VREF)**|**Recommended for (*):**|
|---|---|---|---|
|NCL30186A|Latching−off|250 mV|Isolated converters.<br>Non−isolated converters with<br>Vout<br>(Vin,rms)LL|
|NCL30186B|Auto−recovery|250 mV|Isolated converters.<br>Non−isolated converters with<br>Vout<br>(Vin,rms)LL|
|NCL30186C<br>~~re~~|Latching−off<br>~~re~~|200 mV<br>~~re~~|Non−isolated converters with<br>Vout<br>(Vin,rms)LL<br>~~re~~|
|NCL30186D<br>~~ee~~|Auto−recovery<br>~~ee~~|200 mV<br>~~ee~~|Non−isolated converters with<br>Vout<br>(Vin,rms)LL<br>~~ee~~|
*(Vin,rms)LL designates the lowest line rms voltage. Refer to AND9217/D for more details. (http://www.onsemi.com/pub_link/Collateral/AND9217−D.PDF).
**Table 2. PIN FUNCTION DESCRIPTION**
|**Pin No**<br>~~a~~|**Pin Name**<br>~~a~~|**Function**<br>~~a~~|**Pin Description**<br>~~ee~~|
|---|---|---|---|
|1<br>~~a~~|DIM<br>~~a~~|Analog / PWM Dimming<br>~~a~~|This pin is used for analog or PWM dimming control. An analog signal that can be<br>varied between VDIM0and VDIM100or a PWM signal can be used to adjust the<br>LED current.<br>~~ee~~|
|2<br>~~a~~|ZCD<br>~~a~~|Zero Crossing Detection<br>~~a ~~|Connected to the auxiliary winding, this pin detects the core reset event.<br> ~~ee~~|
|3<br>~~re~~<br>~~a~~|VS<br>~~re~~<br>~~a~~|Input Voltage Sensing<br>~~re~~<br>~~ee~~|This pin monitors the input voltage rail for:<br>Power Factor Correction<br>Valley lockout<br>Brownout Detection<br>~~re~~<br>~~ee~~|
|4<br>~~a~~|COMP<br>~~a~~|Filtering Capacitor<br>~~ee~~|This pin receives a filtering capacitor for power factor correction. Typical values<br>ranges from 1 − 4.7 F.<br>~~ee~~|
|5<br>~~a~~|SD<br>~~a~~|Thermal Foldback and<br>Shutdown<br>~~ee~~|Connecting an NTC to this pin allows the user to program thermal current fold-<br>back threshold and slope. A Zener diode can also be used to pull−up the pin and<br>stop the controller for adjustable OVP protection.<br>~~ee~~|
|6<br>~~a~~|CS<br>~~a~~|Current Sense<br>~~a~~|This pin monitors the primary peak current.|
|7<br>~~a~~|GND<br>~~a~~|−<br>~~a~~|Controller ground pin.|
|8<br><br>~~a~~|DRV<br><br>~~a~~|Driver Output<br>|The driver’s output to an external MOSFET<br>~~ee~~|
|9<br>~~a~~<br>~~a~~|VCC<br>~~a~~<br>~~a~~|IC Supply Pin<br>~~a ~~|This pin is the positive supply of the IC. The circuit starts to operate when_VCC_<br>exceeds 18 V and turns off when_VCC_goes below 8.8 V (typical values). After<br>start−up, the operating range is 9.4 V up to 26 V (_VCC_(_OVP_)minimum level).<br> ~~ee~~|
|10<br><br>~~a~~|NC<br><br>~~a~~|−<br>|−<br> ~~ee~~|
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**NCL30186**
**Internal Circuit Architecture**
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**----- Start of picture text -----**<br>
Enable STOP VDD VREF<br>Over Voltage Protection<br>(Auto−recovery or Latched) Aux_SCP OFF<br>VCC<br>Fault UVLO<br>VCC Management<br>Management<br>Over Temp. Protection Latch<br>(Auto−recovery or Latched)<br>ee<br>Internal<br>SD Thermal ShutdownThermal VCC_max VCC Over VoltageProtection<br>Foldback VTF WOD_SCP<br>dae L r i BO_NOK —_ ]<br>DRV FF_mode<br>VVS<br>VCC<br>Zero Crossing Detection Logic FF_mode<br>Aux_SCP<br>ZCD (ZCD Blanking, Time−Out, ...) Valley Selection Clamp<br>Circuit<br>0 Aux. Winding Short Circuit Prot. ee Frequency Foldback<br>S DRV<br>Q<br>CS_ok<br>VVS Q —|>4<br>Linefeed−forward STOP VVS VREFX DIM_disable R<br>_ “E<br>GND<br>CS Leading Power Factor and CS_reset<br>Edge Constant−Current Maximum<br>Blanking Control on time<br>DIM_disable Ipkmax STOP t<br>on,max COMP<br>Max. Peak Ipkmax<br>Current<br>Limit VVS<br>BO_NOK VS<br>Brown−Out<br>CS_ok<br>CS Short<br>Protection<br>VREF<br>UVLO t<br>a on,max oe DIM_disable<br>VREFX DIM<br>Winding and Dimming<br>Output diode WOD_SCP control<br>Short Circuit<br>Protection<br>C k VTF<br>**----- End of picture text -----**<br>
**Figure 3. Internal Circuit Architecture**
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## **Table 3. MAXIMUM RATINGS TABLE(S)**
|**Symbol**|**Rating**|**Value**|**Unit**|
|---|---|---|---|
|VCC(MAX)<br>ICC(MAX)|Maximum Power Supply voltage, VCCpin, continuous voltage<br>Maximum current for VCCpin|−0.3 to 30<br>Internally limited|V<br>mA|
|VDRV(MAX)<br>IDRV(MAX)|Maximum driver pin voltage, DRV pin, continuous voltage<br>Maximum current for DRV pin|−0.3, VDRV(Note 1)<br>−300, +500|V<br>mA|
|VMAX<br>IMAX|Maximum voltage on low power pins (except DRV and VCCpins)<br>Current range for low power pins (except DRV and VCCpins)|−0.3, 5.5 (Notes 2 and 5)<br>−2, +5|V<br>mA|
|RJ−A|Thermal Resistance Junction−to−Air|180|C/W|
|TJ(MAX)|Maximum Junction Temperature|150|C|
||Operating Temperature Range|−40 to +125|C|
||Storage Temperature Range|−60 to +150|C|
||ESD Capability, HBM model (Note 3)|3.5|kV|
||ESD Capability, MM model (Note 3)|250|V|
||ESD Capability, CDM model (Note 3)|2|kV|
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V Zener diode. More positive and negative voltages can be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E, Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.
4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds 100 mA.
5. **Recommended maximum VS voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the VS pin recommended range.**
**Table 4. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)
|Supply Voltage<br>Startup Threshold<br>Minimum Operating Voltage<br>Hysteresis VCC(on)– VCC(off)<br>Internal logic reset<br>~~tt~~|VCCrising<br>VCCrising<br>VCCfalling<br>~~tt~~|VCC(on)<br>VCC(off)<br>VCC(HYS)<br>VCC(reset)<br>~~tt~~|16.0<br>8.2<br>8<br>4<br>~~tt~~|18.0<br>8.8<br>−<br>5<br>~~tt~~|20.0<br>9.4<br>−<br>6<br>~~tt~~|V<br>~~tt~~|
|---|---|---|---|---|---|---|
|VCCOver Voltage Protection Threshold<br>~~tt~~<br>~~i~~|~~tt~~<br>~~ee~~|VCC(OVP)<br>~~tt~~<br>~~ee~~|25.5<br>~~tt~~<br>~~ee~~|26.8<br>~~tt~~<br>~~ee~~|28.5<br>~~tt~~<br>~~ee~~|V<br>~~tt~~<br>~~ee~~|
|VCC(off)noise filter<br>VCC(reset)noise filter<br>~~ee~~<br>~~i~~|~~ee~~<br>~~ee~~|tVCC(off)<br>tVCC(reset)<br>~~ee~~<br>~~ee~~|−<br>−<br>~~ee~~<br>~~ee~~|5<br>20<br>~~ee~~<br>~~ee~~|−<br>−<br>~~ee~~<br>~~ee~~|s<br>~~ee~~<br>~~ee~~|
|Startup current<br>~~i~~|~~ee~~|ICC(start)<br>~~ee~~|−<br>~~ee~~|13<br>~~ee~~|30<br>~~ee~~|A<br>~~ee~~|
|Startup current in fault mode<br>~~i~~|~~ee ~~|ICC(Fault)<br> ~~ee~~|~~ee~~|58<br>~~ee~~|75<br>~~ee~~|A<br>~~ee~~|
|Supply Current<br>Device Disabled/Fault<br>Device Enabled/No output load on DRV pin<br>Device Switching<br>~~a~~|VCC> VCC(off)<br>Fsw= 65 kHz<br>CDRV= 470 pF, Fsw= 65 kHz<br>~~ee~~|ICC1<br>ICC2<br>ICC3<br>~~ee~~|0.8<br>–<br>−<br>~~ee~~|1.0<br>2.6<br>3.0<br>~~ee~~|1.2<br>4.0<br>4.5<br>~~ee~~|mA<br>~~ee~~|
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. **www.onsemi.com Share Feedback** ~~—————————~~ **5** Your Opinion Matters
## **NCL30186**
**Table 4. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)
|**Description**<br>**Unit**<br>**Max**<br>**Typ**<br>**Min**<br>**Symbol**<br>**Test Condition**<br>**CURRENT SENSE**<br>~~ee~~|
|---|
|Maximum on−time<br>ton(MAX)<br>26<br>36<br>46<br>s<br>~~a~~|
|Threshold for immediate fault protection activation<br>VCS(stop)<br>1.35<br>1.50<br>1.65<br>V<br>~~a~~|
|Leading Edge Blanking Duration for VCS(stop)<br>tBCS<br>−<br>150<br>−<br>ns<br>~~a~~|
|Current source for CS to GND short detection<br>ICS(short)<br>400<br>500<br>600<br>A|
|Current sense threshold for CS to GND short de-<br>tection<br>VCSrising<br>VCS(low)<br>30<br>65<br>100<br>mV<br>~~a~~|
|**GATE DRIVE**|
|Drive Resistance|
|DRV Sink<br>RSNK<br>−<br>13<br>−|
|DRV Source<br>RSRC<br>−<br>30<br>−|
|Drive current capability<br>mA|
|DRV Sink (Note 6)<br>ISNK<br>−<br>500<br>−|
|DRV Source (Note 6)<br>ISRC<br>−<br>300<br>−|
|Rise Time (10% to 90%)<br>CDRV= 470 pF<br>tr<br>–<br>40<br>−<br>ns<br>~~a~~|
|Fall Time (90% to 10%)<br>CDRV= 470 pF<br>tf<br>–<br>30<br>−<br>ns<br>~~a~~|
|DRV Low Voltage<br>VCC= VCC(off)+0.2 V<br>CDRV= 470 pF, RDRV= 33 k<br>VDRV(low)<br>8<br>–<br>−<br>V<br>~~po~~|
|DRV High Voltage<br>VCC= VCC(MAX)<br>CDRV= 470 pF, RDRV= 33 k<br>VDRV(high)<br>10<br>12<br>14<br>V<br>~~po~~|
|**ZERO VOLTAGE DETECTION CIRCUIT**|
|Upper ZCD threshold voltage<br>VZCDrising<br>VZCD(rising)<br>−<br>90<br>150<br>mV<br>~~a~~|
|Lower ZCD threshold voltage<br>VZCDfalling<br>VZCD(falling)<br>35<br>55<br>−<br>mV<br>~~a~~|
|ZCD hysteresis<br>VZCD(HYS)<br>15<br>−<br>−<br>mV|
|Propagation Delay from valley detection to DRV<br>high<br>VZCDfalling<br>TDEM<br>−<br>100<br>300<br>ns<br>Blanking delay after on−time<br>VREFX> 30% VREF<br>TZCD(blank1)<br>1.12<br>1.50<br>1.88<br>s<br>~~ee ee ee~~<br>~~a~~|
|Blanking delay at light load<br>VREFX< 25% VREF<br>TZCD(blank2)<br>0.56<br>0.75<br>0.94<br>s<br>~~a~~|
|Timeout after last DEMAG transition<br>TTIMO<br>5.0<br>6.5<br>8.0<br>s<br>~~a~~|
|Pulling−down resistor<br>VZCD= VZCD(falling)<br>RZCD(PD)<br>−<br>200<br>−<br>k<br>~~a~~|
|**CONSTANT CURRENT AND POWER FACTOR CONTROL**|
|Reference Voltage at TJ= 25C<br>A and B versions<br>VREF<br>245<br>250<br>255<br>mV|
|C and D versions<br>195<br>200<br>205|
|Reference Voltage TJ= 25C to 100C<br>A and B versions<br>VREF<br>242.5<br>250.0<br>257.5<br>mV|
|C and D versions<br>192.5<br>200.0<br>207.5|
|Reference Voltage TJ= −40C to 125C<br>A and B versions<br>VREF<br>240<br>250<br>260<br>mV|
|C and D versions<br>190<br>200<br>210|
|Current sense lower threshold<br>VCSfalling<br>VCS(low)<br>20<br>50<br>100<br>mV<br>~~a~~|
|Vcontrolto current setpoint division ratio<br>Vratio<br>−<br>4<br>−<br>−<br>~~a~~|
|Error amplifier gain<br>VREFX= VREF<br>GEA<br>40<br>50<br>60<br>S<br>~~a~~|
|6. Guaranteed by Design|
|7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off)and ROTP(on)give the resistance the<br>NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after|
|an OTP situation.|
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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## **NCL30186**
|**Table 4. ELECTRICAL CHARACTERISTICS**(Unless otherwise noted: For typical values TJ= 25C, VCC= 12 V, VZCD= 0 V,|
|---|
|VCS= 0 V, VSD= 1.5 V) For min/max values TJ= −40C to +125C, VCC= 12 V)<br>**Description**<br>**Unit**<br>**Max**<br>**Typ**<br>**Min**<br>**Symbol**<br>**Test Condition**<br>**CONSTANT CURRENT AND POWER FACTOR CONTROL**<br>~~a~~<br>~~OO~~|
|Error amplifier current capability<br>VREFX= VREF(no dimming)<br>VREFX= 25%* VREF<br>IEA<br>60<br>240<br>A<br>COMP Pin Start−up Current Source<br>COMP pin grounded<br>IEA_STUP<br>140<br>A<br>~~ee~~<br>~~ee~~<br>~~ee ee ee~~<br>~~a~~|
|**LINE FEED FORWARD**|
|VVSto ICS(offset)conversion ratio<br>KLFF<br>18<br>20<br>22<br>S<br>~~a~~<br>~~OO~~|
|Line feed−forward current on CS pin<br>DRV high, VVS= 2 V<br>IFF<br>35<br>40<br>45<br>A<br>~~OO~~|
|Offset current maximum value<br>Ioffset(MAX)<br>80<br>100<br>120<br>A<br>~~a~~|
|**VALLEY LOCKOUT SECTION**|
|Threshold for high− line range (HL) detection<br>VVSrising<br>VHL<br>2.28<br>2.40<br>2.52<br>V|
|Threshold for low−line range (LL) detection<br>VVSfalling<br>VLL<br>2.18<br>2.30<br>2.42<br>V|
|Blanking time for line range detection<br>tHL(blank)<br>15<br>25<br>35<br>ms|
|**FREQUENCY FOLDBACK**|
|Minimum additional dead time in frequency fold-<br>back mode<br>tFF1LL<br>1.4<br>2.0<br>2.6<br>s<br>Additional dead time<br>VREFX= 5% VREF<br>tFF2HL<br>−<br>40<br>−<br>s<br>Additional dead time<br>VREFX= 0% VREF<br>tFF3HL<br>90<br>−<br>s<br>~~ee~~<br>~~ee e~~~~**e**~~<br>~~a~~<br>~~O~~<br>~~a~~<br>~~GO~~|
|**FAULT PROTECTION**|
|Thermal Shutdown (Note 6)<br>FSW= 65 kHz<br>TSHDN<br>130<br>150<br>170<br>C<br>~~a~~<br>~~OO~~|
|Thermal Shutdown Hysteresis<br>TSHDN(HYS)<br>−<br>50<br>–<br>C<br>Threshold voltage for output short circuit or aux.<br>winding short circuit detection<br>VZCD(short)<br>0.8<br>1.0<br>1.2<br>V<br>Short circuit detection Timer<br>VZCD< VZCD(short)<br>tOVLD<br>70<br>90<br>110<br>ms<br>Auto−recovery timer duration<br>trecovery<br>3<br>4<br>5<br>s<br>~~SSeS~~<br>~~ee eee eee~~<br>~~a~~<br>~~OO~~|
|SD pin Clamp series resistor<br>RSD(clamp)<br>1.6<br>k<br>~~LO~~|
|Clamped voltage<br>SD pin open<br>VSD(clamp)<br>1.13<br>1.35<br>1.57<br>V<br>~~a~~<br>~~OO~~|
|SD pin detection level for OVP<br>VSDrising<br>VOVP<br>2.35<br>2.50<br>2.65<br>V<br>~~a~~<br>~~OO~~|
|Delay before OVP or OTP confirmation<br>TSD(delay)<br>22.5<br>30.0<br>37.5<br>s<br>Reference current for direct connection of an NTC<br>(Note 8)<br>IOTP(REF)<br>80<br>85<br>90<br>A<br>Fault detection level for OTP (Note 7)<br>VSDfalling<br>VOTP(off)<br>0.47<br>0.50<br>0.53<br>V<br>~~a~~<br>~~OO~~<br>~~ee~~<br>~~ee ee~~<br>~~a~~<br>~~OO~~|
|SD pin level for operation recovery after an OTP<br>VSDrising<br>VOTP(on)<br>0.66<br>0.70<br>0.74<br>V|
|detection|
|OTP blanking time when circuit starts operating<br>(Note 8)<br>tOTP(start)<br>250<br>370<br>s<br>SD pin voltage where thermal fold−back starts<br>(VREFis decreased)<br>VTF(start)<br>0.94<br>1.00<br>1.06<br>V<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|SD pin voltage at which thermal fold−back stops<br>(VREFis clamped to VREF50)<br>VTF(stop)<br>0.64<br>0.69<br>0.74<br>V|
|VTF(start)over IOTP(REF)ratio (Note 7)<br>TJ= +25C to +125C<br>RTF(start)<br>10.8<br>11.7<br>12.6<br>k<br>~~a~~|
6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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## **NCL30186**
**Table 4. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V, VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)
|(Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V,<br>VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)CS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)= 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)SD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)= 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)J = −40C to +125C, VCC = 12 V)= −40C to +125C, VCC = 12 V)|(Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V,<br>VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)CS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)= 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)SD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)= 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)J = −40C to +125C, VCC = 12 V)= −40C to +125C, VCC = 12 V)C to +125C, VCC = 12 V)C to +125C, VCC = 12 V)C, VCC = 12 V)C, VCC = 12 V)CC = 12 V)= 12 V)|(Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V,J = 25C, VCC = 12 V, VZCD = 0 V,= 25C, VCC = 12 V, VZCD = 0 V,|(Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V,J = 25C, VCC = 12 V, VZCD = 0 V,= 25C, VCC = 12 V, VZCD = 0 V,C, VCC = 12 V, VZCD = 0 V,C, VCC = 12 V, VZCD = 0 V,CC = 12 V, VZCD = 0 V,= 12 V, VZCD = 0 V,|(Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V,J = 25C, VCC = 12 V, VZCD = 0 V,= 25C, VCC = 12 V, VZCD = 0 V,C, VCC = 12 V, VZCD = 0 V,C, VCC = 12 V, VZCD = 0 V,CC = 12 V, VZCD = 0 V,= 12 V, VZCD = 0 V,|(Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V,J = 25C, VCC = 12 V, VZCD = 0 V,= 25C, VCC = 12 V, VZCD = 0 V,C, VCC = 12 V, VZCD = 0 V,C, VCC = 12 V, VZCD = 0 V,CC = 12 V, VZCD = 0 V,= 12 V, VZCD = 0 V,ZCD = 0 V,|(Unless otherwise noted: For typical values TJ = 25C, VCC = 12 V, VZCD = 0 V,J = 25C, VCC = 12 V, VZCD = 0 V,= 25C, VCC = 12 V, VZCD = 0 V,C, VCC = 12 V, VZCD = 0 V,C, VCC = 12 V, VZCD = 0 V,CC = 12 V, VZCD = 0 V,= 12 V, VZCD = 0 V,ZCD = 0 V,|
|---|---|---|---|---|---|---|
|VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)CS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)= 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)SD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)= 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)J = −40C to +125C, VCC = 12 V)= −40C to +125C, VCC = 12 V)<br>**Description**<br>**FAULT PROTECTION**<br>~~a~~|VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)CS = 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)= 0 V, VSD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)SD = 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)= 1.5 V) For min/max values TJ = −40C to +125C, VCC = 12 V)J = −40C to +125C, VCC = 12 V)= −40C to +125C, VCC = 12 V)C to +125C, VCC = 12 V)C to +125C, VCC = 12 V)C, VCC = 12 V)C, VCC = 12 V)CC = 12 V)= 12 V)<br>**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|VTF(stop)over IOTP(REF)ratio (Note 7)<br>~~a~~|TJ= +25C to +125C|RTF(stop)|7.4|8.1|8.8|k|
|VOTP(off)over IOTP(REF)ratio (Note 7)<br>~~a~~|TJ= +25C to +125C|ROTP(off)|5.4|5.9|6.4|k|
|VOTP(on)over IOTP(REF)ratio (Note 7)<br>~~a~~|TJ= +25C to +125C|ROTP(on)|7.5|8.1|8.7|k|
|VREFX@ VSD= 600 mV (as percentage of VREF)|SD pin falling (no OTP<br>detection)|VREF(50)|40|50|60|%|
|**BROWN−OUT**|||||||
|Brown−Out ON level (IC start pulsing)<br>~~a~~|VSrising|VBO(on)|0.95|1.00|1.05|V|
|Brown−Out OFF level (IC shuts down)<br>~~a~~|VSfalling|VBO(off)|0.85|0.90|0.95|V|
|BO comparators delay<br>~~a~~|tBO(delay)<br>30<br>s<br>~~a~~||||||
|Brown−Out blanking time<br>~~a~~||tBO(blank)|15|25|35|ms|
|VSpin Pulling−down Current<br>VS= VBO(on)<br>IBO(bias)<br>50<br>250<br>450<br>nA<br>~~OO~~|||||||
|**DIMMING SECTION**|||||||
|DIM pin voltage for zero output current|VDIMfalling|VDIM0|0.66|0.70|0.74|V|
|(OFF voltage)|||||||
|DIM pin voltage for maximum output current|VDIMrising|VDIM100||||V|
|(VREFX= VREF)|||||||
|TJ= −40C to +125C|||−|2.45|2.60||
|TJ= +25C to +85C**(NCL30186D only)**|||2.32|2.45|2.57||
|TJ= +25C**(NCL30186D only)**|||2.335|2.450|2.555||
|DIM pin voltage for 50% output current|VDIMrising or falling|VDIM50|1.35|1.57|1.75|V|
|(VREFX= 50% VREF)|||||||
|Output Current Internal Reference (VREFX) @|VDIM= 0.8225 V|VREF7||||mV|
|VDIM= 0.8225 V)**(NCL30186D only)**|||||||
|TJ= +25C to +50C|||9.4|14|18.6||
|Dimming range<br>VDIM(range)<br>1.75<br>V<br>Dimming pin pull−up current source<br>IDIM(pullup)<br>7.5<br>9.6<br>12<br>A<br>~~a~~|||||||
6. Guaranteed by Design 7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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**NCL30186**
## **TYPICAL CHARACTERISTICS**
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**----- Start of picture text -----**<br>
20.0 9.4<br>9.3<br>19.5<br>9.2<br>19.0 9.1<br>GESEEEES<br>POPE) 9.0 a a eee<br>18.5<br>8.9<br>18.0 8.8<br>17.5 J 8.7<br>8.6<br>17.0 8.5<br>16.5 HO 8.4 ER<br>8.3<br>16.0 PP 8.2 ett<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)<br>Figure 4. VCC Start−up Threshold vs. Figure 5. VCC Minimum Operating Voltage vs.<br>Temperature Temperature<br>11.5 6.0<br>5.8<br>11.0<br>5.6<br>10.5<br>5.4<br>Soe ee ee ee ee ee ee<br>10.0<br>5.2<br>TORE} reet<br>9.5 5.0<br>4.8<br>9.0<br>4.6<br>SSSSRSS] EERE<br>8.5<br>4.4 Pf fl<br>8.0<br>4.2<br>7.5 a 4.0 fT<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)<br> (V) (V)<br>CC(on) CC(off)<br>V V<br> (V) (V)<br>CC(hys) CC(reset)<br>V V<br>**----- End of picture text -----**<br>
**Figure 6. Hysteresis (VCC(on) − VCC(off)) vs. Temperature**
**Figure 7. VCC(reset) vs. Temperature**
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**NCL30186**
## **TYPICAL CHARACTERISTICS**
**==> picture [243 x 382] intentionally omitted <==**
**----- Start of picture text -----**<br>
28.0<br>27.8<br>|_| ff of ff<br>a<br>27.627.4 a<br>27.2<br>ee<br>OG<br>27.0<br>26.8 a<br>26.6 oO<br>26.4<br>—T_L_ LLL<br>a A<br>26.2<br>|<br>26.0<br>| fof of of fF<br>a<br>25.8<br>25.6 TT TI ITE<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>Figure 8. VCC Over Voltage Protection<br>Threshold vs. Temperature<br>150<br>125<br>100<br>- 75 1 | ft | | |yy.<br>50 TTePeeey<br>25<br>0<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (V)<br>CC(ovp)<br>V<br>A)<br> (<br>ICC(sfault)<br>**----- End of picture text -----**<br>
**Figure 10. Start−up Current in Fault Mode vs. Temperature**
**==> picture [243 x 172] intentionally omitted <==**
**----- Start of picture text -----**<br>
3.8<br>3.6<br>fpa{| ff ff ff<br>3.4<br>3.2 es<br>3.0<br>2.8 poes ff<br>2.6<br>re ee<br>2.4 eee<br>2.2 >)<br>2.0<br>p—_{a_{ { { —} —} {1<br>1.8 a<br>1.6<br>1.4 $$<br>1.2 a ee ee<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (mA)<br>ICC2<br>**----- End of picture text -----**<br>
**Figure 12. ICC2 vs. Temperature**
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**----- Start of picture text -----**<br>
4035 P| | | | | ff<br>30<br>25 P|P| || || || |[| ff| ft<br>20 P| | | | [| | ft<br>ee ee<br>15<br>— —— ee<br>—+—<br>10<br>TT | | dt<br>5 P| | | | [| ff<br>0 P| | | | | | ff<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>A)<br> (<br>ICC(start)<br>**----- End of picture text -----**<br>
**Figure 9. Start−up Current vs. Temperature**
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**----- Start of picture text -----**<br>
2.0<br>1.8<br>1.6<br>1.4<br>1.2 AREER<br>1.0<br>epee<br>0.8<br>0.6<br>0.4<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (mA)<br>ICC1<br>**----- End of picture text -----**<br>
**Figure 11. ICC1 vs. Temperature**
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**----- Start of picture text -----**<br>
5.04.54.0 PotP| | | | | | ft<br>3.5 P|fff| | | [| | ft<br>3.0 P| | | | [| ff<br>eeee ee<br>2.5<br>2.01.5 fefTP|| || || J| ft[| ff<br>fd<br>1.0 | [| | | | [| ff<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (mA)<br>ICC3<br>**----- End of picture text -----**<br>
**Figure 13. ICC3 vs. Temperature**
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**NCL30186**
## **TYPICAL CHARACTERISTICS**
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**----- Start of picture text -----**<br>
1.051.031.04 eeee ee eeeeee<br>1.02 ee ee ee<br>1.01 ee ee ee<br>1.00 ee<br>0.99 a ee ee<br>0.98 em | | | | eee| ft ft<br>0.97 ee ee ee e e<br>0.950.96 Pfa | ct ET<br>−50 −25 0 25 50 75 100 125 150<br> (V)<br>ILIM<br>V<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE (C)<br>**----- End of picture text -----**<br>
**Figure 14. Maximum Internal Current Limit vs. Temperature**
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**----- Start of picture text -----**<br>
400380360 PFa| tf<br>340 PF | tfEE<br>320 PF | tfEE<br>300 EE<br>280 Ff; | | Tl<br>260 PFa | tfee ee<br>240 Pt tTEE<br>220 P| tT EE<br>200 ee ee<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (ns)<br>LEB<br>T<br>**----- End of picture text -----**<br>
**Figure 15. Leading Edge Blanking vs. Temperature**
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**----- Start of picture text -----**<br>
150 50<br>140<br>pf ff ff ff 48 ee ee ee<br>130<br>120 46<br>110 PP errr] 44 fey<br>100<br>90 42<br>80 PP errr 40 |Pt| fe<br>70<br>60 38<br>50 po | pe<br>36<br>40<br>30 34<br>20 pr pee<br>32<br>10<br>0 => 30<br>-<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)<br>Figure 16. Current Limit Propagation Delay vs. Figure 17. Maximum On−time vs. Temperature<br>Temperature<br>1.581.601.56 a a ee 220210200 aa eees es ee<br>es ee 190 a ee ee<br>1.54<br>1.52 es a 180 a ee<br>170<br>1.50 ee ee<br>160<br>1.48 a ee ee ee es<br>150<br>1.46 ee ee a<br>140<br>a ee ee a<br>1.44 eee 130 es<br>1.42 120<br>1.40 BRR 110 EEE EEE<br>1.38 es 100 es ee<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)<br>s)<br> (<br> (ns)<br>ILIM<br>T ON(max)<br>T<br> (V)<br> (ns)<br>BCS<br>CS(stop) T<br>V<br>**----- End of picture text -----**<br>
**Figure 18. VCS(stop) vs. Temperature**
**Figure 19. Leading Edge Blanking Duration for VCS(stop) vs. Temperature**
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**NCL30186**
## **TYPICAL CHARACTERISTICS**
**==> picture [489 x 382] intentionally omitted <==**
**----- Start of picture text -----**<br>
600 100<br>580 a a 90 P| tf | | ft ff<br>560<br>80<br>a<br>540<br>a 520 eea OO OO 70 tTP| Ff |enffee eefteee<br>500 60<br>480<br>|| 50 |<br>460 —T7T a P| [| | | | ff<br>| | | [| | [| 40 ry TUT UU<br>440<br>420 Pf ff pe FY 30 P| | | f ft ft<br>400 a 20 | | | | | | | ft |<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)<br>Figure 20. ICS(short) vs. Temperature Figure 21. VCS(low), VCS Rising vs.<br>Temperature<br>20 40<br>38<br>18<br>36<br>16 Ff [| | fF ft ff 34 a es<br>32<br>14<br>30<br>12 28<br>a 26 el—_|—_|_|<br>10<br>24<br>8 22<br>aneLi 20 ap<br>6 — a<br>18<br>4 H+; | | | [| | | 16 a<br>14<br>2<br>0 a 101212 a<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)J, JUNCTION TEMPERATURE (C), JUNCTION TEMPERATURE (C)C)C)<br>A)<br> ( (mV)<br>ICS(short) VCS(low)<br>) )<br> ( (<br>SNK SRC<br>R R<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
40<br>38<br>36<br>34 a es<br>32<br>30<br>28<br>26 el—_|—_|_|<br>24<br>22<br>20 ap<br>a<br>18<br>16 a<br>14<br>101212 a<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)J, JUNCTION TEMPERATURE (C), JUNCTION TEMPERATURE (C)C)C)<br>)<br> (<br>SRC<br>R<br>**----- End of picture text -----**<br>
**Figure 22. Sink Gate Drive Resistance vs. Temperature**
**Figure 23. Source Gate Drive Resistance vs. Temperature**
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**----- Start of picture text -----**<br>
453050403525 Poteeeeeeee ee eeT ee| [ eeyt TT 7<br>20 eee<br>15 ee ee ee<br>ee<br>10<br>5 ee<br>0 | | | | tf ff fl<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (ns)tr<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
3515305045402520 Poteeeeeeeeeeee[| eeeeeeeeeeee| [ eeeeeeeeeeyt Ty<br>L—+—-~—<br>10<br>5 | | | [| | |<br>0 |ee| | eetf tfeeff<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (ns)<br>tF<br>**----- End of picture text -----**<br>
**Figure 24. Gate Drive Rise Time vs. Temperature**
**Figure 25. Gate Drive Fall Time (CDRV = 470 pF) vs. Temperature**
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**NCL30186**
## **TYPICAL CHARACTERISTICS**
**==> picture [242 x 173] intentionally omitted <==**
**----- Start of picture text -----**<br>
9.89.49.6 FoTy| oTJf TUEJ ff UOTff<br>II<br>9.2 TES<br>9.0 |__| ———————<br>8.88.6 eePf tf ee| eee| ft fd<br>TEE<br>8.4<br>8.2 | | | | ft | lt |<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (V)<br>DRV(low)<br>V<br>**----- End of picture text -----**<br>
**Figure 26. DRV Low Voltage vs. Temperature**
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**----- Start of picture text -----**<br>
15.0<br>14.5 PF | | fl rE<br>14.0<br>PF | | [| Ff ff<br>13.5<br>PF | | ft fF ft<br>13.0<br>12.5 EE<br>12.0<br>| | |<br>11.5<br>es a<br>11.0<br>SF<br>10.5<br>10.0 aee ee ee ee<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (V)<br>DRV(high)<br>V<br>**----- End of picture text -----**<br>
**Figure 27. DRV High Voltage vs. Temperature**
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**----- Start of picture text -----**<br>
150140 Sn<br>130 SEEEEEER<br>120<br>100110 Saa<br>90<br>80 aSee<br>70 ee ee ee e e<br>506040 Sees es<br>30 a<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (mV)<br>ZCD(rising)<br>V<br>**----- End of picture text -----**<br>
**Figure 28. Upper ZCD Threshold Voltage vs. Temperature**
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**----- Start of picture text -----**<br>
80<br>75<br>70 EEREPEEE<br>65<br>60 a<br>55<br>5045 aFREEee S<br>40<br>35 PF | | f[ tf tf [ft]<br>30 | | {| | | | [| [ |<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (mV)<br>ZCD(falling)<br>V<br>**----- End of picture text -----**<br>
**Figure 29. Lower ZCD Threshold vs. Temperature**
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**----- Start of picture text -----**<br>
4550 a ee ee 2.01.9 ee<br>40 PF 1.8 ee<br>35 PF | | ct rE 1.7 a<br>30 FP | | tlrE 1.6 a<br>i | | | fl fllt le pot of hf | |<br>25 1.5<br>20 PF | | eetl rE ee 1.4 PF+++| | ht<br>15 PF | | tl rE 1.3 eeEET<br>105 PFPF || || || fFftft 1.21.1 eeeee e e eeee eeee<br>0 | | | | | | [ [ | 1.0 | | | | ee| | ee[ ee[|<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)<br>s)<br> (<br> (mV)<br>VZCD(HYS) tZCD(blank1)<br>**----- End of picture text -----**<br>
**Figure 30. ZCD Hysteresis vs. Temperature**
**Figure 31. ZCD Blanking Delay vs. Temperature**
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**NCL30186**
## **TYPICAL CHARACTERISTICS**
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**----- Start of picture text -----**<br>
7.8<br>7.6<br>7.4<br>7.2<br>7.0<br>~ 6.8 { | | | | | ft ff<br>6.6<br>6.4 ee ee ee ee ee<br>6.2<br>6.0<br>5.8<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>s)<br> (<br>TIMO<br>T<br>**----- End of picture text -----**<br>
**Figure 32. ZCD Time−out vs. Temperature**
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256<br>255<br>254<br>253<br>252<br>251<br>250 aOO<br>249<br>248<br>pf ff [ft]<br>247<br>246<br>245<br>244<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (mV)<br>REF<br>V<br>**----- End of picture text -----**<br>
**Figure 33. Reference Voltage vs. Temperature (A and B versions)**
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110 60<br>100 58<br>90<br>56<br>80<br>54<br>70<br>52<br>60 a a ee<br>50<br>50 —— a — reee<br>48<br>40<br>po | | PT pf i} fj ft ff eeeft<br>46<br>30<br>20 44<br>10 42<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)<br>S)<br> (mV)<br> (<br>EA<br>CS(low) G<br>V<br>**----- End of picture text -----**<br>
**Figure 34. Current Sense Lower Threshold (VCS Falling) vs. Temperature**
**Figure 35. Error Amplifier Trans−conductance Gain vs. Temperature**
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22.0<br>21.5<br>21.0<br>20.5<br>~ 20.0 Cpe rrrr y .<br>19.5<br>Oa [OO] ——— =<br>19.0<br>18.5<br>18.0<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>S)<br>A)<br> (<br> (<br>KLFF IFFFF<br>**----- End of picture text -----**<br>
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44<br>43<br>42<br>41<br>40 (pee erry<br>39<br>= SS<br>38<br>37<br>36<br>−50 −25 0 25 50 75 100 125 150<br>A)<br> (<br>IFFFF<br>**----- End of picture text -----**<br>
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TJ, JUNCTION TEMPERATURE (C)<br>**----- End of picture text -----**<br>
**Figure 37. Line Feedforward Current on CS Pin (@ VVS = 2 V) vs. Temperature**
**Figure 36. Feedforward VVS to ICS(offset) Conversion Ratio vs. Temperature**
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**NCL30186**
## **TYPICAL CHARACTERISTICS**
**==> picture [242 x 156] intentionally omitted <==**
**----- Start of picture text -----**<br>
120<br>115<br>110<br>105<br>100<br>95 ee ee eee<br>90<br>85<br>80<br>−50 −25 0 25 50 75 100 125 150<br>A)<br> (<br>Ioffset(MAX)<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE (C)<br>**----- End of picture text -----**<br>
**Figure 38. Ioffset(MAX) vs. Temperature**
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**----- Start of picture text -----**<br>
2.60<br>2.55<br>2.50<br>2.45<br>2.40<br>2.35<br>P| | | | [| ff<br>2.30<br>2.25 fe ee<br>2.20<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>Figure 40. Threshold for Low−line Range<br>Detection vs. Temperature<br>1.20<br>1.15<br>1.10<br>1.05<br>0.950.901.00 TTTP| | | | fffLe<br>0.85<br>0.80<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (V)<br>LL<br>V<br> (V)<br>ZCD(short)<br>V<br>**----- End of picture text -----**<br>
**Figure 42. Threshold Voltage for Output Short Circuit Detection vs. Temperature**
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**----- Start of picture text -----**<br>
2.55<br>2.50<br>2.45<br>2.40 [_ a<br>2.35<br>2.30<br>2.25<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (V)<br>HL<br>V<br>**----- End of picture text -----**<br>
**Figure 39. Threshold for High−line Range Detection vs. Temperature**
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40<br>38<br>36<br>34<br>32<br>30<br>28<br>26 — a a a<br>24<br>ee ee<br>22<br>20<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>Figure 41. Blanking Time for Low−line Range<br>Detection vs. Temperature<br>115<br>110<br>105<br>100<br>959085 P|P| || || || ft[| ff]ff<br>80<br>75<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (ms)<br>HL(blank)<br>T<br> (ms)<br>tOVLD<br>**----- End of picture text -----**<br>
**Figure 43. Short Circuit Detection Timer vs. Temperature**
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**TYPICAL CHARACTERISTICS**
**==> picture [242 x 156] intentionally omitted <==**
**----- Start of picture text -----**<br>
5.00<br>4.75 TT... TT<br>4.50 Pf tf | tf ft ft<br>4.25<br>4.00 ee ee ee eee<br>3.753.50 Pf | | | ft ft |<br>3.253.00 rTFFPP oT<br>−50 −25 0 25 50 75 100 125 150<br> (s)<br>recovery<br>T<br>**----- End of picture text -----**<br>
TJ, JUNCTION TEMPERATURE (C)
**Figure 44. Auto−recovery Timer Duration vs. Temperature**
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2.20<br>2.10<br>PTTL<br>2.00<br>1.90 a LL LLL<br>1.80<br>1.70<br>1.60 es<br>1.50<br>1.40<br>1.30 a<br>1.20<br>a<br>1.10<br>1.00 aPTE EEE<br>−50 −25 0 25 50 75 100 125 150<br>)<br> (k<br>SD(clamp)<br>R<br>**----- End of picture text -----**<br>
TJ, JUNCTION TEMPERATURE (C)
**Figure 45. SD Pin Clamp Series Resistor vs. Temperature**
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1.60 2.58<br>1.55 PF | [| tf ft tft 2.56 | | [| | | | | ft |<br>1.50 2.54<br>1.45<br>2.52<br>1.40 ee P| tf fF | tf<br>2.50<br>1.35 eer Ft<br>—T 2.48 _ =|<br>1.30 TTL ee<br>1.251.20 esee 2.462.44 PFee| ee |ee| | | ft ffee<br>1.15 a ee e e 2.42 Pf | [| tf ff<br>1.10 ee ee 2.40 PF | | | jf ft ft |<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br> (V)<br> (V)<br>OVP<br>V<br>SD(clamp)<br>V<br>**----- End of picture text -----**<br>
TJ, JUNCTION TEMPERATURE (C)
**Figure 46. SD Pin Clamp Voltage vs. Temperature**
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TJ, JUNCTION TEMPERATURE (C)<br>**----- End of picture text -----**<br>
**Figure 47. SD Pin OVP Threshold Voltage vs. Temperature**
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38 91<br>90<br>ee ee PLL LLL LL<br>36<br>89<br>34 P| | | tf ft ff 88 a<br>87<br>32<br>86<br>30 85<br>84<br>28 P| | | | f | fy ee eee<br>83<br>26 P| 82 gO<br>81<br>24 TT | [| oo| ft ff aes<br>80<br>22 P| | | [| ff ff 79 a<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)<br>s) A)<br> ( (<br>TSD(delay) IOTP(REF)<br>**----- End of picture text -----**<br>
**Figure 48. TSD(delay) vs. Temperature**
**Figure 49. IOTP(REF) vs. Temperature**
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## **TYPICAL CHARACTERISTICS**
**==> picture [242 x 173] intentionally omitted <==**
**----- Start of picture text -----**<br>
12.5<br>12.4<br>12.3 ee<br>12.2<br>12.1 ee ee ee ee eee<br>12.0<br>ee 11.9<br>11.8<br>11.7<br>11.6<br>11.5<br>11.4<br>11.3 ee<br>11.2<br>11.011.1 eeea<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>)<br> (k<br>TF(start)<br>R<br>**----- End of picture text -----**<br>
**Figure 50. RTF(start) vs. Temperature**
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8.8<br>8.7<br>8.6 $$$ $$}<br>8.5 a<br>8.4<br>8.3<br>8.2<br>8.1<br>8.0<br>7.9<br>7.8 po fof Pf<br>7.7 a<br>7.6 a ee<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>)<br> (k<br>TF(stop)<br>R<br>**----- End of picture text -----**<br>
**Figure 51. RTF(stop) vs. Temperature**
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**----- Start of picture text -----**<br>
6.46.3 rT | | | Ff | ff<br>6.2<br>6.1 ee ee ee<br>oe 6.0 f | ff ye [fe)]<br>5.9<br>5.8 SER |EEEC| ||i<br>5.7<br>5.6 a ee ee<br>5.5 a a<br>5.4 a ee<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>)<br> (k<br>OTP(off)<br>R<br>**----- End of picture text -----**<br>
**Figure 52. ROTP(off) vs. Temperature**
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8.8<br>8.7 ae ee ee ee e e<br>8.6<br>8.5<br>ew 8.4 es<br>8.3<br>8.2<br>8.1 RSeE EEE<br>8.0<br>7.9<br>ee<br>7.77.8 es es<br>7.6 Fs<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br>)<br> (k<br>OTP(on)<br>R<br>**----- End of picture text -----**<br>
**Figure 53. ROTP(on) vs. Temperature**
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5554 aeeee eeee<br>5352 a ee ee ee ee<br>51 a ee ee ee ee<br>50 a<br>a<br>49<br>a a<br>48<br>a ee ee ee ee<br>47<br>a ee ee ee<br>46<br>45 a ee ee ee<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (%)<br>REF(50)<br>V<br>**----- End of picture text -----**<br>
**Figure 54. Ratio VREF(50) over VREF vs. Temperature**
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1.051.04 aa eeee ee<br>1.03<br>1.021.01 aa eee e e ee<br>1.00 ee ee<br>| | | | tf fT |<br>0.99<br>SS eee<br>0.98<br>0.97 came<br>a ee ee<br>0.96<br>0.95 a ee ee ee ee<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (V)<br>BO(on)<br>V<br>**----- End of picture text -----**<br>
**Figure 55. Brown−out ON Level vs. Temperature**
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## **TYPICAL CHARACTERISTICS**
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**----- Start of picture text -----**<br>
0.95 35<br>Tee 34<br>0.94<br>0.93 ee ee ee 3332 a a<br>31<br>0.920.91 Teeee ee ee 2930 aeee<br>28<br>0.90 a<br>27<br>0.89 —rT [| | | | [| ft 26 a<br>0.88 ee 25<br>24<br>0.87 ee ee ee e e 23 a a<br>22<br>0.86<br>0.85 a 2021<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C)<br>Figure 56. Brown−out OFF Level vs. Figure 57. Brown−out Blanking Time vs.<br>Temperature Temperature<br>500<br>450<br>a ee ee e e<br>400<br>a ee ee eee<br>350<br>a ee ee eee<br>300250 a eeee ee eee<br>150100200500 foaaaa eeeeeeee eeeeee eeeee eee<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (C)<br> (V) (ms)<br>BO(off)<br>V<br>tBO(blank)<br> (nA)<br>IBO(bias)<br>**----- End of picture text -----**<br>
**Figure 58. VS Pin Pulling−down Current vs. Temperature**
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## **Application Information**
The NCL30186 is a driver for power−factor corrected flyback and non−isolated buck−boost/ SEPIC converters. It implements a current−mode, quasi−resonant architecture including valley lockout and frequency fold−back capabilities for maintaining high−efficiency performance over a wide load range. A proprietary circuitry ensures both accurate regulation of the output current (without the need for a secondary−side feedback) and near−unity power factor correction. The circuit contains a suite of powerful protections to ensure a robust LED driver design without the need of extra external components or overdesign
- **Quasi−Resonance Current−Mode Operation:** implementing quasi−resonance operation in peak current−mode control, the NCL30186 optimizes the efficiency by turning on the MOSFET when its drain−source voltage is minimal (valley). In light−load conditions, the circuit changes valleys to reduce the switching losses. For a stable operation, the valley at which the MOSFET switches on remains locked until the input voltage or the output current set−point significantly changes.
- **Primary−Side Constant−Current Control with Power Factor Correction:** a proprietary circuitry allows the LED driver to achieve both near−unity power factor correction and accurate regulation of the output current without requiring any secondary−side feedback (no optocoupler needed). A power factor as high as 0.99 and an output current deviation below 2% are typically obtained.
- **Linear or PWM dimming:** the DIM pin allows implementing both analog and PWM dimming.
- **Main protection features:**
- **Over Temperature Thermal Fold−back/ Shutdown/Over Voltage Protection:** the NCL30186 features a gradual current foldback to protect the driver from excessive temperature down to 50% of the programmed current. If the temperature continues to rise after this point to a second level, the controller stops operating. This mode would only be expected to be reached under normal conditions if there is a severe fault. The first and second temperature thresholds depend on the
NTC connected to the circuit SD pin. The SD pin can also be used to shutdown the device by pulling this pin below the VOTP(off) min level . A Zener diode can also be used to pull−up the pin and stop the controller for adjustable OVP protection. Both protections are latching−off (A and C versions) or auto−recovery (the circuit can recover operation after 4−s delay has elapsed − B and D versions).
- **Cycle−by−cycle peak current limit:** when the current sense voltage exceeds the internal threshold VILIM, the MOSFET is immediately turned off.
- **Winding or Output Diode Short−Circuit Protection:** an additional comparator senses the CS signal and stops the controller if it exceeds 150% x VILIM for 4 consecutive cycles. This feature can protect the converter if a winding is shorted or if the output diode is shorted or simply if the transformer saturates. This protection is latching−off (A and C versions) or auto−recovery (B and D versions).
- **Output Short−circuit protection:** if the ZCD pin voltage remains low for a 90−ms time interval, the controller detects that the output or the ZCD pin is grounded and hence, stops operation. This protection is latching−off (A and C versions) or auto−recovery (B and D versions).
- **Open LED protection:** if the VCC pin voltage exceeds the OVP threshold, the controller shuts down and waits 4 seconds before restarting switching operation.
- **Floating or Short Pin Detection:** NCL30186 protections aid in pass safety tests. For instance, the circuit stops operating when the CS pin is grounded or open.
## **Power Factor and Constant Current Control**
The NCL30186 embeds an analog/digital block to control the power factor and regulate the output current by monitoring the ZCD, VS and CS pin voltages (signals ZCD, VS and VCS of Figure 59). This circuitry generates the current setpoint (VCONTROL/4) and compares it to the current sense signal (VCS) to dictate the MOSFET turning
off event when VCS exceeds VCONTROL/4.
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ZCD STOP VVS VREF<br>VCS Power Factor and PWM Latch reset<br>Constant−Current<br>Control<br>COMP<br>DIM_disable<br>C1<br>to<br>Figure 59. Power Factor and Constant−Current Control<br>www.onsemi.com<br>**----- End of picture text -----**<br>
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The VS pin provides the sinusoidal reference necessary for shaping the input current. The obtained current reference is further modulated so that when averaged over a half−line period, it is equal to the output current reference (VREFX). This averaging process is made by an internal Operational Trans−conductance Amplifier (OTA) and the capacitor connected to the COMP pin (C1 in Figure 59). Typical COMP capacitance is 2.2 F and should not be less than 1 u u F to ensure stability. The COMP ripple does not affect the power factor performance as the circuit digitally eliminates it when generating the current setpoint.
If the VS pin properly conveys the sinusoidal shape, power factor will be close to 1. Also, the Total Harmonic Distortion (THD) will be low, especially if the output voltage ripple is small. In any case, the output current will be well regulated following the equation below:
**==> picture [213 x 23] intentionally omitted <==**
Where:
- NPS is the secondary to primary transformer turns NPS = NS / NP
- Rsense is the current sense resistor (see Figure 1).
- VREFX is the output current internal reference. VREFX = VREF (250 mV in A and B versions and 200 mV in C and D versions, typically) at full load.
The output current reference (VREFX) is VREF unless thermal fold−back is activated by the SD pin voltage being reduced below 1 V typical (see “protections” section) or unless the DIM pin voltage is below VDIM100 (see analog dimming section).
If a major fault is detected, the circuit enters the latched−off or auto−recovery mode and the COMP pin is grounded (except in an UVLO condition). This ensures a clean start−up when the circuit resumes operation.
## **Start−up Sequence**
Generally an LED lamp is expected to emit light in < 1 sec and typically within 300 ms. The start−up phase consists of
the time to charge the VCC capacitor, initiate startup and begin switching and the time to charge the output capacitor until sufficient current flows into the LED string. To speed−up this phase, the following defines the start−up sequence:
- The COMP pin is grounded when the circuit is off. The average COMP voltage needs to exceed the VS pin peak value to have the LED current properly regulated (whatever the current target is). To speed−up the COMP capacitance charge and shorten the start−up phase, an internal 80−A current source adds to the OTA sourced u current (60 A max typically) to charge up the COMP u capacitance. The 80−A current source remains on until u the OTA starts to sink current as a result of the COMP pin voltage sufficient rise. At that moment, the COMP pin being near its steady−state value, it is only driven by the OTA.
- If VCC drops below the VCC(off) threshold because the circuit fails to start−up properly on the first attempt, a new attempt takes place as soon as VCC is recharged to VCC(on). The COMP voltage is not reset at that moment. Instead, the new attempt starts with the COMP level obtained at the end of the previous operating phase.
- If the load is shorted, the circuit will operate in hiccup mode with VCC oscillating between VCC(off) and VCC(on) until the AUX_SCP protection trips (AUX_SCP is triggered if the ZCD pin voltage does not exceed 1 V within a 90−ms operation period of time thus indicating a short to ground of the ZCD pin or an excessive load preventing the output voltage from rising). The NCL30186A and NCL3006C latch off in this case. With the B and D versions, the AUX_SCP protection forces the 4−s auto−recovery delay to reduce the operation duty−ratio. Figure 60 illustrates a start−up sequence with the output shorted to ground, in this second case.
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## **NCL30186**
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**----- Start of picture text -----**<br>
V<br>CC(on)<br>VCC<br>V<br>CC(off)<br> <br>time<br>AUX_SCPtrips<br>as t 1 t 2 t 3 tOVLD<br>DRV [t] 1 |a [t] 3 tOVLD 0 ms [t] 1 [t] 3 time<br>[t] 2 [t] 2<br>trecovery s trecovery s <br>**----- End of picture text -----**<br>
**Figure 60. Start−up Sequence in a Load Short−circuit Situation (auto−recovery versions)**
## **Zero Crossing Detection Block**
The ZCD pin detects when the drain−source voltage of the power MOSFET reaches a valley by crossing below the 55−mV internal threshold (VZCD(TH)). At startup or in case of extremely damped free oscillations, the ZCD comparator may not be able to detect the valleys. To avoid such a
situation, the NCL30186 features a time−out circuit that generates pulses if the voltage on ZCD pin stays below the 55−mV threshold for 6.5 s nominal. The time−out also acts as a substitute clock for the valley detection and simulates a missing valley in case the free oscillations are too damped.
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**----- Start of picture text -----**<br>
t ZCD(blank1)<br>t ZCD(blank) @<br><<br>FF_mode<br>t ZCD(blank2)<br>\/<br>ZCD<br>+<br>VZCD(TH)<br>− Clock<br>Time−Out<br>Ie<br>+<br>VZCD(short) —— +<br>−<br>−<br>S<br>Q Aux_SCP<br>Q<br>90−ms Timer<br>~ c R a<br>4−s Timer (auto−recovery version)<br>Vcc<Vcc(reset) (latching−off version) ><br>**----- End of picture text -----**<br>
**Figure 61. Zero Current Detection Block**
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**NCL30186**
If the ZCD pin or the auxiliary winding happen to be shorted, the time−out function would normally make the controller keep switching and hence lead to improper LED current value. The “AUX_SCP” protection prevents such a stressful operation: a secondary timer starts counting that is only reset when the ZCD voltage exceeds the VZCD(short) threshold (1 V typically). If this timer reaches 90 ms (no ZCD voltage pulse having exceeded VZCD(short) for this time period), the controller detects a fault and stops operation for 4 seconds (B and D versions) or latches off (A and C versions).
The “clock” shown in Figure 61 is used by the “valley selection frequency foldback” circuitry of the block diagram (Figure 3), to generate the next DRV pulse (if no fault prevents it):
- After the appropriate number of “clock” pulses in thermal foldback mode
**For an optimal operation, the maximum ZCD level should be maintained below 5 V to stay safely below the built in clamping voltage of the pin.**
## **Line Range Detection**
As sketched in Figure 62, this circuit detects the low−line range if the VS pin remains below the VLL threshold (2.3 V typical) for more than the 25−ms blanking time. High−line is detected as soon as the VS pin voltage exceeds VHL (2.4 V typical). These levels roughly correspond to 184−V rms and 192−V rms line voltages if the external resistors divider applied to the VS pin is designed to provide a 1−V peak value at 80 V rms.
- Immediately when the clock occurs in QR mode at low line or valley 2 at high line (full load)
**Figure 62. Line Range Detection**
In the low−line range, conduction losses are generally dominant. Adding a dead−time would further increase these losses. Hence, only a short dead−time is necessary to reach the MOSFET valley. In high−line conditions, switching losses generally are the most critical. It is thus efficient to skip one valley to lower the switching frequency. Hence, under normal operation, the NCL30186 optimizes the
efficiency over the line range by turning on the MOSFET at the first valley in low−line conditions and at the second valley in the high−line case. This is illustrated by Figure 63 that sketches the MOSFET Drain−Source voltage in both cases. In the event that thermal foldback is activated, additional valleys can be skipped as the power is reduced.
**Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line (right)**
## **Line Feedforward**
To compensate for current regulation errors due to AC line variation, the NCL30186 includes a method to add line feedforward adjustment. As illustrated by Figure 64, the input voltage is sensed by the VS pin and converted into a
current. By adding an external resistor in series between the sense resistor and the CS pin, a voltage offset proportional to the input voltage is added to the CS signal for the MOSFET on−time.
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**NCL30186**
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**----- Start of picture text -----**<br>
Bulk rail<br>vDD<br>VS<br>I CS(offset) CS RCS<br>Rsense<br>Q_drv<br>**----- End of picture text -----**<br>
**Figure 64. Line Feed−Forward Schematic**
In Figure 64, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise.
## **PWM or Linear Dimming Detection**
The DIM pin of the NCL30186 is provided to implement linear and/or PWM dimming of the LED current.
Where:
- NPS is the secondary to primary transformer turns
Applying a voltage on the DIM pin voltage (VDIM) forces the output current internal reference to operate in one of three regions:
**==> picture [59 x 11] intentionally omitted <==**
- Rsense is the current sense resistor (see Figure 1).
- VREF is the output current internal reference (250 mV typically)
**==> picture [220 x 62] intentionally omitted <==**
- Iout,nom is the full−load output current.
The DRV output is disabled whenever the DIM pin voltage is lower than VDIM0 and the output current setpoint is maximal when VDIM exceeds VDIM100. Thus, for PWM dimming, a PWM signal with a low−state value below VDIM0 and a high−state value above VDIM100 should be applied.
VDIM0 and VDIM100 respectively, are 0.7 V and 2.45 V typically.
The output current can then be controlled by the DIM pin as follows:
In this case, the output current will be:
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**----- Start of picture text -----**<br>
Iout 0 V if VDIM VDIM0 (eq. 3) Iout Iout,nom d<br>Iout Iout,nom 2 NPSREFRsense if VDIM VDIM100<br>V V<br>Iout V DIM VDIM0 Iout,nom otherwise<br>DIM100 DIM0<br>VDIM<br>VDIM100<br>VDIM0<br>time<br>Iout<br>Iout,nom<br>0 A<br>time<br>**----- End of picture text -----**<br>
**==> picture [202 x 11] intentionally omitted <==**
Where d is the duty ratio of the DIM pin signal.
**Figure 65. Pin DIM Chronograms**
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**NCL30186**
## _Notes:_
- The current does not immediately reach its new target value when the PWM dimming signal state changes due to system time constants like the time necessary to charge or discharge the output capacitor to the required level. The output current settling time can hence affect the obtained output current, particularly if the PWM signal frequency is high.
- If either the high−state (VDIM(high)) or low−state level (VDIM(low)) of the input or both are between VDIM0 and VDIM100, the output current will be proportionally reduced as both analog and PWM dimming are simultaneous active, thus the output current will be:
**==> picture [477 x 90] intentionally omitted <==**
- If thermal foldback is activated as well, the current reduction is cumulative. For instance, if the DIM pin voltage and the thermal foldback respectively, reduces the output current setpoint by 50% and 20% respectively, the output current will be 80%*50% that is 40% of its nominal level.
The DIM pin is pulled up internally by a 10 A current source. Thus, if the pin is let open, the controller is able to start.
For any power factor corrected single stage architecture there will be a component of line ripple (100 / 120 Hz) on the output. If PWM dimming is used, it is recommended to select the dimming frequency to be sufficiently high not to generating beat frequencies that could create optical artifacts.
**>> As a general rule, the minimum PWM frequency should be at least 2.5x the line ripple frequency and not be set near multiples of the line frequency.**
## **Protections**
The circuit incorporates a full suite of protection features listed below to make the LED driver very rugged.
## **Output Short Circuit Situation**
An overload fault is detected if the ZCD pin voltage remains below VZCD(short) for 90 ms. In such a situation, the circuit stops generating pulses until the 4−s delay auto−recovery time has elapsed (B and D versions) or latches off (A and C versions).
## **Winding or Output Diode Short Circuit Protection**
If a transformer winding happens to be shorted, the primary inductance will collapse leading the current to ramp up in a very abrupt manner. The VILIM comparator (current limitation threshold) will trip to open the MOSFET and eventually stop the current rise. However, because of the abnormally steep slope of the current, internal propagation delays and the MOSFET turn−off time, a current rise > 50% of the nominal maximum value set by VILIM is possible. As illustrated in Figure 66, an additional circuit monitors for this current overshoot to detect a winding short circuit. The leading edge blanking (LEB) time for short circuit protection (LEB2) is significantly faster than the LEB time for cycle−by−cycle protection (LEB1). Practically, if four consecutive switching periods lead the CS pin voltage to exceed (VCS(stop) = 150% * VILIM), the controller enters the auto−recovery mode (4−s operation interruption between active bursts with versions B and D) or latches off (versions A and C).
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**==> picture [439 x 202] intentionally omitted <==**
**----- Start of picture text -----**<br>
S<br>Q DRV Vdd UVLO aux<br>Q<br>= _ i<br>CS R TSDBONOK Vcc VCC<br>LEB1 + PWMreset UVLO management<br>Vcontrol / 4 −<br>latch<br>4−s timer VCCreset<br>+ Ipkmax STOP (grand<br>− reset)<br>j> C t<br>VILIMIT AUX_SCP<br>SD Pin OVP<br>LEB2 + WOD_SCP 4−pulse (OVP2) VCC(ovp)<br>− counter OTP<br>S VCS(stop) e S OFF S latch<br>Q Q<br>Q Q<br>AUTORECOVERY LATCHING−OFF<br>R (B and D versions) R (A and C versions)<br>4−s timer VCCreset<br>**----- End of picture text -----**<br>
**Figure 66. Winding Short Circuit Protection, Max. Peak Current Limit Circuits**
## **VCC Over Voltage Protection**
The circuit stops generating pulses if VCC exceeds VCC(OVP) and enters auto−recovery mode. This feature protects the circuit in the event that the output LED string is disconnected or an individual LED in the string happens to fail open.
## **Programmable Over Voltage Protection (OVP2)**
In addition to the VCC OVP protection, it is possible to connect a Zener diode between VCC and the SD pin to implement programmable VCC OVP monitoring (DZ of Figure 67). The triggering level is (VZ+VOVP) where VOVP is the 2.5−V internal threshold. If this protection trips, the NCL30186A and NCL30186C latch off while the NCL30186B and NCL30186D enter the auto−recovery mode.
**==> picture [355 x 272] intentionally omitted <==**
**----- Start of picture text -----**<br>
Vdd<br>NCL30186B / NCL30186D<br>IOTP(REF) SD PIN OVP (OVP2) DETECTION (autorecovery versions)<br>VCC L o + S Q OFF<br>− Q<br>DZ VOVP TSD(delay) R<br>SD<br>OTP DETECTION 4−s Timer<br>NTC NCL30186A / NCL30186C<br>TOTP(start) (latching off versions)<br>V / VOTP(off) OTP(on)<br>S<br>Q Latch<br>re L e Q<br>Thermal VTF R<br>Foldback<br>grand reset<br>Rclamp<br>Vclamp<br>a<br>Clamp<br>−<br>+<br>**----- End of picture text -----**<br>
**Figure 67. Thermal Foldback and OVP/OTP Circuitry**
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The SD pin is clamped to about 1.35 V ( _Vclamp_ ) through a 1.6−k Q resistor ( _Rclamp_ ). It is then necessary to inject about
**==> picture [118 x 79] intentionally omitted <==**
typically, to trigger the OVP protection. This current helps ensure an accurate detection by using the Zener diode far from its knee region.
## **Programmable Over Temperature Foldback Protection (OTP)**
Connect an NTC between the SD pin and ground to detect an over−temperature condition. In response to a high temperature (detected if VSD drops below VTF(start)), the circuit gradually reduces the LED current down to 50% (> 50% reduction in output power) of its initial value when VSD reaches VTF(stop), in accordance with the characteristic of Figure 68 (Note 9).
At this point, if the temperature continues to rise and the secondary OTP level is reached, (VSD drop below VOTP), the circuit latches off (A and C versions) or enters auto−recovery mode (B and D versions) and cannot resume operation until VSD exceeds VOTP(on) to provide some temperature hysteresis (around 10 C typically). The OTP thresholds nearly correspond to the following resistances of the NTC:
- Thermal foldback starts when RNTC RTF(start) (11.7 k typically)
- Thermal foldback stops when RNTC RTF(stop) (8.0 k typically)
- OTP triggers when RNTC ROTP(off) (5.9 k typically)
- OTP is removed when RNTC ROTP(on) (8.0 k typically) (Note 10)
**Figure 68. Output Current Reduction versus SD Pin Voltage**
At startup, when VCC reaches VCC(on), the OTP comparator is blanked for at least 180 s which allows the u SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. This avoids flickering of the LED light during turn on.
## **Brown−Out Protection**
The NCL30186 prevents operation when the line voltage is too low for proper operation. As sketched in Figure 69, the circuit detects a brown−out situation if the VS pin remains below the VBO(off) threshold (0.9 V typical) for more than the 25−ms blanking time. In this case, the controller stops operating. Operation resumes as soon as the VS pin voltage exceeds VBO(on) (1.0 V typical) and VCC is higher than VCC(on). To ease recovery, the circuit overrides the VCC normal sequence (no need for VCC cycling down below VCC(off)). Instead, its consumption immediately reduces to ICC(start) so that VCC rapidly charges up to VCC(on) and the circuit re−starts operation.
**Figure 69. Brown−out Circuit**
9. The above mentioned initial value is the output current before the system enters the thermal foldback, that is, its maximum level if PWM or analog dimming is not engaged or a lower one based on the dimming value.
- 10.This condition is sufficient for operation recovery of the B and D versions. For the A and C versions which latches off when OTP is triggered, the circuit further needs to be reset by the VCC drop below VCC(reset).
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## **Die Over Temperature (TSD)**
The circuit stops operating if the junction temperature (TJ) exceeds 150 C typically. The controller remains off until TJ goes below nearly 100 C.
## **Pin Connection Faults**
The circuit addresses most pin connection fault cases:
- **CS Pin Short to Ground**
- The circuit senses the CS pin impedance every time it starts−up and after DRV pulses terminated by the 36−s maximum on−time. If the measured impedance does not exceed 120 typically, the circuit stops operating. In practice, it is recommended to place a minimum of 250 in series between the CS pin and the current sense resistor to take into account parasitics.
- **Fault of the GND Connection**
- If the GND pin is properly connected, the supply current drawn from the positive terminal of the _VCC_ capacitor, flows out of the GND pin to return to the negative terminal of the _VCC_ capacitor. If the GND pin is not connected, the circuit ESD diodes offer another return path. The accidental non−connection of the GND pin is monitored by detecting that one of the ESD diode is conducting. Practically, the ESD diode of CS pin is monitored. If such a fault is detected for 200 s, the circuit stops generating DRV pulses.
**More generally, incorrect pin connection situations (open, grounded, shorted to adjacent pin) are covered by AND9204/D.**
## **Fault Management**
## _OFF Mode_
The circuit turns off in the case of an incorrect feeding of the circuit: “UVLO high”. The UVLO signal becomes high when VCC drops below VCC(off) and remains high until VCC exceeds VCC(on).
The circuit also turns off whenever a major faulty condition prevents it from operating:
- Severe OTP (VSD level below VOTP(off))
- VCC OVP
- OVP2 (additional OVP provided by SD pin)
- Output diode short circuit protection: “WOD_SCP high”
- Output / Auxiliary winding Short circuit protection: “Aux_SCP high”
- Die over temperature (TSD)
In this mode, the DRV pulses generation is interrupted.
In the case of a latching−off fault, the circuit stops pulsing until the LED driver is unplugged and VCC drops below VCC(reset). At that moment, the circuit resumes operation.
In the auto−recovery case, the circuit cannot generate DRV pulses for the auto−recovery 4−s delay. When this time has elapsed, the circuit recovers operation as soon as the VCC voltage has exceeded VCC(on). In the B and D versions, all these protections are auto−recovery. The SD pin OTP and OVP, WOD_SCP and AUX_SCP functions are latching off in the A and C versions (see Table 5).
**Table 5. PROTECTION MODES**
|**Table 5. PROTECTION MODES**|**Table 5. PROTECTION MODES**||||
|---|---|---|---|---|
||**AUX_SCP**|**WOD_SCP**|**SD Pin OTP**|**SD Pin OVP**|
|NCL30186A*|Latching off|Latching off|Latching off|Latching off|
|NCL30186B|Auto−recovery|Auto−recovery|Auto−recovery|Auto−recovery|
|NCL30186C*|Latching off|Latching off|Latching off|Latching off|
|NCL30186D|Auto−recovery|Auto−recovery|Auto−recovery|Auto−recovery|
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**NCL30186**
## **ORDERING INFORMATION**
|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package Type**|**Shipping**|
|NCL30186BDR2G|SOIC−10<br>(Pb−Free/Halide Free)|2500 / Tape & Reel|
|NCL30186DDR2G|||
*Please contact local sales representative for availability
**DISCONTINUED** (Note 11) **Device Package Shipping**[†] NCL30186ADR2G* SOIC−10 (Pb−Free/Halide Free) 2500 / Tape & Reel NCL30186CDR2G* ~~———~~ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
11. **DISCONTINUED:** This device is not recommended for new design. Please contact your **onsemi** representative for information. The most current information on this device may be available on www.onsemi.com.
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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS**
**==> picture [484 x 451] intentionally omitted <==**
**----- Start of picture text -----**<br>
SOIC−10 NB<br>CASE 751BQ<br>10<br>ISSUE B<br>1 DATE 26 NOV 2013<br>SCALE 1:1<br>2X<br>0.10 C A-B NOTES:1. DIMENSIONING AND TOLERANCING PER<br>ASME Y14.5M, 1994.<br>D 2. CONTROLLING DIMENSION: MILLIMETERS.<br>D 3. DIMENSION b DOES NOT INCLUDE DAMBAR<br>A PROTRUSION. ALLOWABLE PROTRUSION<br>2X SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’<br>0.10 C A-B F 4. AT MAXIMUM MATERIAL CONDITION.DIMENSIONS D AND E DO NOT INCLUDE<br>10 6 MOLD FLASH, PROTRUSIONS, OR GATE<br>BURRS. MOLD FLASH, PROTRUSIONS, OR<br>GATE BURRS SHALL NOT EXCEED 0.15mm<br>H E PER SIDE. DIMENSIONS D AND E ARE DE-<br>TERMINED AT DATUM F.<br>1<br>5. DIMENSIONS A AND B ARE TO BE DETERM-<br>5<br>L2 INED AT DATUM F.<br>A3<br>L C SEATINGPLANE 6. A1 IS DEFINED AS THE VERTICAL DISTANCEFROM THE SEATING PLANE TO THE LOWEST<br>0.20 C 10X b DETAIL A POINT ON THE PACKAGE BODY.<br>B<br>2X 5 TIPS 0.25 M C A-B D MILLIMETERS<br>TOP VIEW DIMA MIN 1.25 MAX 1.75<br>A1 0.10 0.25<br>10X h A3 0.17 0.25<br>0.10 C 0.10 C X 45 � Db 4.800.31 5.000.51<br>M E 3.80 4.00<br>e 1.00 BSC<br>H 5.80 6.20<br>A h 0.37 REF<br>L 0.40 0.80<br>A1 SIDE VIEWe C SEATINGPLANE DETAIL A END VIEW L2M 0 0.25 BSC � 8 �<br>GENERIC<br>RECOMMENDED<br>MARKING DIAGRAM*<br>SOLDERING FOOTPRINT*<br>10<br>1.00<br>10X 0.58 PITCH XXXXX<br>ALYWX<br>�<br>1<br>6.50 XXXXX = Specific Device Code<br>A = Assembly Location<br>L = Wafer Lot<br>Y = Year<br>W = Work Week<br>1 � = Pb−Free Package<br>10X 1.18<br>DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
DATE 26 NOV 2013<br>**----- End of picture text -----**<br>
- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present.
*For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
**DOCUMENT NUMBER: 98AON52341E DESCRIPTION: SOIC−10 NB**
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Updated at April 15, 2026
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