NCL30082ADMR2G.

## NCL30082 

## Dimmable Quasi-Resonant Primary Side Current-Mode Controller for LED Lighting with Thermal Fold-back 

The NCL30082 is a PWM current mode controller targeting isolated flyback and non−isolated constant current topologies. The controller operates in a quasi−resonant mode to provide high efficiency. Thanks to a novel control method, the device is able to precisely regulate a constant LED current from the primary side. This removes the need for secondary side feedback circuitry, biasing and an optocoupler. 

The device is highly integrated with a minimum number of external components. A robust suite of safety protection is built in to simplify the design. This device supports analog/digital dimming as well as thermal current fold−back. While the NCL30082 has integrated fixed overvoltage protection, the designer has the flexibility to program a lower OVP level. 

## **Features** 

- Quasi−resonant Peak Current−mode Control Operation 

- Primary Side Sensing (no optocoupler needed) 

- Wide VCC Range 

- Source 300 mA / Sink 500 mA Totem Pole Driver with 12 V Gate Clamp 

- Precise LED Constant Current Regulation ±1% Typical 

- Line Feed−forward for Enhanced Regulation Accuracy 

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8 : <i<br>8<br>1 1<br>Micro8 SOIC−8<br>DM SUFFIX D SUFFIX<br>CASE 846A CASE 751<br>**----- End of picture text -----**<br>


## **MARKING DIAGRAMS** 

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8 HAGA<br>AAx<br>AYW<br>1<br>AAx = Specific Device Code<br>x = C, D or H<br>A = Assembly Location<br>Y = Year<br>W = Work Week<br>= Pb−Free Package<br>(Note: Microdot may be in either location)<br>**----- End of picture text -----**<br>


- Low LED Current Ripple 

- 250 mV ±2% Guaranteed Voltage Reference for Current Regulation 

- ~0.9 Power Factor with Valley Fill Input Stage 

- Low Start−up Current (13 A typ.) 

- Analog or Digital Dimming 

- Thermal Fold−back 

- Wide Temperature Range of −40 to +125°C 

- Pb−Free, Halide−Free MSL1 Product 

- Robust Protection Features 

   - ♦ Over Voltage / LED Open Circuit Protection 

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8<br>L30082x<br>ALYW<br>1<br>L30082x = Specific Device Code<br>x = B, B1, B2, B3, D<br>A = Assembly Location<br>L = Wafer Lot<br>Y = Year<br>W = Work Week<br>= Pb−Free Package<br>**----- End of picture text -----**<br>


- ♦ Over Temperature Protection 

- ♦ Secondary Diode Short Protection 

- ♦ Output Short Circuit Protection 

- ♦ Shorted Current Sense Pin Fault Detection 

- ♦ Latched and Auto−recoverable Versions 

- ♦ Brown−out 

- ♦ VCC Under Voltage Lockout 

- ♦ Thermal Shutdown 

## **PIN CONNECTIONS** 

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1<br>|<br>SD a |IT DIM<br>ZCD cor} J VIN<br>CS cor} — — VCC<br>GND om — DRV<br>UL [__][]]<br>(Top View)<br>**----- End of picture text -----**<br>


- These Devices are Pb−Free and Halogen Free/BFR Free 

## **Typical Applications** 

- Integral LED Bulbs 

- LED Power Driver Supplies 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 33 of this data sheet. 

- LED Light Engines 

Publication Order Number: **NCL30082/D** 

**1** 

© Semiconductor Components Industries, LLC, 2015 **January, 2015 − Rev. 5** 

**NCL30082** 

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.<br>.<br>Aux<br>.<br>VDIM<br>1 8<br>2 7<br>3 6<br>4 5<br>**----- End of picture text -----**<br>


**Figure 1. Typical Application Schematic for NCL30082** 

**Table 1. PIN FUNCTION DESCRIPTION** 

|**Pin No**|**Pin Name**|**Function**|**Pin Description**|
|---|---|---|---|
|1|SD|Thermal Fold−back<br>and shutdown|Connecting an NTC to this pin allows reducing the output current down to 50%<br>of its fixed value before stopping the controller. A Zener diode can also be<br>used to pull−up the pin and stop the controller for adjustable OVP protection|
|2|ZCD|Zero Crossing Detection|Connected to the auxiliary winding, this pin detects the core reset event.|
|3|CS|Current sense|This pin monitors the primary peak current|
|4|GND|−|The controller ground|
|5|DRV|Driver output|The current capability of the totem pole gate drive (+0.3/−0.5 A) makes it suit-<br>able to effectively drive a broad range of power MOSFETs.|
|6|VCC|Supplies the controller|This pin is connected to an external auxiliary voltage.|
|7|VIN|Input voltage sensing<br>Brown−Out|This pin observes the HV rail and is used in valley selection. This pin also<br>monitors and protects for low mains conditions.|
|8|DIM|Analog / PWM dimming|This pin is used for analog or PWM dimming control. An analog signal than<br>can be varied between VDIM(EN)and VDIM100can be used to vary the current,<br>or a PWM signal with an amplitude greater than VDIM100.|



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**2** 

**NCL30082** 

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CS_shorted Enable STOP VDD VREF<br>Over Voltage<br>Protection<br>Aux_SCP OFF<br>VCC<br>Fault UVLO<br>Over Temperature Management Latch VCC Management<br>Protection<br>Internal<br>SD Thermal ShutdownThermal Ipkmax VCC_max VCC Over VoltageProtection<br>Foldback VTF WOD_SCP<br>BO_NOK<br>Qdrv VVIN VREF VCC<br>Clamp<br>ZCD Zero Crossing Detection offset_OK Circuit<br>Valley Selection<br>Aux. Winding<br>Short Circuit Prot. S Qdrv DRV<br>Aux_SCP Q<br>VVIN offset_OK<br>VVLY<br>R<br>Line<br>Feedforward VTF STOP VREF<br>CS Leading Constant−Current CS_reset VDIMA DimmingType DIM<br>Edge<br>Control Detection<br>Blanking<br>Ipkmax STOP<br>Enable<br>Enable VDIMA<br>Max. Peak<br>Current Ipkmax VVIN<br>Limit<br>VIN<br>CS Short BO_NOK Brown−Out<br>Protection CS_shorted<br>VVIN<br>Winding and<br>Output diode<br>GND Short Circuit WOD_SCP Note: CS Short Protection is disabled<br>Protection Note: for NCL30082B1<br>**----- End of picture text -----**<br>


**Figure 2. Internal Circuit Architecture** 

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**NCL30082** 

## **Table 2. MAXIMUM RATINGS TABLE** 

|**Symbol**|**Rating**|**Value**|**Unit**|
|---|---|---|---|
|VCC(MAX)<br>ICC(MAX)|Maximum Power Supply voltage, VCC pin, continuous voltage<br>Maximum current for VCC pin|−0.3, +35<br>Internally limited|V<br>mA|
|VDRV(MAX)<br>IDRV(MAX)|Maximum driver pin voltage, DRV pin, continuous voltage<br>Maximum current for DRV pin|−0.3, VDRV(Note 1)<br>−500, +800|V<br>mA|
|VMAX<br>IMAX|Maximum voltage on low power pins (except pins ZCD, DIM, DRV and VCC)<br>Current range for low power pins (except pins ZCD, DRV and VCC)|−0.3, +5.5<br>−2, +5|V<br>mA|
|VZCD(MAX)<br>IZCD(MAX)|Maximum voltage for ZCD pin<br>Maximum current for ZCD pin|−0.3, +10<br>−2, +5|V<br>mA|
|VDIM(MAX)|Maximum voltage for DIM pin|−0.3, +10|V|
|RθJA|Thermal Resistance, Junction−to−Ambient (Note 4)<br>Micro8 version<br>SOIC−8 version|228<br>180|°C/W|
|�JC|Thermal Characterization Parameter, Junction−to−Case Top<br>Micro8 version<br>SOIC−8 version|50<br>45|°C/W|
|TJ(MAX)|Maximum Junction Temperature|150|°C|
||Operating Temperature Range|−40 to +125|°C|
||Storage Temperature Range|−60 to +150|°C|
||ESD Capability, HBM model (Note 2)|4|kV|
||ESD Capability, MM model (Note 2)|200|V|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC unless otherwise noted. 2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC JESD22−A114−F and Machine Model Method 200 V per JEDEC JESD22−A115−A. 

3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 except for VIN pin which passes 60 mA. 4. With a 100 mm[2] , 2 oz copper area based on JEDEC EIA/JESD51-3 board design. 

**Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V; For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) 

|For min/max values TJ= −40°C to +125°C, Max TJ= 150°C, V|CC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Description**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**STARTUP AND SUPPLY CIRCUITS**|||||||
|Supply Voltage<br>Startup Threshold<br>Minimum Operating Voltage<br>Hysteresis VCC(on)– VCC(off)<br>Internal logic reset|VCCincreasing<br>VCCdecreasing<br>VCCdecreasing|VCC(on)<br>VCC(off)<br>VCC(HYS)<br>VCC(reset)|16<br>8.2<br>8<br>3.5|18<br>8.8<br>–<br>4.5|20<br>9.4<br>–<br>5.5|V|
|Over Voltage Protection<br>VCC OVP threshold||VCC(OVP)|26|28|30|V|
|VCC(off)noise filter<br>VCC(reset)noise filter−||tVCC(off)<br>tVCC(reset)|–<br>–|5<br>20|–<br>–|�s|
|Startup current||ICC(start)|–|13|30|�A|
|Startup current in fault mode||ICC(sFault)|–|46|60|�A|
|Supply Current<br>Device Disabled/Fault<br>Device Enabled/No output load on pin 5<br>Device Switching (Fsw= 65 kHz)|VCC> VCC(off)<br>Fsw= 65 kHz<br>CDRV= 470 pF,<br>Fsw= 65 kHz|ICC1<br>ICC2<br>ICC3|0.8<br>–<br>–|1.2<br>2.3<br>2.7|1.4<br>4.0<br>5.0|mA|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Guaranteed by design. 

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**4** 

## **NCL30082** 

**Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V; For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) 

|For min/max values TJ= −40°C to +125°C, Max TJ= 150°C, V|CC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Description**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**CURRENT SENSE**|||||||
|Maximum Internal current limit||VILIM|0.95|1|1.05|V|
|Leading Edge Blanking Duration for VILIM<br>(Tj= −25°C to 125°C) (Not applicable for NCL30082D)||tLEB|250|300|350|ns|
|Leading Edge Blanking Duration for VILIM<br>(Tj= −40°C to 125°C)||tLEB|240|300|350|ns|
|Input Bias Current|DRV high|Ibias|–|0.02|–|�A|
|Propagation delay from current detection to gate off−state||tILIM|–|50|150|ns|
|Threshold for immediate fault protection activation||VCS(stop)|1.35|1.5|1.65|V|
|Leading Edge Blanking Duration for VCS(stop)||tBCS|–|120|–|ns|
|Blanking time for CS to GND short detection VpinVIN= 1 V||tCS(blank1)|6|–|12|�s|
|Blanking time for CS to GND short detection VpinVIN= 1 V<br>NCL30082D||tCS(blank1)D|8|10.7|14|�s|
|Blanking time for CS to GND short detection VpinVIN= 3.3 V||tCS(blank2)|2|–|4|�s|
|Blanking time for CS to GND short detection VpinVIN= 3.3 V<br>NCL30082D||tCS(blank2)D|2.6|3.6|4.6|�s|
|**GATE DRIVE**|||||||
|Drive Resistance<br>DRV Sink<br>DRV Source||RSNK<br>RSRC|–<br>–|13<br>30|–<br>–|�|
|Drive current capability<br>DRV Sink (Note 6)<br>DRV Source (Note 6)||ISNK<br>ISRC|–<br>–|500<br>300|–<br>–|mA|
|Rise Time (10% to 90%)|CDRV= 470 pF|tr|–|40|–|ns|
|Fall Time (90% to 10%)|CDRV= 470 pF|tf|–|30|–|ns|
|DRV Low Voltage|VCC= VCC(off)+0.2 V<br>CDRV= 470 pF,<br>RDRV= 33 k�|VDRV(low)|8|–|–|V|
|DRV High Voltage|VCC= 30 V<br>CDRV= 470 pF,<br>RDRV= 33 k�|VDRV(high)|10|12|14|V|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Guaranteed by design. 

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**5** 

## **NCL30082** 

**Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V; For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) 

|For min/max values TJ= −40°C to +125°C, Max TJ= 150°C, V|CC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Description**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**ZERO VOLTAGE DETECTION CIRCUIT**|||||||
|ZCD threshold voltage|VZCDincreasing|VZCD(THI)|25|45|65|mV|
|ZCD threshold voltage (Note 6)|VZCDdecreasing|VZCD(THD)|5|25|45|mV|
|ZCD hysteresis (Note 6)|VZCDincreasing|VZCD(HYS)|10|–|–|mV|
|Threshold voltage for output short circuit or aux. winding<br>short circuit detection||VZCD(short)|0.8|1|1.2|V|
|Short circuit detection Timer|VZCD< VZCD(short)|tOVLD|70|90|110|ms|
|Auto−recovery timer duration||trecovery|3|4|5|s|
|Input clamp voltage<br>High state<br>Low state|Ipin1= 3.0 mA<br>Ipin1= −2.0 mA|VCH<br>VCL|–<br>−0.9|9.5<br>−0.6|–<br>−0.3|V|
|Propagation Delay from valley detection to DRV high|VZCDdecreasing|tDEM|–|–|150|ns|
|Equivalent time constant for ZCD input (Note 6)||tPAR|–|20|–|ns|
|Blanking delay after on−time||tBLANK|2.25|3|3.75|�s|
|Blanking delay after on−time NCL30082B2 and<br>NCL30082B3||tBLANKB2|1.2|1.6|2.0|�s|
|Timeout after last demag transition||tTIMO|5|6.5|8|�s|
|**CONSTANT CURRENT CONTROL**|||||||
|Reference Voltage at TJ= 25°C||VREF|245|250|255|mV|
|Reference Voltage TJ= −40°C to 125°C||VREF|242.5|250|257.5|mV|
|Reference Voltage NCL30082D (TJ= 25°C)||VREFD|495|500|505|mV|
|Reference Voltage NCL30082D (TJ= 0°C to 85°C)||VREFD|492|500|508|mV|
|Reference Voltage NCL30082D (TJ= −40°C to 125°C)||VREFD|488|500|512|mV|
|Reference Voltage NCL30082B3 (TJ= 25°C)||VREFB3|329|333|337|mV|
|Reference Voltage NCL30082B3 (TJ= 0°C to 85°C)||VREFB3|325|333|341|mV|
|Reference Voltage NCL30082B3 (TJ= −40°C to 125°C)||VREFB3|321|333|345|mV|
|50% reference voltage (for thermal foldback)||VREF50|–|125|–|mV|
|25% reference voltage (for thermal foldback) NCL30082D||VREF25D|−|125|−|mV|
|Current sense lower threshold for detection of the<br>leakage inductance reset time||VCS(low)|30|55|80|mV|
|**LINE FEED−FORWARD**|||||||
|VVINto ICS(offset)conversion ratio||KLFF|15|17|19|�A/V|
|Offset current maximum value|VpinVIN= 4.5 V|Ioffset(MAX)|67.5|76.5|85.5|�A|
|VREFvalue below which the offset current source is turned off|VREFdecreases|VREF(off)|–|37.5|–|mV|
|VREFvalue above which the offset current source is turned on|VREFincreases|VREF(on)|–|50|–|mV|
|**VALLEY SELECTION**|||||||
|Threshold for line range detection Vinincreasing<br>(1stto 2ndvalley transition for VREF> 0.75 V)|VVINincreases|VHL|2.28|2.4|2.52|V|
|Threshold for line range detection Vindecreasing<br>(2ndto 1stvalley transition for VREF> 0.75 V)|VVINdecreases|VLL|2.18|2.3|2.42|V|
|Blanking time for line range detection||tHL(blank)|15|25|35|ms|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Guaranteed by design. 

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**6** 

## **NCL30082** 

**Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V; For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) 

|For min/max values TJ= −40°C to +125°C, Max TJ= 150°C, V|CC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Description**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**VALLEY SELECTION**|||||||
|Valley thresholds<br>1stto 2ndvalley transition at LL and 2ndto 3rdvalley HL<br>2ndto 1stvalley transition at LL and 3rdto 2ndvalley HL<br>2ndto 4thvalley transition at LL and 3rdto 5thvalley HL<br>4thto 2ndvalley transition at LL and 5thto 3rdvalley HL<br>4thto 7thvalley transition at LL and 5thto 8thvalley HL<br>7thto 4thvalley transition at LL and 8thto 5thvalley HL<br>7thto 11thvalley transition at LL and 8thto 12thvalley HL<br>11thto 7thvalley transition at LL and 12thto 8thvalley HL<br>11thto 13thvalley transition at LL and 12thto 15thvalley HL<br>13thto 11thvalley transition at LL and 15thto 12thvalley HL|VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases<br>VREFdecreases<br>VREFincreases|VVLY1−2/2−3<br>VVLY2−1/3−2<br>VVLY2−4/3−5<br>VVLY4−2/5−3<br>VVLY4−7/5−8<br>VVLY7−4/8−5<br>VVLY7−11/8−12<br>VVLY11−7/12−8<br>VVLY11−13/12−15<br>VVLY13−11/15−12|177.5<br>185.0<br>117.5<br>125.0<br>–<br>–<br>–<br>–<br>–<br>–|187.5<br>195.0<br>125.0<br>132.5<br>75.0<br>82.5<br>37.5<br>50.0<br>15.0<br>20.0|197.5<br>205.0<br>132.5<br>140.0<br>–<br>–<br>–<br>–<br>–<br>–|mV|
|**DIMMING SECTION**|||||||
|DIM pin voltage for zero output current (OFF voltage)||VDIM(EN)|0.66|0.7|0.74|V|
|DIM pin voltage for maximum output current||VDIM100|2.25|2.45|2.65|V|
|Dimming range||VDIM(range)|–|1.75|–|V|
|Clamping voltage for DIM pin||VDIM(CLP)|–|7.8|–|V|
|Dimming pin pull−up current source||IDIM(pullup)|–|280|–|nA|
|**THERMAL FOLD−BACK AND OVP**|||||||
|Reference current for direct connection of an NTC (Note 6)||IOTP(REF)|80|85|90||
|SD pin voltage at which thermal fold−back starts||VTF(start)|0.9|1|1.1|V|
|SD pin voltage at which thermal fold−back stops<br>(Iout= 50% Iout(nom))||VTF(stop)|0.64|0.68|0.72|V|
|SD pin voltage at which thermal fold−back stops<br>NCL30082D (Iout= 25% Iout(nom))||VTF(stop)D|0.86|0.90|0.94|V|
|Reference current for direct connection of an NTC||IOTP(REF)|80|85|90|�A|
|Fault detection level for OTP|VSDdecreasing|VOTP(off)|0.47|0.5|0.53|V|
|Fault detection level for OTP NCL30082D||VOTP(off)D|0.81|0.85|0.89|V|
|SD pin level at which controller re−start switching after OTP<br>detection|VSDincreasing|VOTP(on)|0.64|0.68|0.72|V|
|SD pin level at which controller re−start switching after OTP<br>detection NCL30082D||VOTP(on)D|0.86|0.9|0.94|V|
|SD pin Over temperature Protection Hysteresis NCL30082D||VOTP(hys)D|15|50|100|mV|
|VTF(start)over IOTP(REF)ratio (Note 5)|TJ= +25°C to +125°C|RTF(start)|10.8|11.7|12.6|k�|
|VTF(stop)over IOTP(REF)ratio (Note 5)|TJ= +25°C to +125°C|RTF(stop)|7.4|8.0|8.6|k�|
|VOTP(off)over IOTP(REF)ratio (Note 5)|TJ= +25°C to +125°C|ROTP(off)|5.4|5.9|6.4|k�|
|VOTP(on)over IOTP(REF)ratio (Note 5)|TJ= +25°C to +125°C|ROTP(on)|7.4|8.0|8.6|k�|
|VTF(stop)over IOTP(REF)ratio NCL30082D (Note 5)|TJ= +25°C to +125°C|RTF(stop)D|9.9|10.5|11.1|k�|
|VOTP(off)over IOTP(REF)ratio NCL30082D (Note 5)|TJ= +25°C to +125°C|ROTP(off)D|9.4|10.0|10.6|k�|
|VOTP(on)over IOTP(REF)ratio NCL30082D (Note 5)|TJ= +25°C to +125°C|ROTP(on)D|9.9|10.5|11.1|k�|



5. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation. 

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Guaranteed by design. 

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**7** 

## **NCL30082** 

**Table 3. ELECTRICAL CHARACTERISTICS** (Unless otherwise noted: For typical values TJ = 25 ° C, VCC = 12 V; For min/max values TJ = −40 ° C to +125 ° C, Max TJ = 150 ° C, VCC = 12 V) 

|For min/max values TJ= −40°C to +125°C, Max TJ= 150°C, V|CC= 12 V)||||||
|---|---|---|---|---|---|---|
|**Description**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**THERMAL FOLD−BACK AND OVP**|||||||
|Timer duration after which the controller is allowed to start<br>pulsing||tOTP(start)|180|–|300|�s|
|Clamped voltage (SD pin left open)|SD pin open|VSD(clamp)|1.13|1.35|1.57|V|
|Clamp series resistor||RSD(clamp)|–|1.6|–|k�|
|SD pin detection level for OVP|VSDincreasing|VOVP|2.35|2.5|2.65|V|
|Delay before OVP or OTP confirmation (OVP and OTP)||TSD(delay)|15|30|45|�s|
|**THERMAL SHUTDOWN**|||||||
|Thermal Shutdown (Note 6)|Device switching<br>(FSWaround 65 kHz)|TSHDN|130|150|170|°C|
|Thermal Shutdown Hysteresis (Note 6)||TSHDN(HYS)|–|50|–|°C|
|**BROWN−OUT**|||||||
|Brown−Out ON level (IC start pulsing)|VSDincreasing|VBO(on)|0.90|1|1.10|V|
|Brown−Out OFF level (IC shuts down)|VSDdecreasing|VBO(off)|0.85|0.9|0.95|V|
|BO comparators delay||tBO(delay)|–|30|–|�s|
|Brown−Out blanking time||tBO(blank)|35|50|65|ms|
|Brown−Out blanking time NCL30082D||tBO(blank)D|10.5|15|19.5|ms|
|Brown−out pin bias current||IBO(bias)|−250|–|250|nA|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Guaranteed by design. 

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**8** 

**NCL30082** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
18.20<br>18.15<br>18.10<br>18.05<br>18.00<br>17.95<br>17.90<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>CC(on)<br>V<br>**----- End of picture text -----**<br>


**Figure 3. VCC(on) vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
27.80<br>27.75<br>27.70<br>27.65<br>27.60<br>27.55<br>27.50<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>CC(OVP)<br>V<br>**----- End of picture text -----**<br>


**Figure 5. VCC(OVP) vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
8.90<br>8.85<br>8.80<br>8.75<br>8.70<br>8.65<br>8.60<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 4. VCC(off) vs. Junction Temperature<br>18<br>17<br>16<br>15<br>14<br>13<br>12<br>11<br>10<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>CC(off)<br>V<br>A)<br>�<br> (<br>ICC(start)<br>**----- End of picture text -----**<br>


**Figure 6. ICC(start) vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
52<br>50<br>48<br>46<br>44<br>42<br>40<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 7. ICC(sFault) vs. Junction Temperature<br>A)<br>�<br> (<br>ICC(sFault)<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
1.30<br>1.28<br>1.26<br>1.24<br>1.22<br>1.20<br>1.18<br>1.16<br>1.14<br>1.12<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 8. ICC1 vs. Junction Temperature<br> (mA)<br>ICC1<br>**----- End of picture text -----**<br>


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**9** 

**NCL30082** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
2.40 2.85<br>2.80<br>2.35<br>2.75<br>2.30<br>2.70<br>2.25 2.65<br>2.60<br>2.20<br>2.55<br>2.15<br>2.50<br>2.10 2.45<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br> (mA)  (mA)<br>ICC2 ICC3<br>**----- End of picture text -----**<br>


**Figure 9. ICC2 vs. Junction Temperature** 

**Figure 10. ICC3 vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
1.000 1.495<br>0.995 1.490<br>0.990 1.485<br>0.985 1.480<br>0.980 1.475<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br> (V)<br>ILIM<br>V CS(stop)<br>V<br>**----- End of picture text -----**<br>


**Figure 11. VILIM vs. Junction Temperature** 

**Figure 12. VCS(stop) vs. Junction Temperature** 

**==> picture [488 x 199] intentionally omitted <==**

**----- Start of picture text -----**<br>
305 1.010<br>303<br>1.005<br>301<br>299<br>1.000<br>297<br>295 0.995<br>293<br>0.990<br>291<br>289<br>0.985<br>287<br>285 0.980<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 13. tLEB vs. Junction Temperature Figure 14. VZCD(short) vs. Junction<br>Temperature<br> (V)<br> (ns)<br>tLEB<br>ZCD(short)<br>V<br>**----- End of picture text -----**<br>


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**10** 

**NCL30082** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [238 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.20<br>3.15<br>3.10<br>3.05<br>3.00<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>s)<br>�<br> (<br>tBLANK<br>**----- End of picture text -----**<br>


**Figure 15. tBLANK vs. Junction Temperature** 

**==> picture [237 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
7.1<br>7.0<br>6.9<br>6.8<br>6.7<br>6.6<br>6.5<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>s)<br>�<br> (<br>tTIMO<br>**----- End of picture text -----**<br>


**Figure 16. tTIMO vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
255<br>254<br>253<br>252<br>251<br>250<br>249<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (mV)<br>REF<br>V<br>**----- End of picture text -----**<br>


**Figure 17. VREF vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
16.60<br>16.55<br>16.50<br>16.45<br>16.40<br>16.35<br>16.30<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 19. KLFF vs. Junction Temperature<br>A/V)<br>�<br> (<br>LFF<br>K<br>**----- End of picture text -----**<br>


**==> picture [237 x 400] intentionally omitted <==**

**----- Start of picture text -----**<br>
55.0<br>54.5<br>54.0<br>53.5<br>53.0<br>52.5<br>52.0<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 18. VCS(low) vs. Junction Temperature<br>37.6<br>37.5<br>37.4<br>37.3<br>37.2<br>37.1<br>37.0<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 20. VREF(off) vs. Junction Temperature<br> (mV)<br>CS(low)<br>V<br> (mV)<br>REF(off)<br>V<br>**----- End of picture text -----**<br>


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**11** 

**NCL30082** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [238 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
49.0<br>48.5<br>48.0<br>47.5<br>47.0<br>46.5<br>46.0<br>45.5<br>45.0<br>44.5<br>44.0<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (mV)<br>REF(on)<br>V<br>**----- End of picture text -----**<br>


**Figure 21. VREF(on) vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
2.400<br>2.395<br>2.390<br>2.385<br>2.380<br>2.375<br>2.370<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>HL<br>V<br>**----- End of picture text -----**<br>


**Figure 22. VHL vs. Junction Temperature** 

**==> picture [488 x 409] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.300 28.0<br>2.295<br>27.5<br>2.290<br>2.285 27.0<br>2.280<br>26.5<br>2.275<br>2.270 26.0<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 23. VLL vs. Junction Temperature Figure 24. tHL(BLANK) vs. Junction Temperature<br>187.0 198<br>197<br>186.5<br>196<br>186.0<br>195<br>185.5<br>194<br>185.0<br>193<br>184.5<br>192<br>184.0 191<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 25. VVLY1−2/2−3 vs. Junction Figure 26. VVLY2−1/3−2 vs. Junction<br>Temperature Temperature<br> (ms)<br> (V)<br>LL<br>V<br>tHL(BLANK)<br> (mV)  (mV)<br>VLY1−2/2−3 VLY2−1/3−2<br>V V<br>**----- End of picture text -----**<br>


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**12** 

**NCL30082** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [488 x 618] intentionally omitted <==**

**----- Start of picture text -----**<br>
125.0 136<br>124.5 135<br>124.0 134<br>123.5 133<br>123.0 132<br>122.5 131<br>122.0 130<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 27. VVLY2−4/3−5 vs. Junction Figure 28. VVLY4−2/5−3 vs. Junction<br>Temperature Temperature<br>76.0 87<br>86<br>75.5<br>85<br>75.0<br>84<br>74.5<br>83<br>74.0<br>82<br>73.5<br>81<br>73.0 80<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 29. VVLY4−7/5−8 vs. Junction Figure 30. VVLY7−4/8−5 vs. Junction<br>Temperature Temperature<br>37.7 50<br>37.6 49<br>37.5 48<br>37.4 47<br>37.3 46<br>37.2 45<br>37.1 44<br>37.0 43<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 31. VVLY7−11/8−12 vs. Junction Figure 32. VVLY11−7/12−8 vs. Junction<br>Temperature Temperature<br> (mV)  (mV)<br>VLY2−4/3−5 VLY4−2/5−3<br>V V<br> (mV)  (mV)<br>VLY4−7/5−8 VLY7−4/8−5<br>V V<br> (mV)  (mV)<br>VLY7−11/8−12 VLY11−7/12−8<br>V V<br>**----- End of picture text -----**<br>


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**13** 

**NCL30082** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [240 x 382] intentionally omitted <==**

**----- Start of picture text -----**<br>
15.10<br>15.05<br>15.00<br>14.95<br>14.90<br>14.85<br>14.80<br>14.75<br>14.70<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 33. VVLY11−13/12−15 vs. Junction<br>Temperature<br>0.710<br>0.705<br>0.700<br>0.695<br>0.690<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (mV)<br>VLY11−13/12−15<br>V<br> (V)<br>DIM(EN)<br>V<br>**----- End of picture text -----**<br>


**Figure 35. VDIM(EN) vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
88.0<br>87.5<br>87.0<br>86.5<br>86.0<br>85.5<br>85.0<br>84.5<br>84.0<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 37. tOVLD vs. Junction Temperature<br> (ms)<br>tOVLD<br>**----- End of picture text -----**<br>


**==> picture [237 x 591] intentionally omitted <==**

**----- Start of picture text -----**<br>
21.0<br>20.5<br>20.0<br>19.5<br>19.0<br>18.5<br>18.0<br>17.5<br>17.0<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 34. VVLY13−11/15−12 vs. Junction<br>Temperature<br>2.46<br>2.45<br>2.44<br>2.43<br>2.42<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 36. VDIM(100) vs. Junction Temperature<br>4.55<br>4.50<br>4.45<br>4.40<br>4.35<br>4.30<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (mV)<br>VLY13−11/15−12<br>V<br> (V)<br>DIM(100)<br>V<br> (s)<br>trecovery<br>**----- End of picture text -----**<br>


**Figure 38. trecovery vs. Junction Temperature** 

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**14** 

**NCL30082** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [239 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.500<br>2.495<br>2.490<br>2.485<br>2.480<br>2.475<br>2.470<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>OVP<br>V<br>**----- End of picture text -----**<br>


**Figure 39. VOVP vs. Junction Temperature** 

**==> picture [237 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
86.5<br>86.0<br>85.5<br>85.0<br>84.5<br>84.0<br>83.5<br>83.0<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>A)<br>�<br> (<br>IOTP(ref)<br>**----- End of picture text -----**<br>


**Figure 40. IOTP(ref) vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
0.690<br>0.688<br>0.686<br>0.684<br>0.682<br>0.680<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE (J, JUNCTION TEMPERATURE (, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>TF(stop)<br>, V<br>OTP(on)<br>V<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
0.690<br>0.997<br>0.688<br>0.995<br>0.686 0.993<br>0.991<br>0.684<br>0.989<br>0.682<br>0.987<br>0.680 0.985<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE (J, JUNCTION TEMPERATURE (, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 41. VOTP(on), VTF(stop) vs. Junction Figure 42. VTF(start) vs. Junction Temperature<br>Temperature<br>0.994 0.906<br>0.992<br>0.904<br>0.990<br>0.902<br>0.988<br>0.900<br>0.986<br>0.898<br>0.984<br>0.982 0.896<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br> (V)<br>TF(stop)<br>, V<br>TF(start)<br>V<br>OTP(on)<br>V<br> (V)  (V)<br>BO(on) BO(off)<br>V V<br>**----- End of picture text -----**<br>


**Figure 43. VBO(on) vs. Junction Temperature** 

**Figure 44. VBO(off) vs. Junction Temperature** 

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**15** 

**NCL30082** 

## **TYPICAL CHARACTERISTICS** 

**==> picture [239 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
504<br>503<br>502<br>501<br>500<br>499<br>498<br>497<br>496<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (mV)<br>REFD<br>V<br>**----- End of picture text -----**<br>


**Figure 45. VREFD vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
130<br>129<br>128<br>127<br>126<br>125<br>124<br>123<br>122<br>121<br>120<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (mV)<br>REF25D<br>V<br>**----- End of picture text -----**<br>


**Figure 46. VREF25D vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
0.850<br>0.848<br>0.846<br>0.844<br>0.842<br>0.840<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br> (V)<br>OTP(off)D<br>V<br>**----- End of picture text -----**<br>


**Figure 47. VOTP(off)D vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
48.2<br>48.0<br>47.8<br>47.6<br>47.4<br>47.2<br>47.0<br>46.8<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 49. VOTP(HYS)D vs. Junction<br>Temperature<br> (mV)<br>OTP(HYS)D<br>V<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
0.900<br>0.898<br>0.896<br>0.894<br>0.892<br>0.890<br>0.888<br>0.886<br>−40 −20 0 20 40 60 80 100 120<br> (V)<br>TF(stop)D<br>, V<br>OTP(on)D<br>V<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TJ, JUNCTION TEMPERATURE ( ° C)<br>**----- End of picture text -----**<br>


**Figure 48. VOTP(on)D, VTF(stop)D vs. Junction Temperature** 

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**----- Start of picture text -----**<br>
15.5<br>15.4<br>15.3<br>15.2<br>15.1<br>15.0<br>14.9<br>14.8<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 50. tBO(BLANK)D vs. Junction<br>Temperature<br> (ms)<br>tBO(BLANK)D<br>**----- End of picture text -----**<br>


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**16** 

**NCL30082** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
56.0<br>55.5<br>55.0<br>54.5<br>54.0<br>53.5<br>53.0<br>52.5<br>−40 −20 0 20 40 60 80 100 120<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 51. tBO(BLANK) vs. Junction Temperature<br> (ms)<br>tBO(BLANK)<br>**----- End of picture text -----**<br>


## **APPLICATION INFORMATION** 

The **NCL30082** implements a current−mode architecture operating in quasi−resonant mode. Thanks to proprietary circuitry, the controller is able to accurately regulate the secondary side current of the flyback converter without using any opto−coupler or measuring directly the secondary side current. 

- **Quasi−Resonance Current−Mode Operation:** implementing quasi−resonance operation in peak current−mode control, the NCL30082 optimizes the efficiency by switching in the valley of the MOSFET drain−source voltage. Thanks to a smart control algorithm, the controller locks−out in a selected valley and remains locked until the input voltage or the output current set point significantly changes. 

- **Primary Side Constant Current Control:** thanks to a proprietary circuit, the controller is able to compensate for the leakage inductance of the transformer and allow accurate control of the secondary side current. 

- **Line Feed−forward:** compensation for possible variation of the output current caused by system slew rate variation. 

- **Open LED protection:** if the voltage on the VCC pin exceeds an internal limit, the controller shuts down and waits 4 seconds before restarting switching. 

- **Thermal Fold−back / Over Temperature / Over Voltage Protection:** by combining a dual threshold on the SD pin, the controller allows the direct connection of an NTC to ground plus a Zener diode to a monitored voltage. The temperature is monitored and the output current is linearly reduced in the event that the 

temperature exceeds a prescribed level. If the temperature continues to increase, the current will be further reduced until the controller is stopped. The control will automatically restart if the temperature is reduced. This pin can implement a programmable OVP shutdown that can also auto−restart the device. 

- **Brown−Out:** the controller includes a brown−out circuit which safely stops the controller in case the input voltage is too low. The device will automatically restart if the line recovers. 

- **Cycle−by−cycle peak current limit:** when the current sense voltage exceeds the internal threshold VILIM, the MOSFET is turned off for the rest of the switching cycle. 

- **Winding Short−Circuit Protection:** an additional comparator with a short LEB filter (tBCS) senses the CS signal and stops the controller if VCS reaches 1.5 x VILIM. For noise immunity reasons, this comparator is enabled only during the main LEB duration tLEB. 

- **Output Short−circuit protection:** If a very low voltage is applied on ZCD pin for 90 ms (nominal), the controllers assume that the output or the ZCD pin is shorted to ground and enters shutdown. The auto−restart version (B suffix) waits 4 seconds, then the controller restarts switching. In the latched version (A suffix), the controller is latched as long as VCC stays above the V threshold. CC(reset) 

- **Linear or PWM dimming:** the DIM pin allows implementing both analog and PWM dimming. 

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**17** 

**NCL30082** 

## **Constant Current Control** 

Figure 53 portrays the primary and secondary current of a flyback converter in discontinuous conduction mode (DCM). Figure 52 shows the basic circuit of a flyback converter. 

**==> picture [343 x 257] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vbulk Transformer<br>Lleak<br>N<br>Cclp Rclp sp Vout<br>.<br>L<br>p<br>.<br>Clamping<br>network<br>DRV<br>Clump<br>Rsense<br>**----- End of picture text -----**<br>


**Figure 52. Basic Flyback Converter Schematic** 

During the on−time of the MOSFET, the bulk voltage Vbulk is applied to the magnetizing and leakage inductors Lp and Lleak and the current ramps up. 

When the MOSFET is turned−off, the inductor current first charges Clump . The output diode is off until the voltage across L reverses and reaches: p 

**==> picture [146 x 17] intentionally omitted <==**

The output diode current increase is limited by the leakage inductor. As a consequence, the secondary peak current is reduced: 

**==> picture [146 x 25] intentionally omitted <==**

The diode current reaches its peak when the leakage inductor is reset. Thus, in order to accurately regulate the output current, we need to take into account the leakage inductor current. This is accomplished by sensing the clamping network current. Practically, a node of the clamp capacitor is connected to Rsense instead of the bulk voltage Vbulk . Then, by reading the voltage on the CS pin, we have an image of the primary current (red curve in Figure 53). 

When the diode conducts, the secondary current decreases linearly from ID,pk to zero. When the diode current has turned off, the drain voltage begins to oscillate because of the resonating network formed by the inductors ( Lp+Lleak ) and the lump capacitor. This voltage is reflected on the auxiliary winding wired in flyback mode. Thus, by looking at the auxiliary winding voltage, we can detect the end of the conduction time of secondary diode. The constant current control block picks up the leakage inductor current, the end of conduction of the output rectifier and controls the drain current to maintain the output current constant. 

We have: 

**==> picture [150 x 24] intentionally omitted <==**

The output current value is set by choosing the sense resistor: 

**==> picture [150 x 24] intentionally omitted <==**

From Equation 3, the first key point is that the output current is independent of the inductor value. Moreover, the leakage inductance does not influence the output current value as the reset time is taken into account by the controller. 

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**18** 

**NCL30082** 

**==> picture [302 x 333] intentionally omitted <==**

**----- Start of picture text -----**<br>
IL,pk<br>N I<br>sp D,pk<br>Ipri(t)<br>Isec(t)<br>time<br>t1 t2<br>ton tdemag<br>Vaux(t)<br>time<br>**----- End of picture text -----**<br>


**Figure 53. Flyback Currents and Auxiliary Winding Voltage in DCM** 

## **Internal Soft−Start** 

At startup or after recovering from a fault, there is a small internal soft−start of 40 �s. 

In addition, during startup, as the output voltage is zero volts, the demagnetization time is long and the constant 

current control block will slowly increase the peak current towards its nominal value as the output voltage grows. Figure 54 shows a soft−start simulation example for a 9 W LED power supply. 

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**19** 

**NCL30082** 

**==> picture [488 x 345] intentionally omitted <==**

**----- Start of picture text -----**<br>
16.0<br>12.0 1 Vout<br>8.00<br>4.00<br>0<br>800m<br>600m<br>2 Iout<br>400m<br>200m<br>0<br>800m<br>600m<br>4 VControl<br>400m<br>200m<br>0 3 VCS<br>604u 1.47m 2.34m 3.21m 4.07m<br>time in seconds<br>(V)<br>(A)<br>(V)<br>**----- End of picture text -----**<br>


**Figure 54. Startup Simulation Showing the Natural Soft−start** 

## **Cycle−by−Cycle Current Limit** 

When the current sense voltage exceeds the internal threshold VILIM, the MOSFET is turned off for the rest of the switching cycle (Figure 55). 

## **Winding and Output Diode Short−Circuit Protection** 

In parallel with the cycle−by−cycle sensing of the CS pin, another comparator with a reduced LEB (tBCS) and a higher threshold (1.5 V typical) is able to sense winding short−circuit and immediately stops the DRV pulses. The controller goes into auto−recovery mode in version B, B1, B2, B3 and D. 

In version A, the controller is latched. In latch mode, the DRV pulses stop and VCC ramps up and down. The circuit un−latches when VCC pin voltage drops below VCC(reset) threshold. 

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**20** 

**NCL30082** 

**==> picture [479 x 259] intentionally omitted <==**

**----- Start of picture text -----**<br>
S<br>Q DRV Vdd aux<br>Q<br>latch<br>VCC<br>CS R Vcc<br>LEB1 + PWMreset management<br>Rsense Vcontrol −<br>UVLO VCCstop<br>+ Ipkmax 8_HICC grand<br>reset<br>−<br>VILIMIT<br>OVP STOP<br>OVP<br>LEB2 + WOD_SCP<br>VCS(stop) − S Q OFF WOD_SCP S Qlatch<br>Q<br>Q<br>R<br>R<br>8_HICC grand<br>reset<br>from Fault Management Block<br>**----- End of picture text -----**<br>


**Figure 55. Winding Short Circuit Protection, Max. Peak Current Limit Circuits** 

## **Thermal Fold−back and Over Voltage / Over Temperature Protection** 

The thermal fold−back circuit reduces the current in the LED string when the ambient temperature exceeds a set point. The current is gradually reduced to 50% of its nominal value if the temperature continues to rise. (Figure 56). The thermal foldback starting temperature depends of the Negative Coefficient Temperature (NTC) resistor chosen by the power supply designer. 

Indeed, the SD pin allows the direct connection of an NTC to sense the ambient temperature. When the SD pin voltage VSD drops below VTF(start), the internal reference for the 

constant current control VREF is decreased proportionally to VSD. When VSD reaches VTF(stop), VREF is clamped to VREF50, corresponding to 50% of the nominal output current (versions A, B, B1, B2, B3). For the NCL30082D, the output current is decreased to 25% of the nominal output current. 

If VSD drops below VOTP, the controller enters into the auto−recovery fault mode for version B, B1, B2, B3 and D meaning that the 4−s timer is activated. The controller will re−start switching after the 4−s timer has elapsed and when VSD > VOTP(on) to provide some temperature hysteresis. 

For version A, this protection is latched: reset occurs when VCC < VCC(reset). 

**==> picture [230 x 156] intentionally omitted <==**

**----- Start of picture text -----**<br>
Iout Temperature increases<br>Temperature decreases<br>Iout(nom)<br>50% Iout(nom)<br>VSD<br>VOTP(off) VTF(stop) VTF(start)<br>VOTP(on)<br>Shutdown<br>**----- End of picture text -----**<br>


**Figure 56. Output Current Reduction vs. SD Pin Voltage for NCL30082 Versions A, B, B1, B2, B3** 

**==> picture [211 x 164] intentionally omitted <==**

**----- Start of picture text -----**<br>
Iout<br>Temperature increases<br>Temperature decreases<br>Iout(nom)<br>25% Iout(nom)<br>VSD<br>VOTP(off) VTF(start)<br>VTF(stop)<br>VOTP(on)<br>Shutdown<br>**----- End of picture text -----**<br>


**Figure 57. Output Current Reduction vs. SD Pin Voltage for NCL30082D** 

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**21** 

**NCL30082** 

At startup, when VCC reaches VCC(on), the controller is not allowed to start pulsing for at least 180 �s in order to allow the SD pin voltage to reach its nominal value if a 

filtering capacitor is connected to the SD pin. This is to avoid flickering of the LED light in case of over temperature. 

**==> picture [478 x 246] intentionally omitted <==**

**----- Start of picture text -----**<br>
VOVP<br>VCC<br>Vdd<br>noise delay<br>OVP<br>Dz<br>IOTP(REF)<br>S<br>Q OFF<br>SD<br>Q<br>OTP_Timer end<br>Rclamp<br>noise delay R<br>OTP<br>NTC 4−s Timer<br>Vclamp<br>(OTP latched for version A)<br>0.5 V if OTP low<br>VOTP 0.7 V if OTP high<br>S<br>Q Latch<br>Q<br>VTF<br>R<br>VCCreset<br>Clamp<br>−<br>+<br>−<br>+<br>**----- End of picture text -----**<br>


**Figure 58. Thermal Fold−back and OVP/OTP Circuitry** 

In the case of excess voltage, the Zener diode starts to conduct and inject current into the internal clamp resistor Rclamp thus causing the pin SD voltage to increase. When 

this voltage reaches the OVP threshold (2.5 V typ.), the controller shuts−down and waits for at least 4 seconds before restarting switching. 

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**22** 

**NCL30082** 

**==> picture [465 x 334] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCC<br>VCC(on)<br>VCC(off)<br>VCC > VCC(on):<br>DRV pulses restart<br>VCC(reset)<br>VDRV<br>4−s Timer<br>VSD > VOVP:<br>VSD controller stops 4−s timer has elapsed:<br>switching waiting for VCC > VCC(on)<br>VOVP to restart DRV pulses<br>VSD(clamp)<br>Vout<br>**----- End of picture text -----**<br>


**Figure 59. OVP with SD Pin Chronograms** 

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**23** 

**NCL30082** 

**==> picture [484 x 315] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCC<br>VCC(on)<br>VCC(off)<br>VCC(reset)<br>VDRV<br>VSD > VTF(stop) and<br>4−s Timer<br>VCC > VCC(on):<br>DRV pulses restart<br>VSD < VOTP(off): 4−s timer has elapsed<br>VSD controller stops but VSD < VTF(stop)<br>switching ≥  no restart<br>VTF(start)<br>VTF(stop)<br>VOTP(off)<br>Iout<br>**----- End of picture text -----**<br>


**Figure 60. Thermal Fold−back / OTP Chronograms** 

## **PWM or Linear Dimming Detection** 

The pin DIM allows implementing either linear dimming or PWM dimming of the LED light. 

If the power supply designer apply an analog signal varying from VDIM(EN) to VDIM100 to the DIM pin, the output current will increase or decrease proportionally to the voltage applied. For VDIM = VDIM100, the power supply delivers the maximum output current. 

If a voltage lower than VDIM(EN) is applied to the DIM pin, the DRV pulses are disabled. Thus, for PWM dimming, a PWM signal with a low state value < VDIM(EN) and a high state value > VDIM100 should be applied. 

The DIM pin is pulled up internally by a small current source. Thus, if the pin is left open, the controller is able to start. 

**==> picture [339 x 81] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDIM Analog dimming PWM dimming<br>VDIM100 100% Iout<br>VDIM(EN) 0% Iout<br>**----- End of picture text -----**<br>


**Figure 61. Pin DIM Chronograms** 

## Note: 

- If a PWM voltage with a high state value < VDIM100 is applied to the DIM pin, the product will still be in PWM dimming mode, but the reference voltage will be decreased according to VDIM. This allows increased dynamic range on the dimming control pin. 

- **Thermal Foldback and dimming:** if the IC is in a dimming state and the thermal foldback (TF) is activated, the output current is further reduced to a value equal to Dimming*TF. 

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**24** 

**NCL30082** 

## **VCC Over Voltage Protection (Open LED Protection)** 

If no output load is connected to the LED power supply, the controller must be able to safely limit the output voltage excursion. 

In the NCL30082, when the VCC voltage reaches the VCC(OVP) threshold, the controller stops the DRV pulses and the 4−s timer starts counting. The IC re−start pulsing after the 4−s timer has elapsed and when VCC ≥ VCC(on). 

**==> picture [479 x 442] intentionally omitted <==**

**----- Start of picture text -----**<br>
40.0<br>VCC(OVP)<br>30.0<br>1 VCC<br>V CC(on)<br>20.0<br>10.0<br>VCC(off)<br>0<br>40.0<br>30.0 2 Vout<br>20.0<br>10.0<br>0<br>800m<br>600m<br>400m<br>200m<br>0 3 Iout<br>8.00<br>6.00<br>4 OVP<br>4.00<br>2.00<br>0<br>1.38 3.96 6.54 9.11 11.7<br>time in seconds<br>(V)<br>(V)<br>(A)<br>(V)<br>**----- End of picture text -----**<br>


**Figure 62. Open LED Protection Chronograms** 

## **Valley Lockout** 

Quasi−square wave resonant systems have a wide switching frequency excursion. The switching frequency increases when the output load decreases or when the input voltage increases. The switching frequency of such systems must be limited. 

The NCL30082 changes the valley as the input voltage increases and as the output current set−point is varied (dimming and thermal fold−back). This limits the switching frequency excursion. Once a valley is selected, the controller stays locked in the valley until the input voltage 

or the output current set−point varies significantly. This avoids valley jumping and the inherent noise caused by this phenomenon. 

The input voltage is sensed by the VIN pin (line range detection in Figure 63). The internal logic selects the operating valley according to VIN pin voltage, SD pin voltage and DIM pin voltage. 

By default, when the output current is not dimmed, the controller operates in the first valley at low line and in the second valley at high line. 

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**NCL30082** 

**==> picture [411 x 115] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vbulk<br>VIN<br>+ LLine<br>HLine<br>25−ms blanking time<br>−<br>2.4 V if LLine low<br>2.3 V if LLine high<br>**----- End of picture text -----**<br>


**Figure 63. Line Range Detector** 

**Table 4. VALLEY SELECTION** 

|**Table 4. VALLEY SELECTION**|||||
|---|---|---|---|---|
|Ioutvalue at which the<br>controller changes valley<br>(Ioutdecreasing)|**VIN pin voltage for valley change**<br>VVINdecreases<br>0<br>−LL−<br>2.3 V<br>−HL−<br>5 V|||Ioutvalue at which the<br>controller changes valley<br>(Ioutincreasing)|
|Ioutdecreases<br>100%<br>75%<br>50%<br>30%<br>15%<br>6%<br>0%|1st||2nd|100%<br>Ioutincreases<br>78%<br>53%<br>33%<br>20%<br>8%<br>0%|
||2nd||3rd||
||4th||5th||
||7th||8th||
||11th||12th||
||13th||15th||
||0<br>−LL−<br>2.4 V<br>−HL−<br>5 V<br>VVINincreases<br>**VIN pin voltage for valley change**||||



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**26** 

**NCL30082** 

## **Zero Crossing Detection Block** 

The ZCD pin allows detecting when the drain−source voltage of the power MOSFET reaches a valley. 

A valley is detected when the voltage on pin 1 crosses below the V internal threshold. ZCD(THD) 

At startup or in case of extremely damped free oscillations, the ZCD comparator may not be able to detect 

the valleys. To avoid such a situation, the NCL30082 features a Time−Out circuit that generates pulses if the voltage on ZCD pin stays below the VZCD(THD) threshold for 6.5 �s. 

The time−out also acts as a substitute clock for the valley detection and simulates a missing valley in case of too damped free oscillations. 

**==> picture [463 x 297] intentionally omitted <==**

**----- Start of picture text -----**<br>
VZCD<br>34<br>VZCD(THD)<br>The 3rd valley<br>is validated<br>high 14<br>2nd, 3rd<br>low 12<br>The 2nd valley is detected The 3rd valley is not detected<br>By the ZCD comparator by the ZCD comp<br>high<br>low 15 ZCD comp<br>high<br>low 16 TimeOut<br>Time−out circuit adds a pulse to<br>account for the missing 3rd valley<br>high<br>low 17 Clk<br>**----- End of picture text -----**<br>


**Figure 64. Time−out Chronograms** 

Normally with this type of time−out function, in the event the ZCD pin or the auxiliary winding is shorted, the controller could continue switching leading to improper regulation of the LED current. Moreover during an output short circuit, the controller will strive to maintain constant current operation. 

To avoid these scenarios, a protection circuit consisting of a comparator and secondary timer starts counting when the ZCD voltage is below the VZCD(short) threshold. If this timer reaches 90 ms, the controller detects a fault and shutdown. The auto−restart version (B, B1, B2, D suffix) waits 4 seconds, then the controller restarts switching. In the latched version (A suffix), the controller is latched as long as VCC stays above the VCC(reset) threshold. 

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**NCL30082** 

**==> picture [475 x 245] intentionally omitted <==**

**----- Start of picture text -----**<br>
Tblank Time−Out<br>ZCD<br>+ Clock<br>. VZCD(TH)<br>−<br>Tblank<br>+<br>VZCD(short)<br>−<br>90−ms<br>Timer<br>Enable_b S<br>Q Aux_SCP<br>Q<br>R<br>4−s Timer<br>**----- End of picture text -----**<br>


**Figure 65. ZCD Block Schematic** 

## **Line Feed−Forward** 

Because of the propagation delays, the MOSFET is not turned−off immediately when the current set−point is reached. As a result, the primary peak current is higher than expected and the output current increases. To compensate the peak current increase brought by the propagation delay, a positive voltage proportional to the line voltage is added on the current sense signal. The amount of offset voltage can be adjusted using the RCS resistor as shown in Figure 66. 

VCS(offset) � KLFFVpinVINRCS (eq. 5) 

The offset voltage is applied only during the MOSFET on−time. 

This offset voltage is removed at light load during dimming when the output current drops below 15% of the programmed output current. 

**==> picture [30 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
Bulk rail<br>**----- End of picture text -----**<br>


**==> picture [328 x 122] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>VIN<br>ICS(offset) CS RCS<br>Rsense<br>Q_drv<br>Offset_OK<br>**----- End of picture text -----**<br>


**Figure 66. Line Feed−Forward Schematic** 

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**28** 

**NCL30082** 

## **Brown−out** 

In order to protect the supply against a very low input voltage, the NCL30082 features a brown−out circuit with a fixed ON/OFF threshold. The controller is allowed to start if a voltage higher than 1 V is applied to the VIN pin and shuts−down if the VIN pin voltage decreases and stays 

below 0.9 V for 50 ms nominal. For the NCL30082D, the blanking time is reduced to 15 ms. Exiting a brown−out condition overrides the hiccup on VCC (VCC does not wait to reach VCC(off)) and the IC immediately goes into startup mode (ICC = ICC(start)). 

**==> picture [477 x 580] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vbulk<br>VIN<br>+<br>BO_NOK<br>Blanking time<br>−<br>1 V if BONOK high<br>0.9 V if BONOK low<br>Figure 67. Brown−out Circuit<br>160<br>120<br>VBulk<br>80.0<br>1<br>40.0<br>0<br>18.0<br>V CC(on) 2<br>16.0<br>14.0<br>12.0 VCC<br>10.0 V CC(off)<br>1.10 V BO(on)<br>900m<br>V BO(off)<br>700m VpinVIN<br>500m<br>3<br>300m<br>8.00<br>6.00 BO Blanking Time BO_NOK low<br>=> Startup mode<br>4.00<br>2.00 BO_NOK<br>0 4<br>46.1m 138m 231m 323m 415m<br>time in seconds<br>(V)<br>(V)<br>(V)<br>(V)<br>**----- End of picture text -----**<br>


**Figure 68. Brown−Out Chronograms (Valley Fill circuit is used)** 

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**29** 

**NCL30082** 

## **CS Pin Short Circuit Protection** 

Normally, if the CS pin or the sense resistor is shorted to ground, the Driver will not be able to turn off, leading to potential damage of the power supply. To avoid this, the versions A, B, B1, B2, B3 and D feature a circuit to protect the power supply against a short circuit of the CS pin. When 

the MOSFET is on, if the CS voltage stays below VCS(low) after the adaptive blanking timer has elapsed, the controller shuts down and will attempt to restart on the next VCC hiccup. In the NCL30082B1, this protection is disabled. 

**==> picture [391 x 222] intentionally omitted <==**

**----- Start of picture text -----**<br>
Adaptative<br>VVIN Blanking Time<br>Q_drv<br>CS<br>S<br>VCS(low) Q CS_short<br>Q<br>R<br>UVLO<br>BO_NOK<br>−<br>+<br>**----- End of picture text -----**<br>


**Figure 69. CS Pin Short Circuit Protection Schematic** 

## **Fault Management** 

## OFF Mode 

The circuit turns off whenever a major condition prevents it from operating: 

- Incorrect feeding of the circuit: “UVLO high”. The UVLO signal becomes high when VCC drops below VCC(off) and remains high until VCC exceeds VCC(on). 

- OTP 

- VCC OVP 

- OVP2 (additional OVP provided by SD pin) 

- Output diode short circuit protection: “WOD_SCP high” 

- Output / Auxiliary winding Short circuit protection: “Aux_SCP high” 

In this mode, the DRV pulses are stopped. The VCC voltage decrease through the controller own consumption (ICC1). 

For the output diode short circuit protection, the CS pin short circuit protection, the output / aux. winding short circuit protection and the OVP2, the controller waits 4 seconds (auto−recovery timer) and then initiates a startup sequence (VCC ≥ VCC(on)) before re−starting switching. 

## Latch Mode 

This mode is activated by the output diode short−circuit protection (WOD_SCP), the OTP and the Aux−SCP in **version A only.** 

In this mode, the DRV pulses are stopped and the controller is latched. There are hiccups on VCC. 

The circuit un−latches when VCC < VCC(reset). 

- Die over temperature (TSD) 

- Brown−Out: “BO_NOK” high 

- Pin CS short circuited to GND: “CS_short high” 

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**30** 

**NCL30082** 

**==> picture [476 x 384] intentionally omitted <==**

**----- Start of picture text -----**<br>
Reset<br>Timer has<br>finished<br>counting<br>VCC > VCC(on)<br>VCC < VCC(off)<br>or<br>BO_NOK  ↓<br>OVP2 or BO_NOK high<br>VCC_OVP or OTP<br>Stop<br>or TSD<br>4−s or CS_Short<br>Timer<br>VCC<br>Disch.<br>BO_NOK high<br>or OTP<br>or TSD<br>OVP2 or CS_Short<br>or WOD_SCP<br>or Aux_SCP<br>or VCC_OVP<br>Run<br>VCC < VCC(off)<br>With states: Reset → Controller is reset, ICC = ICC(start)<br>Stop → Controller is ON, DRV is not switching, tOTP(start) has elapsed<br>Run → Normal switching<br>VCC Disch. → No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)<br>4−s Timer → the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)<br>**----- End of picture text -----**<br>


Note: For the NCL30082B1, the CS pin short circuit Protection is disabled 

**Figure 70. State Diagram for B, B1, B2, B3 and D Version Faults** 

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**31** 

**NCL30082** 

**==> picture [389 x 310] intentionally omitted <==**

**----- Start of picture text -----**<br>
Reset<br>Timer has<br>finished<br>counting VCC > VCC(on)<br>VCC < VCC(off)<br>or<br>VCC < VCC(reset) BO_NOK  ↓<br>OVP2 or<br>Timer4−s VCC_OVP Stop BO_NOK highor TSD<br>or CS_Short<br>VCC<br>Disch.<br>OVP2 or OTP<br>VCC_OVP<br>BO_NOK high<br>or TSD<br>or CS_Short<br>Latch<br>Run<br>OTP or VCC < VCC(off)<br>WOD_SCP or<br>Aux_SCP<br>**----- End of picture text -----**<br>


**==> picture [476 x 88] intentionally omitted <==**

**----- Start of picture text -----**<br>
With states: Reset → Controller is reset, ICC = ICC(start)<br>Stop → Controller is ON, DRV is not switching, tOTP(start) has elapsed<br>Run → Normal switching<br>VCC Disch. → No switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)<br>4−s Timer → the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)<br>Latch → Controller is latched off, VCC is ramping up and down between VCC(on) and VCC(off),<br>only VCC(reset) can release the latch.<br>**----- End of picture text -----**<br>


**Figure 71. State Diagram for A Version Faults** 

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**32** 

**NCL30082** 

## **OPTIONS** 

|**OPTIONS**|||||||||
|---|---|---|---|---|---|---|---|---|
|**Controller**|**Output SCP**|**Winding/**<br>**Output**<br>**Diode SCP**|**Over**<br>**Temperature**<br>**Protection**|**CS Pin**<br>**Short**<br>**Protection**|**VREF**|**ZCD**<br>**Blanking**|**Brown-Out**<br>**blanking**|**Thermal**<br>**Foldback**|
|NCL30082A|Latched|Latched|Latched|Yes|250 mV|3�s|50 ms|Smooth output<br>current<br>decrease|
|NCL30082B|Auto-recovery|Auto-recovery|Auto-recovery|Yes|250 mV|3�s|50 ms|Smooth output<br>current<br>decrease|
|NCL30082B1|Auto-recovery|Auto-recovery|Auto-recovery|No|250 mV|3�s|50 ms|Smooth output<br>current<br>decrease|
|NCL30082B2|Auto-recovery|Auto-recovery|Auto-recovery|Yes|250 mV|1.5�s|50 ms|Smooth output<br>current<br>decrease|
|NCL30082B3|Auto-recovery|Auto-recovery|Auto-recovery|Yes|333 mV|1.5�s|50 ms|Smooth output<br>current<br>decrease|
|NCL30082B4|Auto-recovery|Auto-recovery|Auto-recovery|No|250 mV|1.5�s|50 ms|Smooth output<br>current<br>decrease|
|NCL30082B5|Auto-recovery|Auto-recovery|Auto-recovery|No|333 mV|1.5�s|50 ms|Smooth output<br>current<br>decrease|
|NCL30082D|Auto-recovery|Auto-recovery|Auto-recovery|Yes|500 mV|3�s|15 ms|Steep output<br>current<br>decrease|



## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**||||
|---|---|---|---|
|**Device**|**Package Marking**|**Package Type**|**Shipping**†|
|NCL30082ADMR2G|AAC|Micro8<br>(Pb−Free, Halide−Free)|4000 / Tape & Reel|
|NCL30082BDMR2G|AAD|Micro8<br>(Pb−Free, Halide−Free)|4000 / Tape & Reel|
|NCL30082B1DMR2G|AAH|Micro8<br>(Pb−Free, Halide−Free)|4000 / Tape & Reel|
|NCL30082BDR2G|L30082B|SOIC−8<br>(Pb−Free)|2500 / Tape & Reel|
|NCL30082B1DR2G|L30082B1|SOIC−8<br>(Pb−Free)|2500 / Tape & Reel|
|NCL30082B2DR2G|L30082B2|SOIC−8<br>(Pb−Free)|2500 / Tape & Reel|
|NCL30082B3DR2G|L30082B3|SOIC−8<br>(Pb−Free)|2500 / Tape & Reel|
|NCL30082B4DR2G|L30082B4|SOIC−8<br>(Pb−Free)|2500 / Tape & Reel|
|NCL30082B5DR2G|L30082B5|SOIC−8<br>(Pb−Free)|2500 / Tape & Reel|
|NCL30082DDR2G|L30082D|SOIC−8<br>(Pb−Free)|2500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**33** 

**NCL30082** 

## **PACKAGE DIMENSIONS** 

**Micro8** � CASE 846A−02 ISSUE J 

**==> picture [478 x 204] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|D|NOTES:|
|1.|DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.|
|2.|CONTROLLING DIMENSION: MILLIMETER.|
|3.|DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE|
|BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED|
|HE|E|0.15 (0.006) PER SIDE.|
|4.|DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.|
|INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.|
|5.|846A-01 OBSOLETE, NEW STANDARD 846A-02.|
|MILLIMETERS|INCHES|
|PIN 1 ID|DIM|MIN|NOM|MAX|MIN|NOM|MAX|
|e|A|−−|−−|1.10|−−|−−|0.043|
|b|8 PL|A1|0.05|0.08|0.15|0.002|0.003|0.006|
|0.08 (0.003)|M|T|B|S|A|S|b|0.25|0.33|0.40|0.010|0.013|0.016|
|c|0.13|0.18|0.23|0.005|0.007|0.009|
|D|2.90|3.00|3.10|0.114|0.118|0.122|
|E|2.90|3.00|3.10|0.114|0.118|0.122|
|e|0.65 BSC|0.026 BSC|
|−T−|SEATINGPLANE|L|0.40|0.55|0.70|0.016|0.021|0.028|
|0.038 (0.0015)|A|H|E|4.75|4.90|5.05|0.187|0.193|0.199|
|A|1|c|L|
|RECOMMENDED|
|SOLDERING FOOTPRINT*|

**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
8X<br>8X 0.48 0.80<br>5.25<br>0.65<br>PITCH<br>DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

**www.onsemi.com** 

**34** 

**NCL30082** 

## **PACKAGE DIMENSIONS** 

**==> picture [468 x 454] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOIC−8 NB<br>CASE 751−07<br>ISSUE AK NOTES:<br>−X− 1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>artes 5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>4 MAXIMUM MATERIAL CONDITION.<br>−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW<br>STANDARD IS 751−07.<br>G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>A 4.80 5.00 0.189 0.197<br>C N X 45 B 3.80 4.00 0.150 0.157<br>SEATING C 1.35 1.75 0.053 0.069<br>PLANE D 0.33 0.51 0.013 0.020<br>−Z− G 1.27 BSC 0.050 BSC<br>H 0.10 0.25 0.004 0.010<br>0.10 (0.004) J 0.19 0.25 0.007 0.010<br>H D M J K 0.40 1.27 0.016 0.050<br>M 0  8  0  8<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244<br>SOLDERING FOOTPRINT*<br>1.52<br>0.060<br>ane<br>7.0 4.0<br>0.275 mal 0.155<br>0.6 1.270<br>0.024 ani 0.050<br>SCALE 6:1 mm<br>inches<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


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**35**