NCL30059BDR2G

**DATA SHEET www.onsemi.com** 

## High-Voltage Half-Bridge Controller for LED Lighting Applications 

## NCL30059 

The NCL30059 is a self−oscillating high voltage MOSFET driver primarily tailored for LED driver applications using half−bridge topology. LLC and LCC configurations are supported with optimized wide range control offered by the latter for Constant Current (CC) applications. Due to its proprietary 600 V technology, the driver is useful for bulk voltages utilized in 277 VAC lighting applications. Operating frequency of the driver can be adjusted from 25 kHz to 250 kHz using a single resistor. Adjustable brown−out protection assures correct bulk voltage operating range. An internal 100 ms PFC delay timer ensures the converter is enabled after the bulk voltage is fully stabilized. The device provides fixed dead−time which helps to lower the shoot−through current. 

## **Features** 

## **MARKING DIAGRAM** 

**==> picture [140 x 116] intentionally omitted <==**

**----- Start of picture text -----**<br>
8<br>8<br>30059B<br>1<br>ALYWW<br>SOIC−8 �<br>CASE 751<br>1<br>A = Assembly Location<br>L = Wafer Lot<br>Y = Year<br>WW = Work Week<br>� = Pb−Free Package<br>**----- End of picture text -----**<br>


## **PINOUT DIAGRAM** 

**==> picture [134 x 66] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCC Vboot<br>Rt Mupper<br>BO HB<br>GND Mlower<br>**----- End of picture text -----**<br>


- Wide Operating Frequency Range − from 25 kHz to 250 kHz 

- Minimum Frequency Adjust Accuracy �3% 

- Fixed Dead Time − 0.6 �s 

- Adjustable Brown−out Protection for a Simple PFC Association 

- 100 ms PFC Delay Timer 

- Latched Input for Severe Fault Conditions, e.g. Overtemperature or OVP 

- Internal 16 V VCC Clamp 

- Low Startup Current of 50 �A Maximum 

## **ORDERING INFORMATION** 

|**Device**|**Package**|**Shipping**†|
|---|---|---|
|NCL30059BDR2G|SOIC−8<br>(Pb−Free)|2500 /<br>Tape & Reel|



   - †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

- 1 A / 0.5 A Peak Current Sink / Source Drive Capability 

- Operation up to 600 V Bulk Voltage 

- Internal Temperature Shutdown 

- Supports Outdoor Use: −40  C to +125  C 

- PSR Current Regulation �2% 

- Efficiency up to 92% 

- SOIC−8 Package 

- These are Pb−Free Devices 

## **Typical Applications** 

- Low Cost Resonant Converters 

- Low Parts Count 

- CV and CC LED Drivers 

- Wide Output Voltage Range LCC Drivers 

- Wallpack and Bollard LED Drivers 

- High Bay and Streetlight LED Drivers 

Publication Order Number: **NCL30059/D** 

**1** 

 Semiconductor Components Industries, LLC, 2017 **July, 2024 − Rev. 1** 

**NCL30059** 

**==> picture [483 x 182] intentionally omitted <==**

**----- Start of picture text -----**<br>
+HV<br>Dboot<br>Rbo1<br>Cboot<br>U1<br>Vboot M1 LED1<br>Vcc Vcc Mupper<br>AC PFC NCL30059 HB Lres Chb LED2<br>Input FrontEnd BO Mlower M2 Cres<br>GND Rt Rbias<br>Ccomp<br>Rfmax Diso<br>U2 Rfb1<br>Rbo2 Rfstart<br>Cave<br>CSS Rfb2 Rsense<br>Return<br>**----- End of picture text -----**<br>


**Figure 1. Typical LCC Application Example** 

**www.onsemi.com** 

**2** 

**NCL30059** 

**==> picture [491 x 590] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>Vboot<br>S Q Pulse Level S Q<br>D Trigger Shifter Mupper<br>R Q<br>+<br>CLK<br>Rt Vref Ct +− −Vref R Q Bridge<br>UV<br>Detect<br>IDT<br>PFC Delay<br>(100ms) VCC<br>VCC Vref<br>VDD<br>PON<br>VCC RESET Mlower<br>Delay<br>VCC<br>Management<br>VCC<br>Clamp<br>TSD<br>Q<br>− 20 � s<br>+ Filter S R<br>+− Vreflatch<br>BO<br>+ 20 � s<br>− Filter<br>+− VrefBO<br>SW<br>Switch SW Open for VBO > VrefBO<br>GND<br>Ihyster<br>**----- End of picture text -----**<br>


**Figure 2. Internal Circuit Architecture** 

**www.onsemi.com** 

**3** 

**NCL30059** 

## **PIN FUNCTION DESCRIPTION** 

|**Pin #**|**Pin Name**|**Function**|**Pin Description**|
|---|---|---|---|
|1|VCC|Supplies the Driver|The driver accepts up to 16 V (given by internal zener clamp).|
|2|Rt|Timing Resistor|Connecting a resistor between this pin and GND, sets the operating frequency|
|3|BO|Brown−Out|Detects low input voltage conditions. When brought above Vlatch, it fully latches off<br>the driver.|
|4|GND|IC Ground|−|
|5|Mlower|Low−Side Driver Output|Drives the lower side MOSFET.|
|6|HB|Half−Bridge Connection|Connects to the half−bridge output.|
|7|Mupper|High−Side Driver Output|Drives the higher side MOSFET.|
|8|Vboot|Bootstrap Pin|The floating supply terminal for the upper stage.|



## **MAXIMUM RATINGS TABLE** 

|**MAXIMUM**|**RATINGS TABLE**|||
|---|---|---|---|
|**Symbol**|**Rating**|**Value**|**Unit**|
|Vbridge|High Voltage Bridge Pin − Pin 6|−1 to +600|V|
|Vboot −<br>Vbridge|Floating Supply Voltage|0 to 20|V|
|VDRV_HI|High−Side Output Voltage|Vbridge − 0.3 to<br>Vboot + 0.3|V|
|VDRV_LO|Low−Side Output Voltage|−0.3 to VCC+0.3|V|
|dVbridge/dt|Allowable Output Slew Rate|�50|V/ns|
|ICC|Maximum Current that Can Flow into VCCPin (Pin 1), (Note 1)|20|mA|
|V_Rt|Rt Pin Voltage|−0.3 to 5|V|
||Maximum Voltage, All Pins (Except Pins 4 and 5)|−0.3 to 10|V|
|R�JA|Thermal Resistance Junction−to−Air, IC Soldered on 50 mm2Cooper 35�m|178|C/W|
|R�JA|Thermal Resistance Junction−to−Air, IC Soldered on 200 mm2Cooper 35�m|147|C/W|
||Storage Temperature Range|−60 to +150|C|
||ESD Capability, Human Body Model (All Pins Except Pins 1 , 6, 7 and 8)|2|kV|
||ESD Capability, Machine Model (All Pins Except Pins 1, 6, 7 and 8)|200|V|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device contains internal zener clamp connected between VCC and GND terminals. Current flowing into the VCC pin has to be limited by an external resistor when device is supplied from supply which voltage is higher than VCCclamp (16 V typically). The ICC parameter is specified for VBO = 0 V. 

**www.onsemi.com** 

**4** 

## **NCL30059** 

**ELECTRICAL CHARACTERISTICS** (For typical values TJ = 25C, for min/max values TJ = −40C to +125C, Max TJ = 150C, VCC = 12 V, unless otherwise noted) 

|VCC= 12 V, unless otherwise noted)|||||||
|---|---|---|---|---|---|---|
|**Characteristic**|**Pin**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**SUPPLY SECTION**|||||||
|Turn−On Threshold Level, VCCGoing Up|1|VCCON|10|11|12|V|
|Minimum Operating Voltage after Turn−On|1|VCCmin|8|9|10|V|
|Startup Voltage on the Floating Section|1|VbootON|7.8|8.8|9.8|V|
|Cutoff Voltage on the Floating Section|1|Vbootmin|7|8|9|V|
|VCCLevel at which the Internal Logic gets Reset|1|VCCreset|−|6.5|−|V|
|Startup Current, VCC< VCCON, 0C�Tamb �+125C|1|ICC|−|−|50|�A|
|Startup Current, VCC< VCCON, −40C�Tamb< 0C|1|ICC|−|−|65|�A|
|Internal IC Consumption, No Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz|1|ICC1|−|2.2|−|mA|
|Internal IC Consumption, 1 nF Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz|1|ICC2|−|3.4|−|mA|
|Consumption in Fault Mode (Drivers Disabled, VCC> VCC(min), RT= 3.5 k�)|1|ICC3|−|2.56|−|mA|
|Consumption During PFC Delay Period, 0C�Tamb �+125C||ICC4|−|−|400|�A|
|Consumption During PFC Delay Period, −40C�Tamb< 0C||ICC4|−|−|470|�A|
|Internal IC Consumption, No Output Load on Pin 8/7 FWS= 100 kHz|8|Iboot1|−|0.3|−|mA|
|Internal IC Consumption, 1 nF Output Load on Pin 8/7 FWS= 100 kHz|8|Iboot2|−|1.44|−|mA|
|Consumption in Fault Mode (Drivers Disabled, Vboot> Vbootmin)|8|Iboot3|−|0.1|−|mA|
|VCCZener Clamp Voltage @ 20 mA|1|VCCclamp|15.4|16|17.5|V|
|**INTERNAL OSCILLATOR**|||||||
|Minimum Switching Frequency, Rt= 35 k�on Pin 2, DT= 600 ns|2|FSWmin|24.2<br>5|25|25.7<br>5|kHz|
|Maximum Switching Frequency, Rt= 3.5 k�on Pin 2, DT= 600 ns|2|FSWmax|208|245|282|kHz|
|Reference Voltage for all Current Generations|2|VrefRT|3.33|3.5|3.67|V|
|Internal Resistance Discharging Csoft−start|2|Rtdischarge|−|500|−|�|
|Operating Duty Cycle Symmetry|5, 7|DC|48|50|52|%|
|NOTE:<br>Maximum capacitance directly connected to Pin 2 must be under 100 pF.<br>**DRIVE OUTPUT**|||||||
|Output Voltage Rise Time @ CL = 1 nF, 10−90% of Output Signal|5, 7|Tr|−|40|−|ns|
|Output Voltage Fall Time @ CL = 1 nF, 10−90% of Output Signal|5, 7|Tf|−|20|−|ns|
|Source Resistance|5, 7|ROH|−|12|−|�|
|Sink Resistance|5, 7|ROL|−|5|−|�|
|Dead−Time (Measured Between 50% of Rise and Fall Edge)|5,7|T_dead|540|610|720|ns|
|Leakage Current on High Voltage Pins to GND (600 Vdc)|6,7,8|IHV_Leak|−|−|5|�A|
|**PROTECTION**|||||||
|Brown−Out Input Bias Current|3|IBObias|−|0.01|−|�A|
|Brown−Out Level|3|VBO|0.95|1|1.05|V|
|Hysteresis Current, Vpin3< VBO|3|IBO|15.6|18.2|20.7|�A|
|Latching Voltage on BO Pin|3|Vlatch|1.9|2|2.1|V|
|Propagation Delay Before Drivers are Stopped|3|EN Delay|−|20|−|�s|
|Delay Before Any Driver Restart|−|PFC Delay|−|100|−|ms|
|Temperature Shutdown (Guaranteed by design)|−|TSD|140|−|−|C|
|Hysteresis|−|TSDhyste|−|30|−|C|



**www.onsemi.com** 

**5** 

**NCL30059** 

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be 

indicated by the Electrical Characteristics if operated under different conditions. 

**==> picture [491 x 608] intentionally omitted <==**

**----- Start of picture text -----**<br>
11.01 8.98<br>11.00<br>8.97<br>10.99<br>8.96<br>10.98<br>8.95<br>10.97<br>10.96 8.94<br>10.95 8.93<br>10.94<br>8.92<br>10.93<br>10.92 8.91<br>10.91 8.90<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C) TEMPERATURE (C)<br>Figure 3. VCCon Figure 4. VCCmin<br>8.85 8.10<br>8.80 8.05<br>8.00<br>8.75<br>7.95<br>8.70<br>7.90<br>8.65<br>7.85<br>8.60<br>7.80<br>8.55 7.75<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C) TEMPERATURE (C)<br>Figure 5. VBOOTon Figure 6. VBOOTmin<br>20 8<br>18<br>7<br>16<br>6<br>14<br>12 5<br>10 4<br>8<br>3<br>6<br>2<br>4<br>2 1<br>0 0<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C) TEMPERATURE (C)<br>Figure 7. ROH Figure 8. ROL<br>VOLTAGE (V) VOLTAGE (V)<br>VOLTAGE (V)<br>VOLTAGE (V)<br>) � ) �<br>RESISTANCE ( RESISTANCE (<br>**----- End of picture text -----**<br>


**www.onsemi.com** 

**6** 

**NCL30059** 

**==> picture [242 x 401] intentionally omitted <==**

**----- Start of picture text -----**<br>
243.4<br>243.2<br>243.0<br>242.8<br>242.6<br>242.4<br>242.2<br>242.0<br>241.8<br>−40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C)<br>Figure 9. FSWmax<br>45.0<br>40.0<br>35.0<br>30.0<br>25.0<br>20.0<br>15.0<br>10.0<br>5.0<br>0.0<br>−40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C)<br>Figure 11. ICC_startup<br>FREQUENCY (kHz)<br>A)<br>�<br>CURRENT (<br>**----- End of picture text -----**<br>


**==> picture [242 x 192] intentionally omitted <==**

**----- Start of picture text -----**<br>
580<br>560<br>540<br>520<br>500<br>480<br>460<br>440<br>420<br>400<br>−40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C)<br>Figure 13. Rt_discharge<br>) �<br>RESISTANCE (<br>**----- End of picture text -----**<br>


**==> picture [238 x 189] intentionally omitted <==**

**----- Start of picture text -----**<br>
25.05<br>25.00<br>24.95<br>24.90<br>24.85<br>24.80<br>24.75<br>−40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C)<br>Figure 10. FSWmin<br>FREQUENCY (kHz)<br>**----- End of picture text -----**<br>


**==> picture [233 x 189] intentionally omitted <==**

**----- Start of picture text -----**<br>
450<br>400<br>350<br>300<br>250<br>200<br>150<br>100<br>50<br>0<br>−40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C)<br>Figure 12. ICC4<br>A)<br>�<br>CURRENT (<br>**----- End of picture text -----**<br>


**==> picture [238 x 188] intentionally omitted <==**

**----- Start of picture text -----**<br>
645<br>640<br>635<br>630<br>625<br>620<br>615<br>610<br>−40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C)<br>Figure 14. Tdead<br>TIME (ns)<br>**----- End of picture text -----**<br>


**www.onsemi.com** 

**7** 

**NCL30059** 

**==> picture [238 x 189] intentionally omitted <==**

**----- Start of picture text -----**<br>
109<br>108<br>107<br>106<br>105<br>104<br>103<br>102<br>101<br>100<br>90<br>−40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C)<br>Figure 15. PFCdelay<br>TIME (ms)<br>**----- End of picture text -----**<br>


**==> picture [240 x 188] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.008<br>2.006<br>2.004<br>2.002<br>2.000<br>1.998<br>1.996<br>1.994<br>1.992<br>1.990<br>−40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C)<br>Figure 16. VLATCH<br>VOLTAGE (V)<br>**----- End of picture text -----**<br>


**==> picture [493 x 402] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.015 19.4<br>19.2<br>1.014<br>19.0<br>1.013<br>18.8<br>1.012<br>18.6<br>1.011 18.4<br>18.2<br>1.010<br>18.0<br>1.009<br>17.8<br>1.008<br>17.6<br>1.007 17.4<br>−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120<br>TEMPERATURE (C) TEMPERATURE (C)<br>Figure 17. VBO Figure 18. IBO<br>17.0<br>290<br>16.8<br>240<br>16.6<br>190<br>16.4<br>140<br>16.2<br>16.0 90<br>15.8 40<br>−40 −20 0 20 40 60 80 100 120 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1<br>TEMPERATURE (C) Irt (mA)<br>Figure 19. VCC_clamp Figure 20. Irt and Appropriate Frequency<br>A)<br>�<br>VOLTAGE (V)<br>CURRENT (<br>VOLTAGE (V)<br>FREQUENCY (kHz)<br>**----- End of picture text -----**<br>


**www.onsemi.com** 

**8** 

**NCL30059** 

## **APPLICATION INFORMATION** 

The NCL30059 is primarily intended to drive low cost half−bridge applications. It supports LLC and optimized LCC topologies offering wide output voltage range in constant current (CC) mode making it ideal for LED drivers. The IC includes several features that help the designer to cope with resonant SPMS design. All features are described thereafter: 

- **Wide Operating Frequency Range** : The internal current controlled oscillator is capable to operate over wide frequency range up to 250 kHz. Minimum frequency accuracy is �3%. 

- **Fixed Dead−Time** : Internal dead−time control is optimized to avoid cross conduction or shoot−through during transitions between low and high side conduction. 

- **100 ms PFC Timer** : Fixed delay is placed to IC operation whenever the driver restarts (VCCON or BO_OK detect events). This delay assures that the bulk voltage will be stabilized prior to switching operation. Another benefit of this delay is that the soft start capacitor will be fully discharged before any restart. 

- **Brown−Out Detection** : The BO input monitors bulk voltage level via resistor divider and thus assures that the application is working only for wanted bulk voltage band. The BO input sinks current of 18.2 �A until the VrefBO threshold is reached. Designer can thus adjust the bulk voltage hysteresis according to the application needs. 

- **Latched Input** : The latched comparator input is connected in parallel to the BO terminal to allow the designer latch the IC if necessary − overvoltage or overtemperature shutdown can be implemented using this latch. The supply voltage has to be cycled down below VCCreset threshold, or VBO diminished under VBO level to reset the latch and enable restart. 

- **Internal VCC Clamp** : The internal zener clamp offers a way to prepare passive voltage regulator to maintain VCC voltage at 16 V in case the controller is supplied from unregulated power supply or from bulk capacitor. 

- **Low Startup Current** : This device features maximum startup current of 50 �A which allows the designer to use high value startup resistor for applications when driver is supplied from the auxiliary winding. Power dissipation of startup resistor is thus significantly reduced. 

## **Current Controlled Oscillator** 

The current controlled oscillator features a high−speed circuitry allowing operation from 50 kHz up to 500 kHz. However, as a division by two internally creates the two Q and Q outputs, the final effective signal on output Mlower and Mupper switches between 25 kHz and 250 kHz. The VCO is configured in such a way that if the current that flows out from the Rt pin increases, the switching frequency also goes up. Figure 21 shows the architecture of this oscillator. 

**==> picture [483 x 184] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>S Q A<br>D<br>+<br>− CLK<br>R Q B<br>+<br>− +− Ct IDT + DeadTime<br>Rsoft−start Rt Vref Rt − Vref<br>Csoft−start Rt Delay<br>From PFC Delay PON Reset<br>**----- End of picture text -----**<br>


**Figure 21. The Internal Current Controlled Oscillator Architecture** 

**www.onsemi.com** 

**9** 

**NCL30059** 

The internal timing capacitor Ct is charged by current which is proportional to the current flowing out from the Rt pin. The discharging current IDT is applied when voltage on this capacitor reaches 2.5 V. The output drivers are disabled during discharge period so the dead time length is given by the discharge current sink capability. Discharge sink is disabled when voltage on the timing capacitor reaches zero and charging cycle starts again. The charging current and thus also whole oscillator is disabled during the PFC delay period to keep the IC consumption below 400 �A. 

This is valuable for applications that are supplied from auxiliary winding and VCC capacitor is supposed to provide energy during PFC delay period. 

For resonant LED driver applications it is necessary to adjust minimum operating frequency with high accuracy. The designer also needs to limit maximum operating and startup frequency. All these parameters can be adjusted using few external components connected to the Rt pin as depicted in Figure 22. 

**==> picture [304 x 206] intentionally omitted <==**

**----- Start of picture text -----**<br>
NCL30059<br>Rt<br>VCC<br>Rfmax Rfmax−CC<br>Rfstart Rbias<br>D1<br>Rt<br>(to secondary Rcomp Ccomp<br>voltage regulator)<br>CSS<br>TLV431 (to primary<br>current sensor)<br>Voltage Feedback Current Feedback<br>**----- End of picture text -----**<br>


**Figure 22. Typical Rt Pin Connection** 

The minimum switching frequency is given by the Rt resistor value. This frequency is reached if there is no optocoupler or current feedback action and soft start period has been already finished. The maximum switching frequency excursion is limited by the Rfmax selection. Note that the Fmax value is influenced by the optocoupler saturation voltage value. Resistor Rfstart together with capacitor CSS prepares the soft start period after PFC timer elapses. The Rt pin is grounded via an internal switch during the PFC delay period to assure that the soft start capacitor will be fully discharged via Rfstart resistor. 

Constant LED current is achieved using a feedback loop monitoring the primary current. The sensing voltage must be scaled by the turns ratio of the transformer. The Rt pin reference voltage is VrefRt = 3.5 V. The control regulator operates on the difference between the Rt pin reference voltage and the minimum voltage compliance of the 

regulator. This voltage difference is applied across Rfmax−CC. 

The TLV431 shunt regulator is used in Figure 22 as the constant current control regulator. Diode D1 is used to establish minimum regulator bias current via resistor Rbias. Total saturation voltage of this solution is 1.25 + 0.6 = 1.85 V for room temperature. Shottky diode will further decrease saturation voltage. The Rfmax−CC resistor limits the maximum frequency delivered by this regulation loop. This parameter is affected by D1 temperature drift. 

## **Brown−Out Protection** 

The Brown−Out circuitry (BO) offers a way to protect the application from low DC input voltages. Operation is blocked below a set threshold. Hysteresis is provided by the switched current source providing stable operation. The internal circuitry, depicted by Figure 23, offers a way to monitor the high−voltage (HV) rail. 

**www.onsemi.com** 

**10** 

**NCL30059** 

**==> picture [327 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vbulk<br>Rupper<br>BO<br>+ 20 � s<br>− Filter to BO_OK and gates<br>Rlower +− VrefBO<br>SW<br>To PFC Delay<br>IBO<br>High Level for 50 ms after VCC On<br>**----- End of picture text -----**<br>


**Figure 23. The internal Brown−Out Configuration with an Offset Current Sink** 

A resistive divider made of Rupper and Rlower, brings a portion of the HV rail on Pin 3. Below the turn−on level, the 18.2 �A current sink (IBO) is on. Therefore, the turn−on level is higher than the level given by the division ratio brought by the resistive divider. To the contrary, when the 

internal BO_OK signal is high (PFC timer runs or Mlower and Mupper pulse), the IBO sink is deactivated. As a result, it becomes possible to select the turn−on and turn−off levels via a few lines of algebra: 

## **IBO is ON** 

**==> picture [365 x 28] intentionally omitted <==**

## **IBO is OFF** 

**==> picture [310 x 28] intentionally omitted <==**

We can extract Rlower from Equation 2 and plug it into Equation 1, then solve for Rupper: 

**==> picture [326 x 66] intentionally omitted <==**

If we decide to turn−on our converter for Vbulk1 equals 350 V and turn it off for Vbulk2 equals 250 V, then for IBO = 18.2 �A and VrefBO = 1.0 V we obtain: R = 5.494 M� upper Rlower = 22.066 V 

The bridge power dissipation is 400[2] / 5.517 M� = 29 mW when front−end PFC stage delivers 400 V. Figure 24 simulation result confirms our calculations. 

**www.onsemi.com** 

**11** 

**NCL30059** 

**Figure 24. Simulation Results for 350/250 ON/OFF Brown−Out Levels** 

**Figure 25. BO Input Functionality − Vbulk2 < Vbulk < Vbulk1** 

**www.onsemi.com** 

**12** 

**NCL30059** 

**Figure 26. BO Input Functionality −Vbulk2 < Vbulk < Vbulk1, PFC Start Follows** 

**Figure 27. BO Input Functionality − Vbulk > Vbulk1** 

**www.onsemi.com** 

**13** 

**NCL30059** 

**Figure 28. BO Input Functionality − Vbulk < Vbulk2, PFC Start Follows** 

The IBO current sink is turned ON for 50 ms after any controller restart to let the BO input voltage stabilize (there can be connected big capacitor to the BO input and the IBO is only 18.2 A so it will take some time to discharge). Once u the 50 ms one shoot pulse ends the BO comparator is supposed to either hold the IBO sink turned ON (if the bulk voltage level is not sufficient) or let it turned OFF (if the bulk voltage is higher than Vbulk1). See Figures 25 through 28 for better understanding on how the BO input works. 

## **Latched−Off Protection** 

There are some situations where the converter shall be fully turned−off and stay latched. This can happen in presence of an overvoltage (the feedback loop is drifting) or when an overtemperature is detected. Due to the addition of a comparator on the BO Pin, a simple external circuit can lift up this pin above Vlatch (2 V typical) and permanently disable pulses. The VCC needs to be cycled down below 6.5 V typically to reset the controller. 

**==> picture [451 x 153] intentionally omitted <==**

**----- Start of picture text -----**<br>
to Permanent Latch<br>VCC Vbulk + 20 s<br>Filter<br>Vout −<br>+−<br>Vreflatch<br>Q1 Rupper<br>BO<br>: + 20 s BO_OK<br>NTC Rlower SW +− − Filter<br>VrefBO<br>IBO To PFC Delay<br>High Level for 50 ms After VCC On<br>**----- End of picture text -----**<br>


**Figure 29. Adding a Comparator on the BO Pin Offers a Way to Latch−Off the Controller** 

On Figure 29, Q1 is biased off and does not affect the BO measurement as long as the NTC and the optocoupler are not activated. As soon as the secondary optocoupler senses an 

OVP condition, or the NTC reacts to a high ambient temperature, Q1 base is biased on and the BO Pin goes up, permanently latching off the controller. 

## **The High−Voltage Driver** 

Figure 30 shows the internal architecture of the high−voltage section. The device incorporates an upper UVLO circuitry that makes sure enough Vgs is available for 

the upper side MOSFET. The VCC for floating driver section is provided by Cboot capacitor that is refilled by external bootstrap diode. 

**www.onsemi.com** 

**14** 

**NCL30059** 

**==> picture [435 x 253] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vboot Vbulk<br>Pulse Level S Q Cboot<br>Trigger Shifter Mupper<br>R Q<br>UV HB<br>Detect<br>Dboot<br>DEAD TIME from PFC VCC<br>Delay Vaux<br>B +<br>B<br>A Mlower<br>A Delay<br>GND<br>from latch<br>high if OK<br>**----- End of picture text -----**<br>


**Figure 30. The Internal High−Voltage Section of the NCL30059** 

The A and B outputs are delivered by the internal logic, as depicted in block diagram. This logic is constructed in such a way that the Mlower driver starts to pulse firs after any driver restart. The bootstrap capacitor is thus charged during first pulse. A delay is inserted in the lower rail to ensure good 

matching between these propagating signals. As stated in the maximum rating section, the floating portion can go up to 600 Vdc and makes the IC perfectly suitable for offline applications featuring a 400 V PFC front−end stage. 

**www.onsemi.com** 

**15** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [34 x 28] intentionally omitted <==**

**----- Start of picture text -----**<br>
8<br>1<br>**----- End of picture text -----**<br>


**==> picture [42 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCALE 1:1<br>**----- End of picture text -----**<br>


**SOIC−8 NB** CASE 751−07 ISSUE AK 

**==> picture [79 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
DATE 16 FEB 2011<br>**----- End of picture text -----**<br>


**==> picture [471 x 425] intentionally omitted <==**

**----- Start of picture text -----**<br>
NOTES:<br>−X− 1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>4 MAXIMUM MATERIAL CONDITION.<br>−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW<br>STANDARD IS 751−07.<br>G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>A 4.80 5.00 0.189 0.197<br>C N X 45 � B 3.80 4.00 0.150 0.157<br>SEATING C 1.35 1.75 0.053 0.069<br>PLANE D 0.33 0.51 0.013 0.020<br>−Z− G 1.27 BSC 0.050 BSC<br>H 0.10 0.25 0.004 0.010<br>0.10 (0.004) J 0.19 0.25 0.007 0.010<br>H D M J MK 0.400   � 1.278   � 0.0160   � 0.0508   �<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244<br>GENERIC<br>MARKING DIAGRAM*<br>SOLDERING FOOTPRINT*<br>8 8 8 8<br>XXXXX XXXXX XXXXXX XXXXXX<br>1.52 ALYWX ALYWX � AYWW AYWW �<br>0.060<br>1 1 1 1<br>IC IC Discrete Discrete<br>(Pb−Free) (Pb−Free)<br>7.0 4.0<br>XXXXX = Specific Device Code XXXXXX = Specific Device Code<br>0.275 0.155<br>A = Assembly Location A = Assembly Location<br>L = Wafer Lot Y = Year<br>Y = Year WW = Work Week<br>W = Work Week � = Pb−Free Package<br>� = Pb−Free Package<br>0.6 1.270 *This information is generic. Please refer to<br>0.024 0.050 device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ � ”, may<br>or may not be present. Some products may<br>SCALE 6:1<br>� inches [mm] � not follow the Generic Marking.<br>**----- End of picture text -----**<br>


- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

*For additional information on our Pb−Free strategy and soldering details, please download the **onsemi** Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

## **STYLES ON PAGE 2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 1 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**SOIC−8 NB** CASE 751−07 ISSUE AK 

**==> picture [79 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
DATE 16 FEB 2011<br>**----- End of picture text -----**<br>


|STYLE 1:|STYLE 1:|STYLE 2:||STYLE 3:|STYLE 3:||STYLE 4:|STYLE 4:|
|---|---|---|---|---|---|---|---|---|
|PIN 1.|EMITTER|PIN 1.|COLLECTOR, DIE, #1|PIN 1.||DRAIN, DIE #1|PIN 1.|ANODE|
|2.|COLLECTOR|2.|COLLECTOR, #1|2.||DRAIN, #1|2.|ANODE|
|3.|COLLECTOR|3.|COLLECTOR, #2|3.||DRAIN, #2|3.|ANODE|
|4.|EMITTER|4.|COLLECTOR, #2|4.||DRAIN, #2|4.|ANODE|
|5.|EMITTER|5.|BASE, #2|5.||GATE, #2|5.|ANODE|
|6.|BASE|6.|EMITTER, #2|6.||SOURCE, #2|6.|ANODE|
|7.|BASE|7.|BASE, #1|7.||GATE, #1|7.|ANODE|
|8.|EMITTER|8.|EMITTER, #1|8.||SOURCE, #1|8.|COMMON CATHODE|
|STYLE 5:||STYLE 6:||STYLE 7:|||STYLE 8:||
|PIN 1.|DRAIN|PIN 1.|SOURCE|PIN 1.||INPUT|PIN 1.|COLLECTOR, DIE #1|
|2.|DRAIN|2.|DRAIN|2.||EXTERNAL  BYPASS|2.|BASE, #1|
|3.|DRAIN|3.|DRAIN|3.||THIRD STAGE SOURCE|3.|BASE, #2|
|4.|DRAIN|4.|SOURCE|4.||GROUND|4.|COLLECTOR, #2|
|5.|GATE|5.|SOURCE|5.||DRAIN|5.|COLLECTOR, #2|
|6.|GATE|6.|GATE|6.||GATE 3|6.|EMITTER, #2|
|7.|SOURCE|7.|GATE|7.||SECOND STAGE Vd|7.|EMITTER, #1|
|8.|SOURCE|8.|SOURCE|8.||FIRST STAGE Vd|8.|COLLECTOR, #1|
|STYLE 9:||STYLE 10:||STYLE 11:|||STYLE 12:||
|PIN 1.|EMITTER,  COMMON|PIN 1.|GROUND|PIN 1.||SOURCE 1|PIN 1.|SOURCE|
|2.|COLLECTOR, DIE #1|2.|BIAS 1|2.||GATE 1|2.|SOURCE|
|3.|COLLECTOR, DIE #2|3.|OUTPUT|3.||SOURCE 2|3.|SOURCE|
|4.|EMITTER, COMMON|4.|GROUND|4.||GATE 2|4.|GATE|
|5.|EMITTER, COMMON|5.|GROUND|5.||DRAIN 2|5.|DRAIN|
|6.|BASE, DIE #2|6.|BIAS 2|6.||DRAIN 2|6.|DRAIN|
|7.|BASE, DIE #1|7.|INPUT|7.||DRAIN 1|7.|DRAIN|
|8.|EMITTER, COMMON|8.|GROUND|8.||DRAIN 1|8.|DRAIN|
|STYLE 13:||STYLE 14:||STYLE 15:|||STYLE 16:||
|PIN 1.|N.C.|PIN 1.|N−SOURCE|PIN 1.|ANODE 1||PIN 1.|EMITTER, DIE #1|
|2.|SOURCE|2.|N−GATE|2.|ANODE 1||2.|BASE, DIE #1|
|3.|SOURCE|3.|P−SOURCE|3.|ANODE 1||3.|EMITTER, DIE #2|
|4.|GATE|4.|P−GATE|4.|ANODE 1||4.|BASE, DIE #2|
|5.|DRAIN|5.|P−DRAIN|5.|CATHODE, COMMON||5.|COLLECTOR, DIE #2|
|6.|DRAIN|6.|P−DRAIN|6.|CATHODE, COMMON||6.|COLLECTOR, DIE #2|
|7.|DRAIN|7.|N−DRAIN|7.|CATHODE, COMMON||7.|COLLECTOR, DIE #1|
|8.|DRAIN|8.|N−DRAIN|8.|CATHODE, COMMON||8.|COLLECTOR, DIE #1|
|STYLE 17:||STYLE 18:||STYLE 19:|||STYLE 20:||
|PIN 1.|VCC|PIN 1.|ANODE|PIN 1.||SOURCE 1|PIN 1.|SOURCE (N)|
|2.|V2OUT|2.|ANODE|2.||GATE 1|2.|GATE (N)|
|3.|V1OUT|3.|SOURCE|3.||SOURCE 2|3.|SOURCE (P)|
|4.|TXE|4.|GATE|4.||GATE 2|4.|GATE (P)|
|5.|RXE|5.|DRAIN|5.||DRAIN 2|5.|DRAIN|
|6.|VEE|6.|DRAIN|6.||MIRROR 2|6.|DRAIN|
|7.|GND|7.|CATHODE|7.||DRAIN 1|7.|DRAIN|
|8.|ACC|8.|CATHODE|8.||MIRROR 1|8.|DRAIN|
|STYLE 21:||STYLE 22:||STYLE 23:|||STYLE 24:||
|PIN 1.|CATHODE 1|PIN 1.|I/O LINE 1|PIN 1.||LINE 1 IN|PIN 1.|BASE|
|2.|CATHODE 2|2.|COMMON CATHODE/VCC|2.||COMMON ANODE/GND|2.|EMITTER|
|3.|CATHODE 3|3.|COMMON CATHODE/VCC|3.||COMMON ANODE/GND|3.|COLLECTOR/ANODE|
|4.|CATHODE 4|4.|I/O LINE 3|4.||LINE 2 IN|4.|COLLECTOR/ANODE|
|5.|CATHODE 5|5.|COMMON ANODE/GND|5.||LINE 2 OUT|5.|CATHODE|
|6.|COMMON ANODE|6.|I/O LINE 4|6.||COMMON ANODE/GND|6.|CATHODE|
|7.|COMMON ANODE|7.|I/O LINE 5|7.||COMMON ANODE/GND|7.|COLLECTOR/ANODE|
|8.|CATHODE 6|8.|COMMON ANODE/GND|8.||LINE 1 OUT|8.|COLLECTOR/ANODE|
|STYLE 25:||STYLE 26:||STYLE|27:||STYLE 28:||
|PIN 1.|VIN|PIN 1.|GND|PIN 1.||ILIMIT|PIN 1.|SW_TO_GND|
|2.|N/C|2.|dv/dt|2.||OVLO|2.|DASIC_OFF|
|3.|REXT|3.|ENABLE|3.||UVLO|3.|DASIC_SW_DET|
|4.|GND|4.|ILIMIT|4.||INPUT+|4.|GND|
|5.|IOUT|5.|SOURCE|5.||SOURCE|5.|V_MON|
|6.|IOUT|6.|SOURCE|6.||SOURCE|6.|VBULK|
|7.|IOUT|7.|SOURCE|7.||SOURCE|7.|VBULK|
|8.|IOUT|8.|VCC|8.||DRAIN|8.|VIN|
|STYLE 29:||STYLE 30:|||||||
|PIN 1.|BASE, DIE #1|PIN 1.|DRAIN 1||||||
|2.|EMITTER, #1|2.|DRAIN 1||||||
|3.|BASE, #2|3.|GATE 2||||||
|4.|EMITTER, #2|4.|SOURCE 2||||||
|5.|COLLECTOR, #2|5.|SOURCE 1/DRAIN 2||||||
|6.|COLLECTOR, #2|6.|SOURCE 1/DRAIN 2||||||
|7.|COLLECTOR, #1|7.|SOURCE 1/DRAIN 2||||||
|8.|COLLECTOR, #1|8.|GATE 1||||||



Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42564B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SOIC−8 NB PAGE 2 OF 2** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

**www.onsemi.com** 

~~**2**~~ 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

**TECHNICAL PUBLICATIONS** : **ONLINE SUPPORT** : www.onsemi.com/support **Technical Library:** www.onsemi.com/design/resources/technical−documentation **For additional information, please contact your local Sales Representative at onsemi Website:** www.onsemi.com www.onsemi.com/support/sales 

**==> picture [232 x 43] intentionally omitted <==**

