NCL30002DR2G.

## NCL30002 

## Power Factor Corrected Buck LED Driver 

The NCL30002 is a switch mode power supply controller intended for low to medium power single stage power factor (PF) corrected LED Drivers. The device operates as a critical conduction mode (CrM) buck controller to regulate LED current at a high power factor for a specific line voltage range. The current limit threshold is tightly trimmed allowing open loop control techniques to reduce parts count while maintaining accurate current regulation and high power factor. CrM operation is particularly suited for LED applications as very high efficiency can be achieved even at low power levels. These are important in LED lighting to comply with regulatory requirements and meet overall system luminous efficacy requirements. In CrM, the switching frequency will vary with line and load. Switching losses are low as recovery losses in the output rectifier are negligible since the current goes to zero prior to reactivating the main MOSFET switch. 

The device features a programmable on time limiter, zero current detect sense block, gate driver, trans−conductance error amplifier as well as all PWM control circuitry and protection functions required to implement a CrM switch mode power supply. Moreover, for high efficiency, the device features low startup current enabling fast, low loss charging of the VCC capacitor. The current sense protection threshold has been set at 485 mV to minimize power dissipation in the external sense resistor. To support the environmental operation range of Solid State Lighting, the device is specified across a wide junction temperature range of −40°C to 125°C. 

- | 

## **Features** 

- Very Low 24 A Typical Startup Current 

- Cycle−by−Cycle Current Protection 

- Tightly Trimmed Low Current Sense Threshold of 485 mV ±2% 

- Low 2 mA Typical Operating Current 

- Source 500 mA / Sink 800 mA Totem Pole Gate Driver 

## **http://onsemi.com** 

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MARKING<br>8 DIAGRAM<br>1 8<br>SOIC−8 L0002<br>D SUFFIX ALYW<br>CASE 751<br>1<br>A = Assembly Location<br>L = Wafer Lot<br>Y = Year<br>W = Work Week<br>= Pb−Free Package<br>PIN CONNECTION<br>MFP VCC<br>Comp DRV<br>Ct GND<br>CS ZCD<br>(Top View)<br>ORDERING INFORMATION<br>Device Package Shipping [†]<br>NCL30002DR2G SOIC−8 2500 / Tape & Reel<br>(Pb−Free)<br>Pf<br>†For information on tape and reel specifications,<br>including part orientation and tape sizes, please<br>refer to our Tape and Reel Packaging Specifications<br>Brochure, BRD8011/D.<br>**----- End of picture text -----**<br>


- Wide Operating Temperature Range 

- Enable Function and Overvoltage Protection 

- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 

## **Typical Applications** 

- LED Driver Power Supplies 

- LED Based Bulbs 

- Commercial and Residential LED Fixtures 

Publication Order Number: **NCL30002/D** 

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© Semiconductor Components Industries, LLC, 2012 **March, 2012 − Rev. 0** 

**NCL30002** 

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OVP<br>+<br>+ −<br>VOVP<br>− UVP<br>+ +<br>VUVP<br>(Enable EA)<br>MFP E/A −<br>+<br>gm<br>RMFP +<br>VREF<br>VCC<br>VCC<br>Fault Management<br>VControl<br>COMP<br>VEAH<br>Clamp<br>� VDD VDD<br>Power Good<br>VDD<br>PWM<br>Ct 270  � A* Add CtOffset + −<br>S Q<br>DRV<br>OCP R Q<br>CS LEB +<br>195 ns* − VCC<br>+<br>VILIM<br>+ S Q Demag S Q DRV<br>−<br>+<br>ZCD VZCD(ARM) R Q R Q<br>+<br>Reset<br>− � VDD<br>+<br>VZCD(TRIG) 180  � s* S Q<br>Off Timer<br>R Q<br>GND<br>ZCD<br>Clamp<br>* Typical Values Shown All SR Latches are Reset Dominant<br>**----- End of picture text -----**<br>


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Figure 1. Block Diagram<br>**----- End of picture text -----**<br>


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**NCL30002** 

## **Table 1. PIN FUNCTION DESCRIPTION** 

|**Pin**|**Name**|**Function**|
|---|---|---|
|1|MFP|The multi−function pin is connected to the internal error amplifier. By pulling this pin below the Vuvpthreshold, the<br>controller is disabled. In addition, this pin also has an over voltage comparator which will disable the controller in the<br>event of a fault.|
|2|COMP|The COMP pin is the output of the internal error amplifier. A compensation network connected between this pin and<br>ground sets the loop bandwidth.|
|3|Ct|The Ctpin sources a regulated current to charge an external timing capacitor. The PWM circuit controls the power<br>switch on time by comparing the Ctvoltage to an internal voltage derived from VControl. The CTpin discharges the<br>external timing capacitor at the end of the on time cycle.|
|4|CS|The CS input threshold is precisely trimmed to accurately sense the instantaneous switch current in the external<br>MOSFET. This signal is conditioned by an internal leading edge blanking circuit. The current limit threshold is tightly<br>trimmed for precise peak current control.|
|5|ZCD|The voltage of an auxiliary zero current detection winding is sensed at this pin. When the ZCD control block circuit<br>detects that the winding current has gone to zero, a control signal is sent to the gate drive block to turn on the<br>external MOSFET.|
|6|GND|This is the analog ground for the device. All bypassing components should be connected to the GND pin with a short<br>trace length.|
|7|DRV|The high current capability of the totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate<br>charge power MOSFETs. The driver stage provides both passive and active pull down circuits that force the output to<br>a voltage less than the turn−on threshold voltage of the power MOSFET when VCC(on)is not reached.|
|8|VCC|This pin is the positive supply of the controller. The circuit starts to operate when VCCexceeds VCC(on), nominally<br>12 V and turns off when VCCgoes below VCC(off), typically 9.5 V. After startup, the operating range is 10.2 V up to<br>20 V.|



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**NCL30002** 

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EMI Filter/ Rectifier / Surge Suppression Start−up Resistors HVDC Filter Caps Output Filter Cap<br>AC1 F1 Lemi1 L4<br>LED +<br>RV1 AC1 + C6 C4 Dovp<br>MOV AC2 − Rstart Dbuck Cout<br>OVP Zener<br>AC2 D4<br>Lemi2 LED −<br>Dvcc<br>Lout<br>R15<br>Rtop<br>Cvcc<br>Rin 12 MFPU1 Vcc [8] Vcc Bootstrap Qbuck<br>Rfb 34 CompCTCS GNDDRVZCD [7][6][5] Rzcd Rgdrv<br>NCL30002<br>ZCD<br>Ct<br>Cfilter Rbottom Ccomp Current Sense<br>R8<br>R2 (Optional) Rsense<br>Feed Forward Compensation On Time Capacitor<br>**----- End of picture text -----**<br>


**Figure 2. Simplified PFC Buck Application** 

## **Overview** 

Figure 2 illustrates the basic NCL30002 architecture for a non-isolated low power high power factor LED driver. One of the notable features of this architecture is the open loop control. Notice that there is no direct measurement of the LED current. Tight peak current control coupled with line feed-forward compensation to vary the on-time allows for accurate LED drive current. Fortunately in the vast majority of LED bulb and luminaire applications, the LED forward voltage range is well bounded and the line voltage may be limited to one operating range. This is a huge advantage which makes the simplicity of open loop control possible. 

Buck switching on the low side eliminates a floating gate drive but references the LED to the HV rail. Buck converters only produce output when the input voltage exceeds the load voltage. Consequently, the input current goes to zero near the zero crossing of the line. The exact phase angle of this event depends on the LED string voltage and the line voltage. Unlike the boost PFC, the buck PFC has increased distortion near the zero crossing. However even with cross over distortion, high power factor and acceptable harmonics can be achieved. 

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**NCL30002** 

## **Table 2. MAXIMUM RATINGS** 

|**Table 2. MAXIMUM RATINGS**||||
|---|---|---|---|
|**Rating**|**Symbol**|**Value**|**Unit**|
|MFP Voltage|VMFP|−0.3 to 10|V|
|MFP Current|IMFP|±10|mA|
|COMP Voltage|VControl|−0.3 to 6.5|V|
|COMP Current|IControl|−2 to 10|mA|
|Ct Voltage|VCt|−0.3 to 6|V|
|Ct Current|ICt|±10|mA|
|CS Voltage|VCS|−0.3 to 6|V|
|CS Current|ICS|±10|mA|
|ZCD Voltage|VZCD|−0.3 to 10|V|
|ZCD Current|IZCD|±10|mA|
|DRV Voltage|VDRV|−0.3 to VCC|V|
|DRV Sink Current|IDRV(sink)|800|mA|
|DRV Source Current|IDRV(source)|500|mA|
|Supply Voltage|VCC|−0.3 to 20|V|
|Supply Current|ICC|±20|mA|
|Power Dissipation (TA= 70°C, 2.0 Oz Cu, 55 mm2Printed Circuit Copper Clad)|PD|450|mW|
|Thermal Resistance Junction−to−Ambient<br>(2.0 Oz Cu, 55 mm2Printed Circuit Copper Clad)<br>Junction−to−Air, Low conductivity PCB (Note 3)<br>Junction−to−Air, High conductivity PCB (Note 4)|R�JA<br>R�JA<br>R�JA|178<br>168<br>127|°C/W|
|Operating Junction Temperature Range|TJ|−40 to 125|°C|
|Maximum Junction Temperature|TJ(MAX)|150|°C|
|Storage Temperature Range|TSTG|−65 to 150|°C|
|Lead Temperature (Soldering, 10 s)|TL|300|°C|



Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 

1. This device series contains ESD protection and exceeds the following tests: Pins 1– 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E. Pins 1– 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A. 

2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78. 

3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm[2] of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow. 

4. As mounted on a 40 x 40 x 1.5 mm FR4 substrate with a single layer of 650 mm[2] of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow. 

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**NCL30002** 

**Table 3. ELECTRICAL CHARACTERISTICS** 

VMFP = 2.4 V, VControl = 4 V, Ct = 1 nF, VCS = 0 V, VZCD = 0 V, CDRV = 1 nF, VCC = 12 V, unless otherwise specified (For typical values, TJ = 25 ° C. For min/max values, TJ = −40 ° C to 125 ° C, unless otherwise specified) 

|**Characteristic**|**Test Conditions**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**STARTUP AND SUPPLY CIRCUITS**|||||||
|Startup Voltage Threshold|VCCIncreasing|VCC(on)|11|12|12.5|V|
|Minimum Operating Voltage|VCCDecreasing|VCC(off)|8.8|9.5|10.2|V|
|Supply Voltage Hysteresis||HUVLO|2.2|2.5|2.8|V|
|Startup Current Consumption|0 V < VCC< VCC(on)− 200 mV|Icc(startup)|−|24|35|�A|
|No Load Switching<br>Current Consumption|CDRV= open, 70 kHz Switching,<br>VCS= 2 V|Icc1|−|1.4|1.7|mA|
|Switching Current Consumption|70 kHz Switching, VCS= 2 V|Icc2|−|2.1|2.6|mA|
|Fault Condition Current Consumption|No Switching, VMFP= 0 V|Icc(fault)|−|0.75|0.95|mA|
|**OVERVOLTAGE AND UNDERVOLTAGE PROTECTION**|||||||
|Overvoltage Detect Threshold|VMFP= Increasing|VOVP|2.5|2.67|2.85|V|
|Overvoltage Hysteresis||VOVP(HYS)|20|60|100|mV|
|Overvoltage Detect Threshold<br>Propagation Delay|VMFP= 1 V to 3 V step,<br>VMFP= VOVPto VDRV= 10%|tOVP|−|500|800|ns|
|Undervoltage Detect Threshold|VMFP= Decreasing|VUVP|0.25|0.31|0.4|V|
|Undervoltage Detect Threshold<br>Propagation Delay|VMFP= 2 V to 0 V step,<br>VMFP= VUVPto VDRV= 10%|tUVP|80|200|320|ns|
|**ERROR AMPLIFIER**|||||||
|Voltage Reference|TJ= 25°C<br>TJ= −40°C to 125°C|VREF|2.397<br>2.359|2.510<br>2.510|2.623<br>2.661|V|
|Voltage Reference Line Regulation|VCC(on)+ 200 mV < VCC< 20 V|VREF(line)|−10|−|10|mV|
|Error Amplifier Current Capability|VMFP= VREF+ 0.11 V<br>VMFP= 1.08*VREF<br>VMFP= 0.5 V|IEA(sink)<br>IEA(sink)OVP<br>IEA(source)|6<br>10<br>−110|10<br>20<br>−210|20<br>30<br>−250|�A|
|Transconductance|VMFP= VREF ±100 mV<br>TJ= 25°C<br>TJ= −40°C to 125°C|gm|90<br>70|110<br>110|120<br>135|�S|
|Feedback Pin Internal Pull−Down<br>Resistor|VMFP= VUVPto VREF|RMFP|2|4.6|10|M�|
|Feedback Bias Current|VMFP= 2.5 V|IMFP|0.25|0.54|1.25|�A|
|Control Bias Current|VMFP= 0 V|IControl|−1|−|1|�A|
|Maximum Control Voltage|IControl(pullup)= 10�A,<br>VMFP= VREF|VEAH|5|5.5|6|V|
|Minimum Control Voltage to Generate<br>Drive Pulses|VControl= Decreasing until<br>VDRVis low, VCt= 0 V|Ct(offset)|0.37|0.65|0.88|V|
|Control Voltage Range|VEAH– Ct(offset)|VEA(DIFF)|4.5|4.9|5.3|V|



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**NCL30002** 

**Table 3. ELECTRICAL CHARACTERISTICS** (Continued) 

VMFP = 2.4 V, VControl = 4 V, Ct = 1 nF, VCS = 0 V, VZCD = 0 V, CDRV = 1 nF, VCC = 12 V, unless otherwise specified (For typical values, TJ = 25 ° C. For min/max values, TJ = −40 ° C to 125 ° C, unless otherwise specified) 

|(For typical values, TJ= 25°C. For min/m|<br>ax values, TJ= −40°C to 125°C, unless|<br>otherwise spe|<br>cified)||||
|---|---|---|---|---|---|---|
|**Characteristic**|**Test Conditions**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**RAMP CONTROL**|||||||
|Ct Peak Voltage|VCOMP= open|VCt(MAX)|4.535|4.93|5.25|V|
|On Time Capacitor Charge Current|VCOMP= open<br>VCt= 0 V to VCt(MAX)|Icharge|240|270|292|�A|
|Ct Capacitor Discharge Duration|VCOMP= open<br>VCt= VCt(MAX)−100 mV to 500 mV|tCt(discharge)|−|50|150|ns|
|PWM Propagation Delay|dV/dt = 30 V/�s<br>VCt= VControl− Ct(offset)<br>to VDRV= 10%|tPWM|−|130|220|ns|
|**ZERO CURRENT DETECTION**|||||||
|ZCD Arming Threshold|VZCD= Increasing|VZCD(ARM)|1.25|1.4|1.55|V|
|ZCD Triggering Threshold|VZCD= Decreasing|VZCD(TRIG)|0.6|0.7|0.83|V|
|ZCD Hysteresis||VZCD(HYS)|500|700|900|mV|
|ZCD Bias Current|VZCD= 5 V|IZCD|− 2|−|+ 2|�A|
|Positive Clamp Voltage|IZCD= 3 mA|VCL(POS)|9.8|10|12|V|
|Negative Clamp Voltage|IZCD= −2 mA|VCL(NEG)|−0.9|−0.7|−0.5|V|
|ZCD Propagation Delay|VZCD= 2 V to 0 V ramp,<br>dV/dt = 20 V/�s<br>VZCD= VZCD(TRIG)to VDRV= 90%|tZCD|−|100|170|ns|
|Minimum ZCD Pulse Width||tSYNC|−|70|−|ns|
|Maximum Off Time in Absence of ZCD<br>Transition|Falling VDRV= 10% to<br>Rising VDRV= 90%|tstart|75|165|300|�s|
|**DRIVE**|||||||
|Drive Resistance|Isource= 100 mA<br>Isink= 100 mA|ROH<br>ROL|−<br>−|12<br>6|20<br>13|�|
|Rise Time|10% to 90%|trise|−|35|80|ns|
|Fall Time|90% to 10%|tfall|−|25|70|ns|
|Drive Low Voltage|VCC= VCC(on)−200 mV,<br>Isink= 10 mA|Vout(start)|−|−|0.2|V|
|**CURRENT SENSE**|||||||
|Current Sense Voltage Threshold|TJ= 25°C<br>TJ= −40°C to 125°C|VILIM|0.475<br>0.470|0.485<br>0.485|0.495<br>0.500|V|
|Leading Edge Blanking Duration|VCS= 2 V, VDRV= 90% to 10%|tLEB|100|195|350|ns|
|Overcurrent Detection Propagation<br>Delay|dV/dt = 10 V/�s<br>VCS= VILIMto VDRV= 10%|tCS|40|100|170|ns|
|Current Sense Bias Current|VCS= 2 V|ICS|−1|−|1|�A|



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**NCL30002** 

## **TYPICAL CHARACTERISTICS** 

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2.85 80<br>2.80<br>70<br>2.75<br>2.70<br>60<br>2.65<br>2.60<br>50<br>2.55<br>2.50 40<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 3. Overvoltage Detect Threshold vs. Figure 4. Overvoltage Hysteresis vs. Junction<br>Junction Temperature Temperature<br>0.325<br>7<br>6<br>0.320<br>5<br>0.315<br>4<br>3<br>0.310<br>2<br>0.305<br>1<br>0.300 0<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>ESIS (mV)<br>THRESHOLD (V) , OVERVOLTAGE HYSTER-<br>, OVERVOLTAGE DETECT<br>OVP<br>V<br>OVP(HYS)<br>V<br>) �<br>DOWN RESISTOR (M<br>, FEEDBACK PIN INTERNAL PULL−<br>MFP<br>, UNDERVOLTAGE DETECT THRESHOLD (V) R<br>UVP<br>V<br>**----- End of picture text -----**<br>


**Figure 5. Undervoltage Detect Threshold vs. Junction Temperature** 

**Figure 6. MFP Pin Internal Pull−Down Resistor vs. Junction Temperature** 

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2.54<br>2.53<br>2.52<br>2.51<br>2.50<br>2.49<br>2.48<br>2.47<br>2.46<br>−50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>, REFERENCE VOLTAGE (V)<br>REF<br>V<br>**----- End of picture text -----**<br>


**Figure 7. Reference Voltage vs. Junction Temperature** 

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**NCL30002** 

## **TYPICAL CHARACTERISTICS** 

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20 220<br>VMFP = VREF + 0.11 V<br>18 215<br>16 210<br>205<br>14<br>200<br>12<br>195<br>10<br>190<br>8 VMFP = 0.5 V<br>185<br>6 180<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 8. Error Amplifier Sink Current vs. Figure 9. Error Amplifier Source Current vs.<br>Junction Temperature Junction Temperature<br>125 200 200<br>180 180<br>120<br>Phase<br>160 160<br>115<br>140 140<br>110<br>120 Transconductance 120<br>105 100 100<br>80 80<br>100<br>RControl = 100 k �<br>95 60 CControl = 2 pF 60<br>40 VMFP = 2.5 Vdc, 1 Vac 40<br>90 VCC = 12 V<br>20 TA = 25 ° C 20<br>85 0 0<br>−50 −25 0 25 50 75 100 125 0.01 0.1 1 10 100 1000<br>TJ, JUNCTION TEMPERATURE ( ° C) f, FREQUENCY (kHz)<br>Figure 10. Error Amplifier Transconductance Figure 11. Error Amplifier Transconductance<br>vs. Junction Temperature and Phase vs. Frequency<br>1.0 290<br>285<br>0.9<br>280<br>0.8 275<br>270<br>0.7<br>265<br>0.6<br>260<br>0.5 255<br>250<br>0.4<br>245<br>0.3 240<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>A)<br>�<br>A)<br>�<br>, ERROR AMPLIFIER<br>CURRENT (<br>, ERROR AMPLIFIER SINK<br>SOURCE CURRENT (<br>IEA(source)<br>IEA(sink)<br>S)<br>� S)<br>�<br>�<br>, PHASE (DEGREES)<br>gm, ERROR AMPLIFIER TRANSCONDUCTANCE (<br>gm, ERROR AMPLIFIER TRANSCONDUCTANCE (<br>A)<br>�<br>, Ct CHARGE CURRENT (<br>, MINIMUM CONTROL VOLTAGE<br>(offset) TO GENERATE DRIVE PULSES (V) Icharge<br>Ct<br>**----- End of picture text -----**<br>


**Figure 12. Minimum Control Voltage to Generate Drive Pulses vs. Junction Temperature** 

**Figure 13. On Time Capacitor Charge Current vs. Junction Temperature** 

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**NCL30002** 

## **TYPICAL CHARACTERISTICS** 

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6.0 170<br>160<br>5.5<br>150<br>140<br>5.0<br>130<br>120<br>4.5<br>110<br>4.0 100<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 14. Ct Peak Voltage vs. Junction Figure 15. PWM Propagation Delay vs.<br>Temperature Junction Temperature<br>500 220<br>497<br>494<br>210<br>491<br>488<br>485 200<br>482<br>479<br>190<br>476<br>473<br>470 180<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 16. Current Sense Voltage Threshold Figure 17. Leading Edge Blanking Duration vs.<br>vs. Junction Temperature Junction Temperature<br>205 18<br>200 16<br>14 ROH<br>195<br>12<br>190<br>10<br>185<br>8<br>180<br>6 ROL<br>175<br>4<br>170 2<br>165 0<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>, Ct PEAK VOLTAGE (V)<br>Ct(MAX) , PWM PROPAGATION DELAY (ns)<br>V tPWM<br>DURATION (ns)<br>, LEADING EDGE BLANKING<br>tLEB<br>, CURRENT SENSE VOLTAGE THRESHOLD (mV)<br>ILIM<br>V<br>s)<br>�<br>) �<br>, MAXIMUM OFF TIME IN AB- DRIVE RESISTANCE (<br>tstart SENCE OF ZCD TRANSITION (<br>**----- End of picture text -----**<br>


**Figure 18. Maximum Off Time in Absence of ZCD Transition vs. Junction Temperature** 

**Figure 19. Drive Resistance vs. Junction Temperature** 

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**NCL30002** 

## **TYPICAL CHARACTERISTICS** 

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13 26<br>12 VCC(on) 24<br>22<br>11<br>20<br>10<br>VCC(off) 18<br>9<br>16<br>8 14<br>−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 20. Supply Voltage Thresholds vs. Figure 21. Startup Current Consumption vs.<br>Junction Temperature Junction Temperature<br>2.16<br>2.14<br>2.12<br>2.10<br>2.08<br>2.06<br>2.04<br>2.02<br>2.00<br>−50 −25 0 25 50 75 100 125<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>A)<br>�<br>, STARTUP CURRENT<br>, SUPPLY VOLTAGE<br>THRESHOLDS (V)<br>CC CONSUMPTION (<br>V<br>ICC(startup)<br>SUMPTION (mA)<br>, SWITCHING CURRENT CON-<br>ICC2<br>**----- End of picture text -----**<br>


**Figure 22. Switching Current Consumption vs. Junction Temperature** 

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**NCL30002** 

## **THEORY OF OPERATION** 

High power factor, high efficiency, and small size are key parameters for LED drivers in the incandescent replacement market. The NCL30002 has all the features required to accomplish that is in a compact SOIC-8 package. Power factor is broadly defined as: 

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This differs from the classical definition where there is a phase angle difference between the input voltage and current. However, the underlying concept of optimizing power delivery by minimizing line current is the same. Ideally, current would be directly proportional to the voltage which is the case when the load is a resistor. Offline power converters are active devices which are not purely resistive, capacitive, or inductive often drawing distorted current waveforms from the power lines. This distortion reduces power factor by increasing input RMS current. Preregulators using boost converters are the most common method to correcting the distortion and making the offline power supply appear to be a resistor as far as the power line is concerned. Their performance is excellent achieving power factor greater than 0.99. Regrettably, this two stage approach negatively impacts efficiency and board area. Fortunately, power factors greater than 0.9 are acceptable in the general lighting market and in some applications like US Energystar Integral LED bulbs, the minimum acceptable 

power factor is 0.7. So a certain amount of distortion can be accepted while maintaining high power factor. This buck topology meets the requirements for PF greater than 0.9 and regulate LED current in a single power stage. Unlike the boost converter, the NCL30002 buck controller operates in several different modes over the line cycle. 

## **Buck Modes** 

1. “Zero” Input Current (Iin=0) - Buck converters cannot deliver power when Vin is less than Vout. The “dead time” where no current flows around the zero crossing is dependent on the line voltage and the load voltage. 

2. Constant On-Time (Ton = constant) - This is the same as the boost converter. Constant Ton forces the peak current to be proportional to the input voltage which is key to improved PF. 

3. Constant Peak Current (Ipeak = constant) – The NCL30002 limits the peak inductor and thus the LED current. In this region, the unique nature of the CrM buck means that the average output current is equal to half the peak current. Also the off time is fixed is this mode since the peak current and the output voltage are virtually constant. 

In the example below (Figure 23) in spite of the distortion, the power factor is 0.97. The corresponding pre-filtered output current is shown in Figure 24. 

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Mode 3 Ipeak = Constant<br>Mode 2 ton = Constant<br>Mode 1 Input Current = 0<br>**----- End of picture text -----**<br>


**Figure 23. Theoretical Average Input Current over one half line cycle (conduction angle)** 

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**NCL30002** 

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**----- Start of picture text -----**<br>
Mode 3 Ipeak = Constant<br>Mode 2 ton = Constant<br>Mode 1 Input Current = 0<br>**----- End of picture text -----**<br>


**Figure 24. Theoretical Average Output Current over one half line cycle (conduction angle)** 

An output capacitor filters the output current in the LED string. The dynamic LED resistance, line frequency, and the size of the filter capacitance determine the exact LED ripple. 

The NCL30002 operates as a CrM controller. The controller draws very low currents while the Vcc filter capacitor charges to the start-up threshold. Since CrM operation is not clocked at a fixed frequency and depends on the state of the power circuit to initiate a new switching cycle, a kick start timer turns on the gate driver to start a new cycle. The kick start timer will do this anytime the driver is off for more than about 180 sec as long as none of the Wu protection circuits are disabling the gate driver output. 

The NCL30002 (refer to the block diagram − Figure 1) is composed of 4 key functional blocks along with protection circuitry to ensure reliable operation of the controller. 

- On−Time Control 

## **On Time Control** 

The on−time control circuitry (Figure 25) consists of a precision current source which charges up an external capacitor (Ct) in a linear ramp. The voltage on Ct (after removing an internal offset) is compared to an external control voltage and the output of the comparator is used to turn off the output driver thus terminating the switching cycle. A signal from the driver is fed back to the on−time control block to discharge the Ct capacitor thus preparing the circuit for the start of the next switching cycle. 

The state of Vcontrol is determined by the external regulation loop. The range of on−time is determined by the charging slope of the Ct capacitor and is clamped at 4.93 V nominal. The Ct capacitor is sized to ensure that the required on−time is reached at maximum output power and the minimum input line voltage condition. 

- Zero Current Detection Control 

- MOSFET Gate Driver 

- Startup and VCC Management 

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**NCL30002** 

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VControl<br>COMP<br>VDD VEAH<br>Ct Icharge PWM−<br>+ + ton<br>DRV<br>Ct(offset)<br>VCt<br>VControl − Ct(offset)<br>VCt(off)<br>VControl<br>t on(ma x)<br>DRV<br>**----- End of picture text -----**<br>


**Figure 25. On Time Control** 

## **Off Time Sequence** 

The off time is determined by the peak inductor current, the inductance and the output voltage. In mode 2, the off time is variable because the peak inductor current is not fixed. However in mode 3, the off time is constant since the peak current and the output voltage are both fixed. The auxiliary winding used to provide bias to the NCL30002 is also used to detect when the current has dropped to zero. This is illustrated in Figure 26. 

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MOSFET Conduction<br>Output Rectifier Conduction<br>Iprimary 0 A<br>Isecondary 0 A<br>DRV<br>0 V<br>Vout<br>0 V<br>VZCD(WIND)<br>VZCD(WIND),off<br>0 V<br>VZCD(WIND),on<br>VCL(POS)<br>VZCD(ARM)<br>VZCD(TRIG)<br>0 V<br>VCL(NEG)<br>ton tdiode<br>toff<br>tSW<br>**----- End of picture text -----**<br>


**Figure 26. Ideal CrM Waveforms with ZCD Winding** 

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**NCL30002** 

## **ZCD Detection Block** 

A dedicated circuit block is necessary to implement the zero current detection **.** The NCL30002 provides a separate input pin to signal the controller to turn the power switch back on just after inductor current reaches zero. When the output winding current reaches zero the winding voltage will reverse. Since all windings of the inductor reflect the same voltage characteristic this voltage reversal appears on the bias winding. Coupling the winding voltage to the ZCD input of the NCL30002 allows the controller to start the next switching cycle at the precise time. To avoid false triggering, 

the ZCD input has a dual comparator input structure to arm the latch when the ZCD detect voltage rises above 1.4 V (nominal) thus setting the latch. When the voltage on ZCD falls below 0.7 V (nominal) a zero current event is detected and a signal is asserted which initiates the next switching cycle. This is illustrated in Figure 27. The input of the ZCD has an internal circuit which clamps the positive and negative voltage excursions on this pin. The current into or out of the ZCD pin must be limited to ±10 mA with an external resistor. 

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Varm Vtrig NZCD<br>+ Demag<br>− SResetQ<br>VZCD(ARM) DominantLatch<br>+ DRIVE R Q<br>−<br>VZCD(TRIG)<br>ZCD<br>Bias Winding Voltage<br>RZCD<br>ZCD Clamp<br>+<br>+<br>**----- End of picture text -----**<br>


**Figure 27. ZCD Operation** 

At startup, there is no energy in the ZCD winding and no voltage signal to activate the ZCD comparators. To enable the controller to start under these conditions, an internal watchdog timer is provided which initiates a switching cycle in the event that the output drive has been off for more than 180 �s (nominal). 

The timer is deactivated only under an OVP or UVP fault condition which will be discussed in the next section. 

## **CS** 

The dedicated CS pin of the NCL30002 senses the current through the MOSFET switch and the output inductor. If the voltage of the CS pin exceeds VILIM, the internal comparator will detect the event and turn off the MOSFET. The peak switch current is calculated using Equation 1: 

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To avoid false detection, the NCL30002 incorporates leading edge blanking circuit (LEB) which masks the CS signal for a nominal time of 190 ns. If required, an optional RC filter can be added between Rsense and CS to provide additional filtering. This is illustrated below. 

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CS<br>DRV LEB  + OCP<br>−<br>VILIM<br>Rsense optional<br>+<br>**----- End of picture text -----**<br>


**Figure 28. CS Circuitry with Optional External RC Filter** 

## **MFP Input** 

The multi−function pin connects to the inverting terminal of the transconductance amplifier, the undervoltage and overvoltage protection comparators. This allows this pin to perform several functions. To place the device in standby, the MFP pin should be pulled below the Vuvp threshold. This is illustrated in Figure 29. Additionally, raising the MFP pin above Vovp will also suspend switching activity but not place the controller in the standby mode. This can be used implement overvoltage monitoring on the bias winding and add an additional layer of fault protection. 

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**NCL30002** 

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**----- Start of picture text -----**<br>
+ OVP<br>− OVP Fault<br>VOVP POWER GOOD<br>Bias<br>+− UVP UVP Fault<br>R1 VUVP<br>MFP − EA (Enable EA)<br>+<br>RFB gm<br>Shutdown R2 VREF<br>COMP VControl<br>CCOMP<br>+<br>+<br>+<br>**----- End of picture text -----**<br>


**Figure 29. Multi−Function Pin Operation** 

The positive input of the transconductance amplifier is connected to a 2.51 V (nominal) reference. A filtered line feed-forward signal (see Figure 2) is connected to the negative input of the error amplifier and used to control the on-time of controller. 

## **VCC Management** 

The NCL30002 incorporates a supervisory circuitry to manage the startup and shutdown of the circuit. By managing the startup and keeping the initial startup current at less than 35 �A, a startup resistor connected between the rectified ac line and VCC charges the VCC capacitor to VCC(on). Turn on of the device occurs when the startup voltage has exceeded 12 V (nominal) when the internal reference and switching logic are enabled. A UVLO comparator with a hysteresis of 2.5 V nominal gives ample time for the device to start switching and allow the bias from the auxiliary winding to supply VCC. 

## **Design Tool** 

The NCL30002 implements a unique control method to achieve high power and superior current regulation even though the average current is not directly sensed. There are a number of design tradeoffs that can be made between peak switch current, inductor size, and desired power factor that can impact the current regulation accuracy, efficiency, and physical size. These tradeoffs can be made by adjusting the amount of line feed forward applied, selecting the amount of time where the controller is operating in mode 2 and 3, as well as factoring in the LED forward voltage range. To simplify the component selection process and allow the designer to interactively make these tradeoffs, ON Semiconductor has developed an EXCEL� based Design Guide which allows step-by-step analysis. This tool is available at onsemi.com along with a supporting application note that illustrates a complete design and provides typical application performance. 

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**NCL30002** 

## **PACKAGE DIMENSIONS** 

**SOIC−8 NB** CASE 751−07 ISSUE AK 

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1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 

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−X− 1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>et 5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>−Y− 4 K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEWMAXIMUM MATERIAL CONDITION.<br>STANDARD IS 751−07.<br>7 G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>C N X 45 A 4.80 5.00 0.189 0.197<br>B 3.80 4.00 0.150 0.157<br>SEATING<br>PLANE C 1.35 1.75 0.053 0.069<br>−Z− D 0.33 0.51 0.013 0.020<br>G 1.27 BSC 0.050 BSC<br>0.10 (0.004) H 0.10 0.25 0.004 0.010<br>=S H SL D Rya M p J == KJ 0.400.19 1.270.25 0.0160.007 0.0500.010<br>M 0  8  0  8<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244<br>**----- End of picture text -----**<br>


5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 

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SOLDERING FOOTPRINT*<br>**----- End of picture text -----**<br>


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1.52<br>0.060<br>7.0 4.0<br>0.275 ma 0.155<br>0.6 1.270<br>0.024 0006 0.050<br>SCALE 6:1 mm<br>inches<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


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