NCL30001DR2G

## NCL30001 

## High-Efficiency Single Stage Power Factor Correction and Step-Down Offline LED Driver 

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The NCL30001 is a highly integrated controller for implementing power factor correction (PFC) and isolated step down ac−dc power conversion in a single stage, resulting in a lower cost and reduced part count solution. This controller is ideal for LED Driver power supplies with power requirements between 40 W and 150 W. The single stage is based on the flyback converter and it is designed to operate in continuous conduction (CCM). 

The NCL30001 can be configured as as constant current driver or a fixed output driver for two stage LED lighting applications. In addition, the controller features a proprietary Soft−Skip™ to reduce acoustic noise at light loads. Other features found in the NCL30001 include a high voltage startup circuit, voltage feedforward, brown out detector, internal overload timer, latch input and a high accuracy multiplier. The multi−function latch off pin can also be used to implement an overtemperature shutdown circuit. 

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MARKING<br>DIAGRAM<br>HAH A A A A E<br>NCL30001G<br>AWLYWW<br>Rs —<br>TO H UAH A HA S<br>SOIC−16<br>D SUFFIX<br>CASE 751B<br>A = Assembly Location<br>WL = Wafer Lot<br>YY = Year<br>WW = Work Week<br>G = Pb−Free Package<br>**----- End of picture text -----**<br>


## **Features** 

- Voltage Feedforward Improves Loop Response 

- Frequency Jittering Reduces EMI Signature 

- Proprietary Soft−Skip at Light Loads Reduces Acoustic Noise 

- Brown Out Detector 

- Internal 160 ms Fault Timer 

- Independent Latch−Off Input Facilitates Implementation of Overvoltage and Overtemperature Fault Detectors 

- Average Current Mode Control (ACMC), Fixed Frequency Operation 

- High Accuracy Multiplier Reduces Input Line Harmonics 

- Adjustable Operating Frequency from 20 kHz to 250 kHz 

- These Devices are Pb−Free and are RoHS Compliant 

## **Typical Applications** 

## **PIN CONNECTIONS** 

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Ramp CompCT LT| 21 -= 1516 StartupGND<br>AC IN | 3 = 14 NC<br>FB | 4 = 13 DRV<br>VFF | 5 = 12 VCC<br>CM 6 11 Ispos<br>AC COMP LT 7 = 10 Iavg<br>Latch−Off LT| 8 == 9 TEST<br>(Top View )<br>**----- End of picture text -----**<br>


- LED Street Lights 

- Low Bay LED Lighting 

- High Power LED Drivers 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 30 of this data sheet. 

- Architectural LED Lighting 

Publication Order Number: **NCL30001/D** 

**1** 

© Semiconductor Components Industries, LLC, 2015 **February, 2015 − Rev. 1** 

**NCL30001** 

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FB overload Overload<br>Jitter comparator Timer<br>FB + tOVLD<br>+ − Enable S<br>CT Adj. Jitter VOVLD RQ OVLD<br>Oscillator Clock Startup<br>VFF Brown−Out Enable<br>DC Max DC Max Comparator Out x 2<br>Sawtooth VFF +− Resetcounter<br>+<br>Dual HV<br>VBO BO current sourcestart−up<br>Ramp. Comp. Ramp Comp<br>Adj. VCC(off) HV current<br>Reset Reset VCC GND<br>RampComp AC In skip VCC OK Start ManagementVDD<br>comparator<br>+<br>+ −<br>VDD<br>VDD VSSKIP(sync)<br>Clock<br>Soft−skip Ramp<br>RFB ComparatorFB skip Delay DC Max<br>+ tSSKIP<br>+ − StartTerminate<br>VSSKIP<br>Transient Load Detect<br>+ Comparator<br>AC IN − S<br>+ + Q DRV<br>VSSKIP(TLD) Ramp Comp − R OutputDriver<br>FB V−to−I PWM Skip<br>21.33k � Comparator<br>FB V−to−I<br>Reference<br>Generator +− gm + inverterV−to−I +<br>AC error − PWM VCC<br>VFF VFF Amplifier comparator<br>21.33k �<br>+<br>4V OVLD BO<br>CM Latch VCCOK<br>BlankingtLEB gm Ispos<br>AC COMP<br>Current sense<br>amplifier<br>VDD OVP Comparator<br>+ Iavg<br>+ −<br>Ilatch(clamp) Vlatch(high)<br>blanking<br>tLatch(delay)<br>Latch−Off OTP Comparator<br>− S<br>Ilatch(shdn) + + RQ Latch TEST<br>Vlatch(low)<br>Vlatch(clamp) Reset<br>+<br>−<br>**----- End of picture text -----**<br>


**Figure 1. Detailed Block Diagram** 

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**2** 

**NCL30001** 

## **PIN FUNCTION DESCRIPTION** 

|**Pin**|**Symbol**|**Description**|
|---|---|---|
|1|CT|An external timing capacitor (CT) sets the oscillator frequency. A sawtooth between 0.2 V and 4 V sets the<br>oscillator frequency and the gain of the multiplier.|
|2|RAMP COMP|A resistor (RRC) between this pin and ground adjust the amount of ramp compensation that is added to the<br>current signal. Ramp compensation is required to prevent subharmonic oscillations. This pin should not be<br>left open.|
|3|AC IN|The scaled version of the full wave rectified input ac wave is connected to this pin by means of a resistive<br>voltage divider. The line voltage information is used by the multiplier.|
|4|FB|An error signal from an external error amplifier circuit is fed to this pin via an optocoupler or other isolation<br>circuit. The FB voltage is a proportional of the load of the converter. If the voltage on the FB pin drops be-<br>low 0.41 V (typical) the controller enters Soft−Skip to reduce acoustic noise.|
|5|VFF|Feedforward input. A scaled version of the filtered rectified line voltage is applied by means of a resistive<br>divider and an averaging capacitor. The information is used by the Reference Generator to regulate the<br>controller.|
|6|CM|Multiplier output. A capacitor is connected between this pin and ground to filter the modulated output of the<br>multiplier.|
|7|AC COMP|Sets the pole for the ac reference amplifier. The reference amplifier compares the low frequency compon-<br>ent of the input current to the ac reference signal. The response must be slow enough to filter out most of<br>the high frequency content of the current signal that is injected from the current sense amplifier, but fast<br>enough to cause minimal distortion to the line frequency information. The pin should not be left open.|
|8|Latch|Latch−Off input. Pulling this pin below 1.0 V (typical) or pulling it above 7.0 V (typical) latches the controller.<br>This input can be used to implement an overvoltage detector, an overtemperature detector or both. Refer<br>to Figure 60 for a typical implementation.|
|9|TEST|This pin is a TEST pin. A nominal 50K�10% resistor must be connected to GND for proper operation.|
|10|IAVG|An external resistor and capacitor connected from this terminal to ground, to set and stabilizes the gain of<br>the current sense amplifier output that drives the ac error amplifier.|
|11|ISpos|Positive current sense input. Connects to the positive side of the current sense resistor.|
|12|VCC|Positive input supply. This pin connects to an external capacitor for energy storage. An internal current<br>source supplies current from the STARTUP pin VCC. Once the voltage on VCCreaches approximately 15.3<br>V, the current source turns off and the outputs are enabled. The drivers are disabled once VCCreaches<br>approximately 10.2 V. If VCCdrops below 0.83 V (typical), the startup current is reduced to less than<br>500�A.|
|13|DRV|Drive output for the main flyback power MOSFET or IGBT. DRV has a source resistance of 10.8�(typical)<br>and a sink resistance of 8�(typical).|
|14|NC|No Connect|
|15|GND|Ground reference for the circuit.|
|16|HV|Connect the rectified input line voltage directly to this pin to enable the internal startup regulator. A con-<br>stant current source supplies current from this pin to the capacitor connected to the VCCpin, eliminating<br>the need for a startup resistor. The charge current is typically 5.5 mA. Maximum input voltage is 500 V.|



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**NCL30001** 

## **MAXIMUM RATINGS** (Notes 1 and 2) 

|**MAXIMUM RATINGS**(Notes 1 and 2)||||
|---|---|---|---|
|**Rating**|**Symbol**|**Value**|**Unit**|
|Start_up Input Voltage<br>Start_up Input Current|VHV<br>IHV|−0.3 to 500<br>�100|V<br>mA|
|Power Supply Input Voltage<br>Power Supply Input Current|VCC<br>ICC|−0.3 to 20<br>�100|V<br>mA|
|Latch Input Voltage<br>Latch Input Current|VLatch<br>ILatch|−0.3 to 10<br>�100|V<br>mA|
|All Other Pins Voltage<br>All Other Pins Current||−0.3 to 6.5<br>�100|V<br>mA|
|Thermal Resistance, Junction−to−Air<br>0.1 in” Copper<br>0.5 in” Copper|�JA|130<br>110|°C/W|
|Thermal Resistance, Junction−to−Lead|RΘJL|50|°C/W|
|Maximum Power Dissipation @ TA= 25°C|PMAX|0.77|W|
|Operating Temperature Range|TJ|−40 to 125|°C|
|Storage Temperature Range|TSTG|−55 to 150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. This device contains ESD protection and exceeds the following tests: Pin 1−15:  Human Body Model 2000 V per JEDEC Standard JESD22, Method A114E. 

Machine Model Method 200 V per JEDEC Standard JESD22, Method A114A. 

Pin 16 is the high voltage startup of the device and is rated to the maximum rating of the part, 500 V. 

2. This device contains Latchup protection and exceeds ± 100 mA per JEDEC Standard JESD78. 

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**4** 

**NCL30001** 

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ÎÎ<br>ÎÎÎ<br>Î<br>Î<br>R LED<br>5 6 2 3<br>IN2+ IN2− IN1− IN1+ 4<br>+ − − +<br>8 GND<br>VCC<br>NCS1002<br>OUT2 OUT1<br>7 1<br>FB<br>VCC Latch VCC<br>NTC<br>16 9<br>HV GND DRV VCC Ispos Iavg TEST<br>NCL30001<br>CT Ramp Comp AC IN FB VFF CM AC COMP LATCH<br>1 8<br>Latch<br>FB<br>EMI Filter<br>**----- End of picture text -----**<br>


**Figure 2. Typical Application Schematic** 

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**5** 

## **NCL30001** 

**ELECTRICAL CHARACTERISTICS** (VCC = 15 V, VAC IN = 3.8 V, VFB = 2.0 V, VFF = 2.4 V, VLatch = open, VISPOS = −100 mV, CDRV = 1 nF, CT = 470 pF, CIAVG = 0.27 nF, CLatch = 0.1 nF, CM = 10 nF, RIAVG = 76.8 k � , RTEST = 50 k � , RRC = 43 k � , For typical Value TJ = 25 ° C, for min/max values TJ = −40 ° C to 125 ° C, unless otherwise noted) 

|**Parameter**|**Test Condition**|**Test Condition**|**Test Condition**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|---|---|
|**OSCILLATOR**||||||||||
|Frequency|||||fosc|90|100|110|kHz|
|Frequency Modulation in Percentage<br>of fOSC||||||–|6.8|–|%|
|Frequency Modulation Period||||||–|6.8|–|ms|
|Ramp Peak Voltage|||||VCT(peak)|–|4.0|–|V|
|Ramp Valley Voltage|||||VCT(valley)|–|0.10|–|V|
|Maximum Duty Ratio|RTEST= open||||D|94|−|–|%|
|Ramp Compensation Peak Voltage|||||VRCOMP(peak)|–|4|–|V|
|**AC ERROR AMPLIFIER**||||||||||
|Input Offset Voltage (Note 3)|Ramp IAVG, VFB= 0 V||||ACVIO||40|–|mV|
|Error Amplifier Transconductance|||||gm|–|100|–|�S|
|Source Current|VAC COMP= 2.0 V, VAC IN= 2.0 V,<br>VFF= 1.0 V||||IEA(source)|25|70|–|�A|
|Sink Current|VAC COMP= 2.0 V, VA C_IN= 2.0 V,<br>VFF= 5.0 V||||IEA(sink)|−25|−70|–|�A|
|**CURRENT AMPLIFIER**||||||||||
|Input Bias Current|VISPOS= 0 V||||CAIbias|40|53|80|�A|
|Input Offset Voltage|VAC COMP= 5.0 V, VISpos= 0 V||||CAVIO|−20|0|20|mV|
|Current Limit Threshold|force DRV high, VAC COMP= 3.0 V,<br>ramp VISPOS, VRamp_Comp= open||||VILIM|0.695|0.74|0.77|V|
|Leading Edge Blanking Duration|||||tLEB|–|200|–|ns|
|Bandwidth||||||–|1.5|–|MHz|
|PWM Output Voltage Gain|PWMk�||<br>4<br>(VILIM�CAVIO)||PWMk|4.0|5.3|6.0|V/V|
|Current Limit Voltage Gain (See<br>Current Sense Section)|ISVK�|||<br>V(AVG)<br>VISPOS|ISVk|15.4|18.5|23|V/V|
|**REFERENCE GENERATOR**||||||||||
|Reference Generator Gain|k�|<br>VAC_REF�VFF 2<br>VFB�VAC_IN|||k|–|0.55|–|V|
|Reference Generator output voltage<br>(low input ac line and full load)|VAC IN=|1.2 V, VFF= 0.765 V,<br>VFB= 4 V|||RGout1|3.61|4.36|4.94|Vpk|
|Reference Generator output voltage<br>(high input ac line and full load)|VAC IN=|3.75 V, VFF= 2.39 V,<br>VFB= 4.0 V|||RGout2|1.16|1.35|1.61|Vpk|
|Reference Generator output Voltage<br>(low input as line and minimum load)|VAC IN=|1.2 V, VFF= 0.765 V,<br>VFB= 2.0 V|||RGout3|1.85|2.18|2.58|Vpk|
|Reference Generator output voltage<br>(high input ac line and minimum load)|VAC IN=|3.75 V, VFF= 2.39 V,<br>VFB= 2.0 V|||RGout4|0.55|0.65|0.78|Vpk|
|Reference Generator output offset<br>voltage|||||RGoffset|−100|–|100|mV|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Guaranteed by Design 

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**6** 

## **NCL30001** 

**ELECTRICAL CHARACTERISTICS** (VCC = 15 V, VAC IN = 3.8 V, VFB = 2.0 V, VFF = 2.4 V, VLatch = open, VISPOS = −100 mV, CDRV = 1 nF, CT = 470 pF, CIAVG = 0.27 nF, CLatch = 0.1 nF, CM = 10 nF, RIAVG = 76.8 k � , RTEST = 50 k � , RRC = 43 k � , For typical Value TJ = 25 ° C, for min/max values TJ = −40 ° C to 125 ° C, unless otherwise noted) 

|**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**AC INPUT**|||||||
|Input Bias Current Into Reference<br>Multiplier & Current Compensation<br>Amplifier||IAC IN(IB)|–|0.01|–|�A|
|**DRIVE OUTPUT**|||||||
|Drive Resistance (Thermally Limited)<br>DRV Sink<br>DRV Source|VDRV= 1 V<br>IDRV= 100 mA|RSNK<br>RSRC|–<br>–|8<br>10.8|18<br>24|�|
|Rise Time (10% to 90%)<br>DRV||tr|–|40|–|ns|
|Fall Time (90% to 10%)<br>DRV||tf|–|20|–|ns|
|Driver Out Low Voltage<br>DRV|IDRV= 100�A|VDRV(low)|–|1.0|100|mV|
|**Soft−Skip**|||||||
|Skip Synchronization to ac Line<br>Voltage Threshold|VACINIncreasing, VFB= 1.5 V|VSSKIP(SYNC)|210|267|325|mV|
|Skip Synchronization to ac Line<br>Voltage Threshold Hysteresis|VACINDecreasing|VSSKIP<br>(SYNCHYS)|–|40|–|mV|
|Skip Ramp Period (Note 3)||tSSKIP|−|2.5|–|ms|
|Skip Voltage Threshold||VSSKIP|360|410|460|V|
|Skip Voltage Hysteresis||VSSKIP(HYS)|45|90|140|mV|
|Skip Transient Load Detect Threshold<br>(Note 3)||VSSKIP(TLD)|−|1.75|−|V|
|**FEEDBACK INPUT**|||||||
|Pull−Up Current Source|VFB= 0.5 V|IFB|600|750|920|�A|
|Pull−Up Resistor||RFB|–|6.7|–|k�|
|Open Circuit Voltage||VFB(open)|5.3|5.7|6.3|V|
|**STARTUP AND SUPPLY CIRCUITS**|||||||
|Supply Voltage<br>Startup Threshold<br>Minimum Operating Voltage<br>Logic Reset Voltage|VCCIncreasing<br>VCCDecreasing<br>VCCDecreasing|VCC(on)<br>VCC(off)<br>VCC(reset)|14.3<br>9.3<br>–|15.4<br>10.2<br>7.0|16.3<br>11.3<br>–|V|
|Inhibit Threshold Voltage|VHV= 40 V, Iinhibit= 500�A|Vinhibit|−|0.83|1.15|V|
|Inhibit Bias Current|VHV= 40 V, VCC= 0.8 * Vinhibit|Iinhibit|40|-|500|�A|
|Minimum Startup Voltage|Istart= 0.5 mA, VCC= VCC(on)– 0.5 V|Vstart(min)|–|–|40|V|
|Startup Current|VCC= VCC(on)– 0.5 V, VFB= Open|Istart|3.0|5.62|8.0|mA|
|Off−State Leakage Current|VHV= 400 V, TJ= 25°C<br>TJ= −40°C to 125°C|IHV(off)|–<br>–|17<br>15|40<br>80|�A|
|Supply Current<br>Device Disabled (Overload)<br>Device Switching|VFB= Open<br>fOSC �100 kHz|ICC1<br>ICC2|–<br>–|0.72<br>6.25|1.2<br>7.2|mA|
|**FAULT PROTECTION**|||||||
|Overload Timer||tOVLD|120|160|360|ms|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Guaranteed by Design 

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**7** 

## **NCL30001** 

**ELECTRICAL CHARACTERISTICS** (VCC = 15 V, VAC IN = 3.8 V, VFB = 2.0 V, VFF = 2.4 V, VLatch = open, VISPOS = −100 mV, CDRV = 1 nF, CT = 470 pF, CIAVG = 0.27 nF, CLatch = 0.1 nF, CM = 10 nF, RIAVG = 76.8 k � , RTEST = 50 k � , RRC = 43 k � , For typical Value TJ = 25 ° C, for min/max values TJ = −40 ° C to 125 ° C, unless otherwise noted) 

|**Parameter**|**Test Condition**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**FAULT PROTECTION**|||||||
|Overload Detect Threshold||VOVLD|4.7|4.9|5.2|V|
|Brown−Out Detect Threshold (entering<br>fault mode)|VFFDecreasing, VFB= 2.5 V,<br>VAC IN= 2.0 V|VBO(low)|0.41|0.45|0.49|V|
|Brown−Out Exit Threshold (exiting<br>fault mode)|VFFIncreasing, VFB= 2.5 V,<br>VAC IN= 2.0 V|VBO(high)|0.57|0.63|0.69|V|
|Brown−Out Hysteresis||VBO(HYS)|−|174|−|mV|
|**LATCH INPUT**|||||||
|Pull−Down Latch Voltage Threshold|VLatchDecreasing|Vlatch(low)|0.9|0.98|1.1|V|
|Pull−Up Latch Voltage Threshold|VLatchIncreasing|Vlatch(high)|5.6|7.0|8.4|V|
|Latch Propagation Delay|VLatch= Vlatch(high)|tlatch(delay)|30|56|90|�s|
|Latch Clamp Current (Going Out)|VLatch= 1.5 V|Ilatch(clamp)|42|51|58|�A|
|Latch Clamp Voltage (ILatchGoing In)|ILatch= 50�A|Vlatch(clamp)|2.5|3.27|4.5|V|
|Latch−Off Current Shutdown<br>(Going In)|VLatchIncreasing|Ilatch(shdn)|−|95|−|�A|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Guaranteed by Design 

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**8** 

**NCL30001** 

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110 8.0<br>105 7.5<br>100 7.0<br>95 6.5<br>90 6.0<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 3. Oscillator Frequency (fOSC) vs. Figure 4. Oscillator Frequency Modulation in<br>Junction Temperature Percentage of fOSC vs. Junction Temperature<br>8.0 4.1<br>4.05<br>7.5<br>4.0<br>7.0 3.95<br>3.9<br>6.5<br>3.85<br>6.0 3.8<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 5. Oscillator Frequency Modulation Figure 6. Ramp Peak Voltage vs. Junction<br>Period vs. Junction Temperature Temperature<br>100 4.1<br>4.05<br>98<br>4.0<br>96<br>3.95<br>94<br>3.9<br>92<br>3.85<br>90 3.8<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 7. Maximum Duty Ratio vs. Junction Figure 8. Ramp Compensation Peak Voltage<br>Temperature vs. Junction Temperature<br>MODULATION (%)<br>OSCILLATOR FREQUENCY<br>, OSCILLATOR FREQUENCY (kHz)<br>fOSC<br>VOLTAGE (V)<br>, OSCILLATOR RAMP PEAK<br>CT(peak)<br>V<br>OSCILLATOR FREQUENCY MODULATION PERIOD (ms)<br>, RAMP COMP PEAK VOLTAGE (V)<br>D, MAXIMUM DUTY RATIO (%)<br>COMP(peak)<br>V<br>**----- End of picture text -----**<br>


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**NCL30001** 

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90 90<br>85 85<br>80 80<br>75 75<br>70 70<br>65 65<br>60 60<br>55 55<br>50 50<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 9. Error Amplifier Source Current vs. Figure 10. Error Amplifier Sink Current vs.<br>Junction Temperature Junction Temperature<br>60.0<br>57.5<br>55.0<br>52.5<br>50.0<br>47.5<br>45.0<br>42.5<br>40.0<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>A)<br>�<br>A)<br>�<br>, ERROR AMPLIFIER<br>CURRENT (<br>, ERROR AMPLIFIER SINK<br>SOURCE CURRENT (<br>IEA(SOURCE) IEA(SINK)<br>A)<br>�<br>, CURRENT AMPLIFIER IN-<br>BIAS PUT BIAS CURRENT (<br>CAV<br>**----- End of picture text -----**<br>


**Figure 11. Current Amplifier Input Bias Current vs. Junction Temperature** 

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770 6.0<br>760<br>5.8<br>750<br>5.6<br>740<br>730<br>5.4<br>720<br>5.2<br>710<br>700 5.0<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 12. Current Limit Threshold vs. Figure 13. PWM Output Voltage Gain vs.<br>Junction Temperature Junction Temperature<br>(mV)<br>, CURRENT LIMIT THRESHOLD<br>ILIM PWMk, PWM VOLTAGE GAIN (V/V)<br>V<br>**----- End of picture text -----**<br>


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**NCL30001** 

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22 5.25<br>4.75 RGout1<br>21<br>4.25<br>3.75<br>20<br>3.25<br>19 2.75<br>RGout3<br>2.25<br>18<br>1.75<br>RGout2<br>1.25<br>17 RGout4<br>0.75<br>16 0.25<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 14. Oscillator CS Limit Voltage Gain vs. Figure 15. Oscillator Reference Generator<br>Junction Temperature Output Voltage vs. Junction Temperature<br>14 16<br>12 14<br>10 12<br>8.0 10<br>6.0 8.0<br>4.0 6.0<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>GAIN (V/V)<br>, REFERENCE GENERATOR OUTPUT VOLTAGE (V)<br>Gout<br>ISVk, CURRENT LIMIT VOLTAGE R<br>) �<br>)( �<br>TANCE (<br>, DRV SINK DRIVE RESIS-<br>, DRV SOURCE RESISTANCE<br>SNK1<br>R SRC1<br>R<br>**----- End of picture text -----**<br>


**Figure 16. DRV Sink Resistance  vs. Junction Temperature** 

**Figure 17. DRV Source Drive Resistance vs. Junction Temperature** 

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**NCL30001** 

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130<br>110<br>90<br>70<br>50<br>30<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>, DRV LOW VOLTAGE (mV)<br>DRV(low)<br>V<br>**----- End of picture text -----**<br>


**Figure 18. DRV Low Voltage vs. Junction Temperature** 

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300 0.410<br>0.408<br>280 0.406<br>0.404<br>260 0.402<br>0.400<br>240 0.398<br>0.396<br>220 0.394<br>0.392<br>200 0.390<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>, SKIP SYNC TO AC<br>, SKIP VOLTAGE THRESHOLD (V)<br>SSKIP(SYNC)<br>V<br>LINE VOLTAGE THRESHOLD (mV) SSKIP<br>V<br>**----- End of picture text -----**<br>


**Figure 19. Skip Synchronization to ac Line Voltage Threshold vs. Junction Temperature** 

**Figure 20. Skip Voltage Threshold vs. Junction Temperature** 

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100 780<br>95 755<br>90 730<br>85 705<br>80 680<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 21. Skip Voltage Hysteresis vs. Figure 22. Feedback Pull−Up Current Source<br>Junction Temperature vs. Junction Temperature<br>6.2 15.75<br>6.0 15.55<br>5.8 15.35<br>5.6 15.15<br>5.4 14.95<br>5.2 14.75<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>A)<br>�<br>(mV)<br>SOURCE (<br>, SKIP VOLTAGE HYSTERESIS , FEEDBACK PULL−UP CURRENT<br>VSSKIP IFB<br>, FEEDBACK OPEN CIR-<br>CUIT VOLTAGE (V)<br>, STARTUP THRESHOLD (V)<br>FB(open)<br>V CC(on)<br>V<br>**----- End of picture text -----**<br>


**Figure 23. Feedback Open Circuit Voltage vs. Junction Temperature** 

**Figure 24. Startup Threshold vs. Junction Temperature** 

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10.5<br>10.3<br>10.1<br>9.9<br>9.7<br>9.5<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 25. Minimum Operating Voltage vs.<br>Junction Temperature<br>VOLTAGE (V)<br>, MINIMUM OPERATING<br>CC(off)<br>V<br>**----- End of picture text -----**<br>


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1000<br>350<br>950<br>330<br>900<br>850 310<br>800<br>290<br>750<br>270<br>700<br>650 250<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 26. Inhibit Threshold Voltage vs. Figure 27. Inhibit Bias Current vs. Junction<br>Junction Temperature Temperature<br>25.0 6.0<br>VCC =  VCC − 0.5 V<br>Istart = 0.5 mA<br>24.5<br>5.8<br>24.0<br>5.6<br>23.5<br>5.4<br>23.0<br>5.2<br>22.5<br>22.0 5.0<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 28. Minimum Startup Voltage vs. Figure 29. Startup Current vs. Junction<br>Junction Temperature Temperature<br>30 850<br>825<br>25 800<br>775<br>20 750<br>725<br>15 700<br>675<br>10 650<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>A)<br>�<br>AGE (V)<br>, INHIBIT THRESHOLD VOLT- , INHIBIT BIAS CURRENT (<br>Vinhibit Iinhibit<br>, MINIMUM STARTUP<br>VOLTAGE (V)<br>, STARTUP CURRENT (mA)<br>Vstartup(min) Istart<br>A)<br>A) �<br>�<br>RENT (<br>DISABLED (<br>, OFF−STATE LEAKAGE CUR- , SUPPLY CURRENT DEVICE<br>ICC1<br>IHV(off)<br>**----- End of picture text -----**<br>


**Figure 30. Off−State Leakage Current  vs. Junction Temperature** 

**Figure 31. Supply Current Device Disabled (Overload) vs. Junction Temperature** 

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6.75 200<br>6.55 180<br>6.35 160<br>6.15 140<br>5.95 120<br>5.75 100<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 32. Supply Current Device Switching Figure 33. Overload Timer vs. Junction<br>vs. Junction Temperature Temperature<br>5.5 500<br>5.3 480<br>5.1 460<br>4.9 440<br>4.7 420<br>4.5 400<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 34. Overload Detect Threshold vs. Figure 35. Brown−Out Detect Threshold vs.<br>Junction Temperature Junction Temperature<br>650 180<br>640<br>175<br>630<br>170<br>620<br>165<br>610<br>600 160<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>SWITCHING  (mA)<br>, OVERLOAD TIMER (ms)<br>, SUPPLY CURRENT DEVICE<br>ICC2 tOVLD<br>, OVERLOAD DETECT THRESHOLD  (V) , BROWN−OUT DETECT THRESHOLD (mV)<br>OVLD<br>V BO(low)<br>V<br>SIS (mV)<br>, BROWN−OUT EXIT<br>THRESHOLD (mV) , BROWN−OUT HYSTERE-<br>BO(high)<br>V<br>BO(HYS)<br>V<br>**----- End of picture text -----**<br>


**Figure 36. Brown−Out Exit Threshold vs. Junction Temperature** 

**Figure 37. Brown−Out Hysteresis vs. Junction Temperature** 

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1000 7.5<br>980 7.3<br>960 7.1<br>940 6.9<br>920 6.7<br>900 6.5<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 38. Latch Pull−Down Voltage Threshold Figure 39. Latch Pull−Up Threshold vs.<br>vs. Junction Temperature Junction Temperature<br>7.5 60<br>7.3 58<br>7.1 56<br>6.9 54<br>6.7 52<br>6.5 50<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 40. Latch Pull−Up Voltage Threshold Figure 41. Latch Propagation Delay vs.<br>vs. Junction Temperature Junction Temperature<br>55<br>54<br>53<br>52<br>51<br>50<br>−50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>, LATCH PULL−DOWN , LATCH PULL−UP<br>THRESHOLD (V)<br>LATCH(low) VOLTAGE THRESHOLD (mV) LATCH(low_HYS)<br>V V<br>s)<br>�<br>, LATCH PULL−UP VOLT- , LATCH PROPAGATION DELAY (<br>AGE THRESHOLD (V)<br>VLATCH(lhigh) LATCH(delay)<br>V<br>A)<br>�<br>, LATCH CLAMP CUR- RENT (<br>ILATCH(clamp)<br>**----- End of picture text -----**<br>


**Figure 42. Latch Clamp Current vs. Junction Temperature** 

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3.5 100<br>3.4 98<br>3.3 96<br>3.2 94<br>3.1 92<br>3.0 90<br>−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE ( ° C) TJ, JUNCTION TEMPERATURE ( ° C)<br>A)<br>�<br>AGE (V)<br>, LATCH CLAMP VOLT- , LATCH−OFF CURRENT<br>SHUTDOWN (<br>LATCH(clamp) LATCH(shdn)<br>V V<br>**----- End of picture text -----**<br>


**Figure 43. Latch Clamp Voltage vs. Junction Temperature** 

**Figure 44. Latch−Off Current Shutdown vs. Junction Temperature** 

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**NCL30001** 

## **DETAILED DEVICE DESCRIPTION** 

## **Introduction** 

The NCL30001 is a highly integrated controller combining PFC and isolated step down power conversion in a single stage, resulting in a lower cost and reduced part count solution. This controller is ideal for LED Lighting applications with power requirements between 40 W and 150 W with an output voltage greater than 12 V. The single stage is based on the flyback converter and it is designed to operate in CCM mode. 

## **Power Factor Correction (PFC) Introduction** 

Power factor correction shapes the input current of off−line power supplies to maximize the real power available from the mains. Ideally, the electrical appliance should present a load that emulates a pure resistor, in which case the reactive power drawn by the device is zero. Inherent in this scenario is the freedom from input current harmonics. The current is a perfect replica of the input voltage (usually a sine wave) and is exactly in phase with it. In this case the current drawn from the mains is at a minimum for the real power required to perform the needed work, and this minimizes losses and costs associated not only with the distribution of the power, but also with the generation of the power and the capital equipment involved in the process. The freedom from harmonics also minimizes interference with other devices being powered from the same source. 

Another reason to employ PFC in many of today’s power supplies is to comply with regulatory requirements. Today, lighting equipment in Europe must comply with IEC61000−3−2 Class C. This requirement applies to most lighting applications with input power of 25 W or greater, and it specifies the maximum amplitude of line−frequency harmonics up to and including the 39[th] harmonic. Moreover power factor requirements for commercial lighting is included within the ENERGY STAR® Solid State Lighting Luminaire standard regardless of the applications power level. 

## **Typical Power Supply with PFC** 

A typical power supply consists of a boost PFC preregulator creating an intermediate �400 V bus and an isolated dc−dc converter producing the desired output voltage as shown in Figure 45. This architecture has two power stages. 

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**----- Start of picture text -----**<br>
Rectifier DC−DC<br>AC PFC<br>& Converter<br>Input Filter Preregulator with isolation Vout<br>**----- End of picture text -----**<br>


**Figure 45. Typical Two Stage Power Converter** 

A two stage architecture allows optimization of each individual power stage. It is commonly used because of designer familiarity and a vast range of available 

components. But, because it processes the power twice, the search is always on for a more compact and power efficient solution. 

The NCL30001 controller offers the convenience of shrinking the front−end converter (PFC preregulator) and the dc−dc converter into a single power processing stage as shown in Figure 46. 

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**----- Start of picture text -----**<br>
Rectifier NCL30001 Based<br>AC<br>Input & Single−Stage Vout<br>Filter Flyback Converter<br>**----- End of picture text -----**<br>


**Figure 46. Single Stage Power Converter** 

This approach significantly reduces the component count. The NCL30001 based solution requires only one each of MOSFET, magnetic element, output rectifier (low voltage) and output capacitor (low voltage). In contrast, the 2−stage solution requires two or more of the above−listed components. Elimination of certain high−voltage components (e.g. high voltage capacitor and high voltage PFC diode) has significant impact on the system design. The resultant cost savings and reliability improvement are often worth the effort of designing a new converter. 

## **Single PFC Stage** 

While the single stage offers certain benefits, it is important to recognize that it is not a recommended solution for all requirements. The following three limitations apply to the single stage approach: 

- The output voltage ripple will have a 2x line frequency component (120 Hz for North American applications) that can not be eliminated easily. The cause of this ripple is the elimination of the energy storage element that is typically the boost output capacitor in the 2−stage solution. The only way to reduce the ripple is to increase the output filter capacitance. The required value of capacitance is inversely proportional to the output voltage. Normally the presence of this ripple is not a issue for most LED lighting applications. 

- The hold−up time will not be as good as the 2−stage approach – again due to the lack of an intermediate energy storage element. 

- In a single stage converter, one FET processes all the power – that is both a benefit and a limitation as the stress on that main MOSFET is relatively higher. Similarly, the magnetic component (flyback transformer/inductor) can not be optimized as well as in the 2−stage solution. As a result, potentially higher leakage inductance induces higher voltage spikes (like the one shown in Figure 47) on the MOSFET drain. This may require a MOSFET with a higher voltage 

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rating compared to similar dc−input flyback applications. 

a slightly higher cost and dissipates power only when the drain voltage exceeds the voltage rating of the TVS. 

Other features found in the NCL30001 include a high voltage startup circuit, voltage feedforward, brown out detector, internal overload timer, latch input and a high accuracy multiplier. 

## **NCL30001 PFC Loop** 

The NCL30001 incorporates a modified version of average current mode control used for achieving the unity power factor. The PFC section includes a variable reference generator, a low frequency voltage regulation error amplifier (AC error AMP), ramp compensation (Ramp Comp) and current shaping network. These blocks are shown in the lower portion of the bock diagram (Figure 45). 

**Figure 47. Typical Drain Voltage Waveform of a Flyback Main Switch** 

There are two methods to clamp the voltage spike on the main switch, a resistor−capacitor−diode (RCD) clamp or a transient voltage suppressor (TVS). 

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**----- Start of picture text -----**<br>
RCD<br>Vin a | Clamp<br>| R C<br>| D<br>| e<br>ne|<br>Lo<br>Figure 48. RCD Clamp<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Vout<br>Vout<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
TVS<br>Vin rs | Clamp<br>| TVS<br>|<br>| e<br>LE<br>Lo<br>Figure 49. TVS Clamp<br>**----- End of picture text -----**<br>


Both methods result in dissipation of the leakage energy in the clamping circuits – the dissipation is proportional to LI[2] where L is the leakage inductance of the transformer and I is the peak of the switch current at turn−off. An RCD snubber is simple and has the lowest cost, but constantly dissipates power. A TVS provides good voltage clamping at 

The inputs to the reference generator include feedback signal (FB), scaled AC input signal (AC_IN) and feedforward input (VFF). The output of the reference generator is a rectified version of the input sine−wave scaled by the FB and VFF values. The reference amplitude is proportional to the FB and inversely proportional to the square of the VFF. This, for higher load levels and/or lower input voltage, the signal would be higher. 

The function of the AC error amp is to force the average current output of the current sense amplifier to match the reference generator output. The output of the AC error amplifier is compensated to prevent response to fast events. This output (Verror) is fed into the PWM comparator through a reference buffer. The PWM comparator sums the Verror and the instantaneous current and compares it to a 4.0 V threshold to provide the desired duty cycle control. Ramp compensation is also added to the input signal to allow CCM operation above 50% duty cycle. 

## **High Voltage Startup Circuit** 

The NCL30001 internal high voltage startup circuit eliminates the need for external startup components and provides a faster startup time compared to an external startup resistor. The startup circuit consists of a constant current source that supplies current from the HV pin to the supply capacitor on the VCC pin (CCC). The startup current (Istart) is typically 5.5 mA. 

The DRV driver is enabled and the startup current source is disabled once the VCC voltage reaches VCC(on), typically 15.4 V. The controller is then biased by the VCC capacitor. The drivers are disabled if VCC decays to its minimum operating threshold (VCC(off)) typically 10.2 V. Upon reaching VCC(off) the gate driver is disabled. The VCC capacitor should be sized such VCC is kept above VCC(off) while the auxiliary voltage is building up. Otherwise, the system will not start. 

The controller operates in double hiccup mode while in overload or VCC(off). A double hiccup fault disables the drivers, sets the controller in a low current mode and allows VCC to discharge to VCC(off). This cycle is repeated twice to minimize power dissipation in external components during 

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## **NCL30001** 

a fault event. Figure 50 shows double hiccup mode operation. A soft−start sequence is initiated the second time VCC reaches VCC(on). If the controller is latched upon reaching VCC(on), the controller stays in hiccup mode. 

During this mode, VCC never drops below VCC(reset), the controller logic reset level. This prevents latched faults to be cleared unless power to the controller is completely removed (i.e. unplugging the supply from the AC line). 

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**----- Start of picture text -----**<br>
VCC<br>VCC(on) wee eee' eee' eeeee' ' eee<br>' '<br>VCC(off) rn 'i rn ' TT1 ' TTT<br>''''<br>'' 1 '<br>''''<br>t<br>'' ' '<br>DRV ''''<br>'' 1 '<br>''''<br>''1'<br>'<br>'<br>'<br>'<br>'''' t<br>'' ' '<br>Fault Timer ''''<br>(internal) '' 1 '<br>a ee<br>Overload '''<br>applied '''' ''<br>'1 '<br>' '<br><*> tOVLD ' 4 t<br>**----- End of picture text -----**<br>


**Figure 50. VCC Double Hiccup Operation with a Fault Occurring while the Startup Circuit is Disabled** 

An internal supervisory circuit monitors the VCC voltage to prevent the controller from dissipating excessive power if the VCC pin is accidentally grounded. A lower level current source (Iinhibit) charges CCC from 0 V to Vinhibit, 

typically 0.85 V. Once VCC exceeds Vinhibit, the startup current source is enabled. This behavior is illustrated in Figure 51. This slightly increases the total time to charge VCC, but it is generally not noticeable. 

**Figure 51. Startup Current at Various VCC Levels** 

The rectified ac line voltage is provided to the power stage to achieve accurate PFC. Filtering the rectified ac line voltage with a large bulk capacitor distorts the PFC in a single stage PFC converter. A peak charger is needed to bias 

the HV pin as shown in Figure 52. Otherwise, the HV pin follows the ac line and the startup circuit is disabled every time the ac line voltage approaches 0 V. The VCC capacitor is sized to bias the controller during power up. 

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**----- Start of picture text -----**<br>
Peak Charger<br>VIN VOUT<br>HV<br>DRV<br>NCL30001<br>**----- End of picture text -----**<br>


**Figure 52. Peak charger** 

The startup circuit is rated at a maximum voltage of 500 V. Power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. If dissipation on the controller is excessive, a resistor can be placed in series with the HV pin. This will reduce power dissipation on the controller and transfer it to the series resistor. 

## **Drive Output** 

DRV has a source resistance of 10.8 � (typical) and a sink resistance of 8.0 � (typical). The driver is enabled once VCC reaches VCC(on) and there are no faults present. They are disabled once VCC discharges to VCC(off). The high current drive capability of DRV may generate voltage spikes during switch transitions due to parasitic board inductance. Shortening the connection length between the driver and the load and using wider connections will reduce inductance−induced spikes. 

## **AC Error Amplifier and Buffer** 

The AC error amplifier (EA) shapes the input current into a high quality sine wave by forcing the filtered input current to follow the output of the reference generator. The output of the reference generator is a full wave rectified ac signal 

and it is applied to the non inverting input of the EA. The filtered input current, Iin, is the current sense signal at the ISpos pin multiplied by the current sense amplifier gain. It is applied to the inverting input of the AC EA. 

The AC EA is a transconductance amplifier. A transconductance amplifier generates an output current proportional to its differential input voltage. This amplifier has a nominal gain of 100 �S (or 0.0001 A/V). That is, an input voltage difference of 10 mV causes the output current to change by 1.0 �A. The AC EA has typical source and sink currents of 70 �A. 

The filtered input current is a high frequency signal. A low frequency pole forces the average input current to follow the reference generator output. A pole-zero pair is created by placing a (RCOMP) and capacitor (CCOMP) series combination at the output of the AC EA. The AC COMP pin provides access to the AC EA output. 

The output of the AC EA is inverted and converted into a current using a second transconductance amplifier. The output of the inverting transconductance amplifier is VACEA(buffer). Figure 53 shows the circuit schematic of the AC EA buffer. The AC EA buffer output current, IACEA(out), is given by Equation 1. 

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**----- Start of picture text -----**<br>
VDD<br>x 4<br>IACEA(out) To PWM<br>+<br>+ comparator<br>2.8V −<br>VAC_REF 21.33k �<br>gm = 100 � S 37.33k �<br>IAVG +<br>gm +<br>−<br>AC error −<br>amplifier<br>RIAVG<br>AC COMP<br>RAC_COMP<br>**----- End of picture text -----**<br>


**Figure 53. AC EA Buffer Amplifier** 

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The voltage at the PWM non-inverting input is determined by IACEA(out), the instantaneous switch current along and the ramp compensation current. DRV is terminated once the voltage at the PWM non-inverting input reaches 4 V. 

## **Current Sense Amplifier** 

amplifier is a wide bandwidth amplifier with a differential input. The current sense amplifier has two outputs, PWM Output and IAVG Output. The PWM Output is the instantaneous switch current which is filtered by the internal leading edge blanking (LEB) circuitry prior to applying it to the PWM Comparator non inverting input. The second output is a filtered current signal resembling the average value of the input current. Figure 54 shows the internal architecture of the current sense amplifier. 

A voltage proportional to the main switch current is applied to the current sense input, ISPOS. The current sense 

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**----- Start of picture text -----**<br>
Ip<br>Ispos gm = 250 � S<br>+ blanking Inst. current To PWM<br>− gm tLEB comparator<br>RCS Current sense<br>amplifier<br>IAVG VIAVG To AC error<br>amplifier<br>CIAVG RIAVG<br>**----- End of picture text -----**<br>


**Figure 54. Current Sense Amplifier** 

Caution should be exercised when designing a filter between the current sense resistor and the ISPOS input, due to the low impedance of this amplifier. Any series resistance due to a filter creates a voltage offset (VOS) due to its input bias current, CAIbias. The input bias current is typically 60 �A. The voltage offset is given by Equation 2. 

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The offset adds a positive offset to the current sense signal. The ac error amplifier will then try to compensate for the average output current which appears never to go to zero and cause additional zero crossing distortion. 

A voltage proportional to the main switch current is applied to the ISPOS pin. The ISPOS pin voltage is converted into a current, i1, and internally mirrored. Two internal currents are generated, ICS and IAVG. ICS is a high frequency signal which is a replica of the instantaneous switch current. IAVG is a low frequency signal. The relationship between VISPOS and ICS and IAVG is given by Equation 3. 

**==> picture [154 x 24] intentionally omitted <==**

The PWM Output delivers current to the positive input of the PWM input where it is added to the AC EA and ramp compensation signal. 

The IAVG Output generates a voltage signal to a buffer amplifier. This voltage signal is the product of IAVG and an external RIAVG resistor filtered by the capacitor on the IAVG pin, CIAVG. The pole frequency, _f_ P, set by CIAVG should be significantly below the switching frequency to remove the high frequency content. But, high enough to not to cause significant distortion to the input full wave rectified sinewave waveform. A properly filtered average current signal has twice the line frequency. Equation 4 shows the relationship between CIAVG (in nF) and _f_ P (in kHz). 

**==> picture [168 x 24] intentionally omitted <==**

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**NCL30001** 

The gain of the low frequency current buffer is set by the resistor at the IAVG pin, RIAVG. RIAVG sets the scaling factor between the primary peak and primary average currents. The gain of the current sense amplifier, ACA, is given by Equation 5. 

**==> picture [142 x 24] intentionally omitted <==**

The current sense signal is prone to leading edge spikes during the switch turn on due to parasitic capacitance and inductance. This spike may cause incorrect operation of the PWM Comparator. The NCL30001 incorporates LEB circuitry to block the first 200 ns (typical) of each current pulse. This removes the leading edge spikes without filtering the current signal waveform. 

## **Oscillator** 

The oscillator controls the switching frequency, _f_ , the jitter frequency and the gain of the multiplier. The oscillator ramp is generated by charging the timing capacitor on the CT Pin, CT, with a 200 �A current source. This current source is tightly controlled during manufacturing to achieve a controlled and repeatable oscillator frequency. The current source turns off and CT is immediately discharged with a pull down transistor once the oscillator ramp reaches its peak voltage, VCT(peak), typically 4.0 V. The pull down transistor turns off and the charging current source turns on once the oscillator ramp reaches its valley voltage, VCT(valley). Figure 55 shows the resulting oscillator ramp and control circuitry. 

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**----- Start of picture text -----**<br>
VDD<br>x 1.2<br>To PWM<br>comparator<br>Ramp Comp<br>To PWM skip<br>comparator<br>RRC<br>VDD<br>CT<br>CT<br>+<br>4.0 V / 0.1 V<br>Oscillator<br>− +<br>+<br>−<br>**----- End of picture text -----**<br>


**Figure 55. Oscillator Ramp and Control Circuitry** 

The relationship between the oscillator frequency in kHz and timing capacitor in pF is given by Equation 6. 

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A low frequency oscillator modulates the switching frequency, reducing the controller EMI signature and allowing the use of a smaller EMI filter. The frequency modulation or jitter is typically ±6.8% of the oscillator frequency. 

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## **Output Overload** 

The Feedback Voltage, VFB, is directly proportional to the output power of the converter. An internal 6.7 k Q resistor pulls−up the FB voltage to the internal 6.5 V reference. An external optocoupler pulls down the FB voltage to regulate the output voltage of the system. The optocoupler is off during power up and output overload conditions allowing the FB voltage to reach its maximum level. 

The NCL30001 monitors the FB voltage to detect an overload condition. A typical startup time of a single PFC stage converter is around 100 ms. If the converter is out of regulation (FB voltage exceeds 5.0 V) for more that 160 ms (typical) the drivers are disabled and the controller enters the double hiccup mode to reduce the average power dissipation. A new startup sequence is initiated after the double hiccup is complete. This protection feature is critical to reduce power during an output short condition. 

260 mV. A new Soft−Skip period starts once the voltage on the AC−IN pin increases to 260 mV. 

An increase in output load current terminates a Soft−Skip event. A transient load detector terminates a Soft−Skip period once VFB voltage exceeds VSSKIP (1.75 V nominal). This ensures the required output power is delivered during a load transient and the output voltage does not fall out of regulation. Figure 57 shows the relationship between Soft−Skip and the transient load detector. 

## **Soft−Skip** ™ **Cycle Mode** 

The FB voltage reduces as the output power demand of the converter reduces. Once VFB drops below the skip threshold, VSSKIP, 410 mV (typical) the driver is disabled. The skip comparator hysteresis is typically 90 mV. 

The converter output voltage starts to decay because no additional output power is delivered. As the output voltage decreases the feedback voltage increases to maintain the output voltage in regulation. This mode of operation is known as skip mode. The skip mode frequency is dependent of load loop gain and output capacitance and can create audible noise due to mechanical resonance in the transformer and snubber capacitor. A proprietary Soft−Skip mode reduces audible noise by slowly increasing the primary peak current until it reaches its maximum value. The minimum skip ramp period, tSSKIP, is 2.5 ms. Figure 56 shows the relationship between VFB, VSSKIP and the primary current. 

**==> picture [62 x 24] intentionally omitted <==**

**----- Start of picture text -----**<br>
VSSKIP<br>VFB<br>J<br>**----- End of picture text -----**<br>


**Figure 57. Load transient during Soft−Skip** 

The output of the Soft−Skip Comparator is or−ed with the PWM Comparator output to control the duty ratio. The Soft−Skip Comparator controls the duty ratio in skip mode and the PWM Comparator controls the duty cycle during normal operation. In skip mode, the non−inverting input of the Soft−Skip Comparator exceeds 4 V, disabling the drivers. As the FB voltage increases, the voltage at the non−inverting input is ramp down from 4 V to 0.2 V to enable the drivers. 

## **Multiplier and Reference Generator** 

**Figure 56. Soft−Skip Operation** 

Skip mode operation is synchronized to the ac line voltage. The NCL30001 disables Soft−Skip when the rectified ac line voltage drops to its valley level. This ensures the primary current always ramp up reducing audible noise. A skip event occurring as the ac line voltage is decreasing, causes the primary peak current to ramp down instead of ramp up. Once the skip period is over the primary current is only determined by the ac line voltage. A Soft−Skip event terminates once the AC−IN pin voltage decreases below 

The NCL30001 uses a multiplier to regulate the average output power of the converter. This controller uses a proprietary concept for the multiplier used within the reference generator. This innovative design allows greatly improved accuracy compared to a conventional linear analog multiplier. The multiplier uses a PWM switching circuit to create a scalable output signal, with a very well defined gain. 

The output of the multiplier is the ac-reference signal. The ac-reference signal is used to shape the input current. The multiplier has three inputs, the error signal from an external error amplifier (VFB), the full wave rectified ac input (AC_IN) and the feedforward input (VFF). 

The FB signal from an external error amplifier circuit is applied to the VFB pin via an optocoupler or other isolation circuit. The FB voltage is converted to a current with a V-I 

VCC 

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**NCL30001** 

converter. There is no error in the output signal due to the series rectifier as shown in Figure 58. 

The scaled version of the full wave rectified input ac wave is applied to the AC_IN pin by means of a resistive voltage divider. The multiplier ramp is generated by comparing the scaled line voltage to the oscillator ramp with the AC_IN Comparator. The current signal from the V-I converter is 

factored by the AC_IN comparator output. The resulting signal is filtered by the low pass R-C filter on the CM pin. The low pass filter removes the high frequency content. The gain of the multiplier is determined by the V-I converter, the resistor on the CM pin, and the peak and valley voltages of the oscillator sawtooth ramp. 

**==> picture [435 x 313] intentionally omitted <==**

**----- Start of picture text -----**<br>
FB<br>Multiplier<br>V−to−I<br>AC IN Oscillator+− VAC_REF  � k  � VFBV  � FF VAC_IN [2]<br>CM Divide AC_REF<br>VFF [2]<br>VFF Square<br>**----- End of picture text -----**<br>


**Figure 58. Reference Generator** 

The third input to the reference generator is the VFF signal. The VFF signal is a dc voltage proportional to the ac line voltage. A resistive voltage divider attenuates the full wave rectified line voltage between 0.7 and 5.0 V. The full wave rectified line is then averaged with a capacitor. The ac average voltage must be constant over each half cycle of the line. Line voltage ripple (120 Hz or 100 Hz) ripple on the VFF signal adds ripple to the output of the multiplier. This will distort the ac reference signal and reduce the power factor and increase the line current distortion. Excessive filtering delays the feedforward signal reducing the line transient response. A good starting point is to set the filter time constant to one cycle of the line voltage. The user can then optimize the filter for line transient response versus power factor. The average voltage on the VFF pin is: 

**==> picture [149 x 19] intentionally omitted <==**

Where, � is the voltage divider ratio, normally 0.01. 

**==> picture [171 x 29] intentionally omitted <==**

The multiplier transfer function is given by Equation 8. The output of the multiplier is the AC_REF. It connects to the AC Error Amplifier. 

where, k is the reference generator gain, typically 0.55. The output of the reference generator is clamped at 4.5 V to limit the maximum output power. 

Feedforward maintains a constant input power independent of the line voltage. That is, for a given FB voltage, if the line voltage doubles (AC_IN), the feedforward term quadruples and reduces the output of the error amplifier in half to maintain the same input power. 

## **AC Error Amplifier Compensation** 

A pole-zero pair is created by placing a series combination of RCOMP and CCOMP at the output of the AC error amplifier (EA). The value of the compensation components is 

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**NCL30001** 

dependent of the average input current and the instantaneous switch current. The gain of the average input current or slow loop is given by Equation 9. 

**==> picture [221 x 28] intentionally omitted <==**

The low frequency gain is the product of the current sense averaging circuit, the transconductance amplifier and the gain of the AC error amplifier. 

A current proportional to the instantaneous current is generated using a 4 k� resistor in the current sense amplifier input. This proportional current is applied to a 21.33 k� at the PWM comparator input to generate a current sense voltage signal. The high frequency or fast loop gain, AHF, is calculated using Equation 10. 

**==> picture [153 x 21] intentionally omitted <==**

Equation 11 shows system stability requirements. That is, the low frequency gain has to be less than one half of the high frequency gain. 

**==> picture [224 x 28] intentionally omitted <==**

Equation 12 is obtained by re-arranging Equation 11 for RAC_COMP. This equation provides the maximum value for RAC_COMP. 

**==> picture [165 x 24] intentionally omitted <==**

The control loop zero, _f_ Z, is calculated using Equation 13. The control loop zero should be set at approximately at 1/10[th] of the oscillator frequency, _f_ OSC. The compensation capacitor is calculated using Equation 14. 

**==> picture [186 x 65] intentionally omitted <==**

## **Current Sense Resistor** 

The PFC stage has two control loops. The first loop controls the average input current and the second loop controls the instantaneous current across the main switch. The current sense signal affects both loops. The current sense signal is fed into the positive input of the error amplifier to control the average input current. In addition, the current sense information together with the ramp compensation and error amplifier signal control the instantaneous primary peak current. 

The primary peak current, IPK, is calculated using Equation 15, 

**==> picture [186 x 31] intentionally omitted <==**

where, Vin(LL) is the low line ac input voltage, D is the duty ratio, Pout is the output power, Pin is the input power, � is the efficiency, LP is the primary inductance and ton is the on time. Typical efficiency for this topology is around 88%. 

The current sense resistor is selected to achieve maximum signal resolution at the input of the ac reference amplifier. The maximum voltage input of the ac reference amplifier to prevent saturation is 4.5 V. This together with the instantaneous peak current is used to calculate the current sense resistor, RCS, using Equation 16. 

**==> picture [170 x 36] intentionally omitted <==**

## **Ramp Compensation** 

Subharmonic oscillations are observed in peak current-mode controllers operating in continuous conduction mode with a duty ratio greater than 50%. Injecting a compensation ramp on the current sense signal eliminates the subharmonic oscillations. The amount of compensation is system dependent and it is determined by the inductor falling di/dt. 

The NCL30001 has built in ramp compensation to facilitate system design. The amount of ramp compensation is set by the user with a resistor, RRCOMP, between the Ramp Comp pin and ground. The Ramp Comp pin buffers the oscillator ramp generated on the CT pin. The current across RRCOMP is internally mirrored with a 1:1.2 ratio. The inverted ac error amplifier and the instantaneous switch current signals are added to the ramp compensation mirrored current. The resulting current signal is applied to an internal 21.33 k� between the PWM Comparator non inverting input and ground as shown in Figure 55. 

The maximum voltage contribution of the ramp compensation signal to the error signal, VRCOMP, is given by Equation 17. 

**==> picture [236 x 65] intentionally omitted <==**

For proper ramp compensation, the ramp signal should match the falling di/dt (which has been converted to a dv/dt) of the inductor at 50% duty cycle. Both the falling di/dt and output voltage need to be reflected by the transformer turns ratio to the primary side. Equations 18 through 23 assist in the derivation of equations for RCS and RCOMP. 

**==> picture [200 x 69] intentionally omitted <==**

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## **NCL30001** 

**==> picture [189 x 61] intentionally omitted <==**

At low line and full load, the output of the ac error amplifier output is nearly saturated in a low state. While the ac error amplifier output is saturated, IACEA is zero and does not contribute to the voltage across the internal 21.33 k� resistor on the PWM comparator non-inverting input. In this operation mode, the voltage across the 21.33 k� resistor is determined solely by the ramp compensation and the instantaneous switch current as given by Equation 22. 

**==> picture [189 x 23] intentionally omitted <==**

The voltage reference of the PWM Comparator, VREF(PWM), is 4 V. For these calculations, 3.8 V is used to provide some margin. The maximum instantaneous switch current voltage contribution, VINST, is given by Equation 23. 

**==> picture [165 x 11] intentionally omitted <==**

Substituting Equation 23 in Equation 22, setting VREF(PWM) at 3.8 V (provides margin) and solving for RRCOMP, Equation 24 is obtained. 

**==> picture [208 x 29] intentionally omitted <==**

Replacing Equation 24 in Equation 21 we obtain: 

**==> picture [200 x 37] intentionally omitted <==**

latch is Set dominant which means that if both R and S are high the S signal will dominate and Q will be high, which will hold the power switch off. 

The NCL30001 uses a pulse width modulation scheme based on a fixed frequency oscillator. The oscillator generates a voltage ramp as well as a pulse in sync with the falling edge of the ramp. The pulse is an input to the PWM Logic and Driver block. While the oscillator pulse is present, the latch is reset, and the output drive is in its low state. On the falling edge of the pulse, the DRV goes high and the power switch begins conduction. 

The instantaneous inductor current is summed with a current proportional to the ac error amplifier output voltage. This complex waveform is compared to the 4 V reference signal on the PWM comparator inverting input. When the signal at the non-inverting input to the PWM comparator exceeds 4 V, the output of the PWM comparator toggles to a high state which drives the Set input of the latch and turns the power switch off until the next clock cycle. 

## **Brown−Out** 

The NCL30001 incorporates a brown−out detection circuit to prevent the controller operate at low ac line voltages and reduce stress in power components. A scaled version of the rectified line voltage is applied to the VFF Pin by means of a resistor divider. This voltage is used by the brown out detector. 

A brown−out condition exists if the feedforward voltage is below the brown−out exit threshold, VBO(high), typically 0.45 V. The brown−out detector has 175 mV hysteresis. The controller is enabled once VFF is above 0.63 V and VCC reaches VCC(on). Figure 59 shows the relationship between the brown−out, VCC and DRV signals. 

## **PWM Logic** 

The PWM and logic circuits are comprised of a PWM comparator, an RS flip-flop (latch) and an OR gate. The 

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**NCL30001** 

**==> picture [153 x 247] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCC<br>VCC(on)<br>VCC(off)<br>t<br>DRV<br>t<br>VFF<br>VBO(low)<br>VBO(high)<br>Brown−Out<br>t<br>**----- End of picture text -----**<br>


**Figure 59. Relationship Between the Brown−Out, VCC, and DRV** 

**==> picture [446 x 221] intentionally omitted <==**

**----- Start of picture text -----**<br>
Vaux or VCC VDD OVP comparator<br>+<br>+ −<br>Ilatch(clamp) Vlatch(high)<br>blanking<br>Latch−Off tlatch(delay)<br>OTP comparator<br>I latch(shdn) −+ S Q Latch<br>+ R<br>NTC Vlatch(low)<br>Vlatch(clamp)<br>Reset<br>**----- End of picture text -----**<br>


**Figure 60.** 

## **Latch Input** 

The NCL30001 has a dedicated latch input to easily latch the controller during overtemperature and overvoltage faults (See Figure 60). The controller is latched if the 

Latch−Off pin voltage is pulled below 1 V or above 6.5 V. Figure 61 shows the relationship between the Latch−Off, VCC and DRV signals. 

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**NCL30001** 

**==> picture [179 x 251] intentionally omitted <==**

**----- Start of picture text -----**<br>
VCC<br>VCC(on)<br>VCC(off)<br>t<br>DRV<br>t<br>Latch−Off<br>Latch−Off<br>Vlatch(high)<br>Vlatch(low)<br>Latch−Off<br>t<br>**----- End of picture text -----**<br>


**Figure 61. Relationship Between the Latch−Off, VCC, and DRV** 

The Latch−Off pin is clamped at 3.5 V. A 50 �A (typical) pull−up current source is always on and a 100 �A (typical) pull−down current source is enabled once the Latch−Off pin voltage reaches 3.5 V (typical). This effectively clamps the Latch−Off pin voltage at 3.5 V. A minimum pull−up or pull−down current of 50 �A is required to overcome the internal current sources and latch the controller. The 

Latch−Off input features a 50 �s (typical) filter to prevent latching the controller due to noise or a line surge event. 

The startup circuit continues to cycle VCC between VCC(on) and VCC(off) while the controller is in latch mode. The controller exits the latch mode once power to the system is removed and VCC drops below VCC(reset). 

## **APPLICATION INFORMATION** 

ON Semiconductor provides an electronic design tool, facilitate design of the NCL30001 and reduce development cycle time. The design tool can be downloaded at www.onsemi.com. 

The electronic design tool allows the user to easily determine most of the system parameters of a single PFC stage The tool evaluates the power stage as well as the frequency response of the system. 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package**|**Shipping**†|
|NCL30001DR2G|SO−16<br>(Pb−Free)|2500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**30** 

**NCL30001** 

## **PACKAGE DIMENSIONS** 

**==> picture [480 x 461] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOIC−16<br>CASE 751B−05<br>ISSUE K<br>− A− NOTES:<br>1. DIMENSIONING AND TOLERANCING PER ANSI<br>Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: MILLIMETER.<br>16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD<br>PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.<br>oe −B− P 8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>PROTRUSION.  ALLOWABLE DAMBAR PROTRUSION<br>1 8 yy 0.25 (0.010) M B [S] SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIAL CONDITION.<br>MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>G A 9.80 10.00 0.386 0.393<br>B 3.80 4.00 0.150 0.157<br>C 1.35 1.75 0.054 0.068<br>K R X 45 F DF 0.350.40 0.491.25 0.0140.016 0.0190.049<br>G 1.27 BSC 0.050 BSC<br>J 0.19 0.25 0.008 0.009<br>C K 0.10 0.25 0.004 0.009<br>M 0 7 0 7<br>−T− SEATING P 5.80 6.20 0.229 0.244<br>PLANE M J R 0.25 0.50 0.010 0.019<br>D 16 PL<br>0.25 (0.010) M T B S A [S]<br>SOLDERING FOOTPRINT*<br>8X<br>6.40<br>16X 1.12<br>rt 1 16<br>16X<br>0.58 | 5<br>1.27<br>PITCH<br>=F<br>— 8 9 =a<br>DIMENSIONS: MILLIMETERS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


Soft−Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC). ENERGY STAR and the ENERGY STAR mark are registered U.S. marks. 

ON Semiconductor and the         are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf.  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

**LITERATURE FULFILLMENT** : **N. American Technical Support** : 800−282−9855 Toll Free **ON Semiconductor Website** : **www.onsemi.com** Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA **Europe, Middle East and Africa Technical Support: Order Literature** : http://www.onsemi.com/orderlit **Phone** : 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 **Fax** : 303−675−2176 or 800−344−3867 Toll Free USA/Canada **Japan Customer Focus Center** For additional information, please contact your local **Email** : orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative 

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