MPF300T-FCG484I.

FPGA, 244 I/O, 500MHZ, FCBGA-484

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: MICROCHIP
Product type: FPGAs
FPGA Type:-; No. of Logic Cells:300000Logic Cells; IC Case / Package:FCBGA; No. of Pins:484Pins; Speed Grade:-; No.of User I/Os:244I/O s; Process Technology:28nm (CMOS)
MSL: MSL 3 - 168 hours
SVHC: No SVHC (04-Feb-2026)
FPGA Type: -
No. of Pins: 484Pins
No. of I/O's: 244I/O's
Qualification: -
No.of User I/Os: 244I/O's
No. of Macrocells: 300000Macrocells
No. of Logic Cells: 300000Logic Cells
Delivery and price
Units per pack	25
Price	292.2 €
Current stock	10+
Lead time	30 days
Datasheet
## **DS0141** 

# **PolarFire Datasheet** 

**December 2019** 

Contents 

## **Contents** 

|1 Revision History.................................................................................................................................1|1 Revision History.................................................................................................................................1|
|---|---|
||1.1 Revision 1.7.........................................................................................................................................................1|
||1.2 Revision 1.6.........................................................................................................................................................1|
||1.3 Revision 1.5.........................................................................................................................................................2|
||1.4 Revision 1.4.........................................................................................................................................................2|
||1.5 Revision 1.3.........................................................................................................................................................2|
||1.6 Revision 1.2.........................................................................................................................................................2|
||1.7 Revision 1.1.........................................................................................................................................................2|
||1.8 Revision 1.0.........................................................................................................................................................2|
|2 Overview............................................................................................................................................3|2 Overview............................................................................................................................................3|
|3|References.........................................................................................................................................4|
|4 Device Offering..................................................................................................................................5|4 Device Offering..................................................................................................................................5|
|5 Silicon and Libero Tool Status............................................................................................................6|5 Silicon and Libero Tool Status............................................................................................................6|
|6 DC Characteristics..............................................................................................................................8|6 DC Characteristics..............................................................................................................................8|
||6.1 Absolute Maximum Rating.................................................................................................................................8|
||6.2 Recommended Operating Conditions.................................................................................................................9|
||6.2.1 DC Characteristics over Recommended Operating Conditions..........................................................11|
||6.2.2 Maximum Allowed Overshoot and Undershoot................................................................................12|
||6.3 Input and Output..............................................................................................................................................17|
||6.3.1 DC Input and Output Levels...............................................................................................................17|
||6.3.2 Differential DC Input and Output Levels............................................................................................19|
||6.3.3 Complementary Differential DC Input and Output Levels.................................................................23|
||6.3.4 HSIO On-Die Termination...................................................................................................................26|
||6.3.5 GPIO On-Die Termination..................................................................................................................27|
|7 AC Switching Characteristics............................................................................................................29|7 AC Switching Characteristics............................................................................................................29|
||7.1 I/O Standards Specifications.............................................................................................................................29|
||7.1.1 Input Delay Measurement Methodology Maximum PHY Rate for Memory Interface IP..................29|
||7.1.2 Output Delay Measurement Methodology.......................................................................................33|
||7.1.3 Input Buffer Speed.............................................................................................................................37|
||7.1.4 Output Buffer Speed..........................................................................................................................40|
||7.1.5 Maximum PHY Rate for Memory Interface IP....................................................................................42|
||7.1.6 User I/O Switching Characteristics.....................................................................................................43|
||7.2 Clocking Specifications......................................................................................................................................49|
||7.2.1 Clocking..............................................................................................................................................49|
||7.2.2 PLL......................................................................................................................................................50|
||7.2.3 DLL.....................................................................................................................................................52|
||7.2.4 RC Oscillators.....................................................................................................................................54|
||7.3 Fabric Specifications.........................................................................................................................................55|
||7.3.1 Math Blocks.......................................................................................................................................55|
||7.3.2 SRAM Blocks......................................................................................................................................56|
||7.4 Transceiver Switching Characteristics...............................................................................................................58|
||7.4.1 Transceiver Performance...................................................................................................................58|
||7.4.2 Transceiver Reference Clock Performance.........................................................................................59|
||7.4.3 Transceiver Reference Clock I/O Standards.......................................................................................60|



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Contents 

**==> picture [456 x 658] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|7.4.4 Transmitter Performance...................................................................................................................61|
|7.4.5 Receiver Performance........................................................................................................................68|
|7.4.6 Transceiver and Receiver Return Loss Characteristics ......................................................................72|
|7.5 Transceiver Protocol Characteristics.................................................................................................................73|
|7.5.1 PCI Express.........................................................................................................................................73|
|7.5.2 Interlaken...........................................................................................................................................74|
|7.5.3 10GbE (10GBASE-R and 10GBASE-KR)...............................................................................................74|
|7.5.4 1GbE (1000BASE-X) ...........................................................................................................................75|
|7.5.5 SGMII and QSGMII.............................................................................................................................75|
|7.5.6 CPRI....................................................................................................................................................76|
|7.5.7|JESD204B...........................................................................................................................................76|
|7.5.8 Display Port........................................................................................................................................77|
|7.5.9|Serial|RapidIO....................................................................................................................................77|
|7.5.10 SDI....................................................................................................................................................78|
|7.5.11|OTN..................................................................................................................................................78|
|7.5.12 Fiber Channel...................................................................................................................................79|
|7.5.13 HiGig and HiGig+..............................................................................................................................80|
|7.5.14|HiGig|II.............................................................................................................................................80|
|7.5.15 Firewire IEEE 1394...........................................................................................................................80|
|7.6 Non-Volatile Characteristics..............................................................................................................................80|
|7.6.1 FPGA Programming Cycle and Retention...........................................................................................80|
|7.6.2 FPGA Programming Time...................................................................................................................81|
|7.6.3 FPGA Bitstream Sizes.........................................................................................................................82|
|7.6.4|Digest|Cycles......................................................................................................................................83|
|7.6.5|Digest|Time........................................................................................................................................84|
|7.6.6|Zeroization|Time................................................................................................................................85|
|7.6.7 Verify Time.........................................................................................................................................88|
|7.6.8|Authentication|Time..........................................................................................................................90|
|7.6.9|Secure|NVM|Performance.................................................................................................................90|
|7.6.10 Secure NVM Programming Cycles....................................................................................................91|
|7.7|System|Services................................................................................................................................................91|
|7.7.1 System Services Throughput Characteristics.....................................................................................91|
|7.8|Fabric|Macros...................................................................................................................................................93|
|7.8.1 UJTAG Switching Characteristics........................................................................................................93|
|7.8.2 UJTAG_SEC Switching Characteristics................................................................................................94|
|7.8.3 USPI Switching Characteristics...........................................................................................................94|
|7.8.4|Tamper|Detectors..............................................................................................................................95|
|7.8.5 System Controller Suspend Switching Characteristics.......................................................................97|
|7.8.6 Dynamic Reconfiguration Interface...................................................................................................98|
|7.8.7 User Voltage Detector Characteristics...............................................................................................98|
|7.9 Power-Up to Functional Timing........................................................................................................................99|
|7.9.1 Power-On (Cold) Reset Initialization Sequence.................................................................................99|
|7.9.2 Warm Reset Initialization Sequence................................................................................................100|
|7.9.3 Power-On Reset Voltages.................................................................................................................100|
|7.9.4 User Design Dependence of Power-Up Times ................................................................................101|
|7.9.5 Cold Reset to Fabric and I/Os (Low Speed) Functional....................................................................101|
|7.9.6 Warm Reset to Fabric and I/Os (Low Speed) Functional.................................................................102|
|7.9.7 Miscellaneous Initialization Parameters..........................................................................................102|
|7.9.8|I/O|Calibration.................................................................................................................................103|
|7.10|Dedicated|Pins..............................................................................................................................................103|
|7.10.1 JTAG Switching Characteristics.......................................................................................................104|
|7.10.2 SPI|Switching|Characteristics.........................................................................................................104|
|7.10.3 SmartDebug Probe Switching Characteristics................................................................................106|
|7.10.4 DEVRST_N Switching Characteristics.............................................................................................106|
|7.11 User Crypto...................................................................................................................................................107|

**----- End of picture text -----**<br>


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Contents 

|7.11.1 TeraFire 5200B Switching Characteristics......................................................................................107|7.11.1 TeraFire 5200B Switching Characteristics......................................................................................107|7.11.1 TeraFire 5200B Switching Characteristics......................................................................................107|
|---|---|---|
|7.11.2 TeraFire 5200B Throughput Characteristics...................................................................................107|7.11.2 TeraFire 5200B Throughput Characteristics...................................................................................107|7.11.2 TeraFire 5200B Throughput Characteristics...................................................................................107|



Microsemi Proprietary and Confidential. DS0141 Revision 1.7 

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Revision History 

## **1 Revision History** 

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. 

## **1.1 Revision 1.7** 

Revision 1.7 was published in December 2019. The following is a summary of changes. 

- Updated table PolarFire FPGA Silicon Status. Libero 12.2 now contains production timing and power for all devices. 

- Corrected footnote 5 in the table PolarFire Transceiver Reference Clock AC Requirements. 

- Corrected footnote in the table sNVM Programming Cycles vs. Retention Characteristics. 

- Added timing parameters to the table Master SPI Programming Time (IAP) and table Slave SPI Programming Time. 

- Added 270 mbps rates to the section SDI. 

- Added FireWire section. 

- Added footnotes to the following tables: 

   - Recommended Operating Conditions 

   - I/O Digital Receive Double Data Rate Switching Characteristics 

   - I/O Digital Transmit Single Data Rate Switching Characteristics 

   - I/O Digital Transmit Double Data Rate Switching Characteristics 

   - HSIO Maximum Input Buffer Speed 

   - HSIO Maximum Output Buffer Speed 

   - GPIO Maximum Output Buffer Speed 

   - Programmable Delay 

- Added MIPI data rates to the following tables: 

   - GPIO Maximum Input Buffer Speed 

   - GPIO Maximum Output Buffer Speed 

- Updated MIPIE25 output DC specifications. 

## **1.2 Revision 1.6** 

Revision 1.6 was published in June 2019. The following is a summary of changes. 

- The parameter RX_DDRX_B_G_FA (for Video7 applications) was added. For more information, see table I/O Digital Receive Double-Data Rate Switching Characteristics. 

- I/O CDR switching characteristics were added. For more information, see table I/O CDR Switching Characteristics. 

- High-speed I/O clock skew with bridging was added. For more information, see table High-Speed I/O Clock Characteristics (–40 °C to 100 °C). 

- PCS and PMA minimum reset pulse widths were added. For more information, see table PolarFire Transceiver and TXPLL Performance. 

- Auto adaptive calibration was added to CDR lock times, Burst Mode Receiver (BMR) high-gain lock time, and BMR high-gain state time. For more information, see table PolarFire Transceiver Receiver Characteristics. 

- Fiber channel rates were corrected. For more information, see table Fiber Channel. 

- HiGig and HiGig+ specifications were updated. For more information, see table HiGig and HiGig+. 

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Revision History 

- HiGig II specifications were updated. For more information, see table HiGigII. 

- The DEVRST_N parameter was correctly classified as ramp time. For more information, see section Dedicated Pins. 

- Transmitter and receiver return loss characteristics were added. For more information, see section Transceiver Switching Characteristics. 

- Voltage detector specifications were added and the voltage glitch detector was removed. For more information, see section User Voltage Detector Characteristics. 

## **1.3 Revision 1.5** 

- All tables have been reviewed and updated to reflect production silicon characteristics for the 200T, 200TL, 200TS, 200TLS, 100T, 100TL, 100TS, and 100TLS devices in all packages, speed grades, and temperature grades. 

- The maximum transceiver reference clock input rate was changed from 800 MHz to 400 MHz due to a typo in version 1.4. For more information, see table PolarFire Transceiver Reference Clock AC Requirements. 

## **1.4 Revision 1.4** 

Revision 1.4 was published September 2018. The following is a summary of changes. 

- All tables have been reviewed and updated to reflect production silicon characteristics for the 300T, 300TL, 300TS, and 300TLS devices in all packages, speed grades, and temperature grades. 

## **1.5 Revision 1.3** 

Revision 1.3 was published in June 2018. The following is a summary of changes. 

- The System Services section was updated. 

- The Non-Volatile Characteristics section was updated. 

- The Fabric Macros section was updated. 

- The Transceiver Switching Characteristics section was updated. 

## **1.6 Revision 1.2** 

Revision 1.2 was published in June 2018. The following is a summary of changes. 

- The datasheet has moved to preliminary status. Every table has been updated. 

## **1.7 Revision 1.1** 

Revision 1.1 was published in August 2017. The following is a summary of changes. 

- LVDS specifications changed to 1.25G. 

- LVDS18, LVDS25/LVDS33, and LVDS25 specifications changed to 800 Mbps. 

- A note was added indicting a zeroization cycle counts as a programming cycle. 

- A note was added defining power down conditions for programming recovery conditions. 

## **1.8 Revision 1.0** 

Revision 1.0 was the first publication of this document. 

Microsemi Proprietary and Confidential. DS0141 Revision 1.7 

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Overview 

## **2 Overview** 

This datasheet describes PolarFire[® ] FPGA device characteristics with industrial temperature range (–40 °C to 100 °C TJ) and extended commercial temperature range (0 °C to 100 °C TJ). The devices are provided with a standard speed grade (STD) and a –1 speed grade with higher performance. The FPGA core supply VDD can operate at 1.0 V for lower-power or 1.05 V for higher performance. Similarly, the transceiver core supply VDDA can also operate at 1.0 V or 1.05 V. Users select the core operating voltage while creating the Libero project. 

Microsemi Proprietary and Confidential. DS0141 Revision 1.7 

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References 

## **3 References** 

The following documents are recommended references. For more information about PolarFire static and dynamic power data, see the PolarFire Power Estimator Spreadsheet. 

- PO0137: PolarFire FPGA Product Overview 

- ER0217: PolarFire FPGA Pre-Production Device Errata 

- UG0722: PolarFire FPGA Packaging and Pin Descriptions User Guide 

- UG0726: PolarFire FPGA Board Design User Guide 

- UG0686: PolarFire FPGA User I/O User Guide 

- UG0680: PolarFire FPGA Fabric User Guide 

- UG0714: PolarFire FPGA Programming User Guide 

- UG0684: PolarFire FPGA Clocking Resources User Guide 

- UG0687: PolarFire FPGA 1G Ethernet Solutions User Guide 

- UG0727: PolarFire FPGA 10G Ethernet Solutions User Guide 

- UG0748: PolarFire FPGA Low Power User Guide 

- UG0676: PolarFire FPGA DDR Memory Controller User Guide 

- UG0743: PolarFire FPGA Debugging User Guide 

- UG0725: PolarFire FPGA Device Power-Up and Resets User Guide 

- UG0677: PolarFire FPGA Transceiver User Guide 

- UG0685: PolarFire FPGA PCI Express User Guide 

- UG0753: PolarFire FPGA Security User Guide 

- UG0752: PolarFire FPGA Power Estimator User Guide 

Microsemi Proprietary and Confidential. DS0141 Revision 1.7 

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Device Offering 

## **4 Device Offering** 

The following table lists the PolarFire FPGA device options using the MPF300T as an example. The MPF100T, MPF200T, and MPF500T device densities have identical offerings. 

## **Table 1 • PolarFire FPGA Device Options** 

|**Device Options**|**Extended Com-**<br>**mercial**<br>**0 °C–100 °C**|**Industrial**<br>**–40 °C–100 °C**|**STD**|**–1**|**Transceivers T**|**Lower S-**<br>**taticPow-**<br>**er L**|**Data Security S**|
|---|---|---|---|---|---|---|---|
|MPF300T|Yes|Yes|Yes|Yes|Yes|||
|MPF300TL|Yes|Yes|Yes||Yes|Yes||
|MPF300TS||Yes|Yes|Yes|Yes||Yes|
|MPF300TLS||Yes|Yes||Yes|Yes|Yes|



Microsemi Proprietary and Confidential. DS0141 Revision 1.7 

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Silicon and Libero Tool Status 

## **5 Silicon and Libero Tool Status** 

There are three status levels: 

- Advanced—initial estimated information based on simulations 

- Preliminary—information based on simulation and/or initial characterization 

- Production—final production data 

The following tables list the status of the PolarFire FPGA silicon and Libero Timing and Power tool. 

## **Table 2 • PolarFire FPGA Silicon Status** 

|**Product**|||**Silicon**|
|---|---|---|---|
|MPF100T, TS, TL, TLS|MPF100T, TS, TL, TLS|MPF100T, TS, TL, TLS|Production<br>MPF100T, TS, TL, TLS|
|MPF200T, TS, TL, TLS|MPF200T, TS, TL, TLS|MPF200T, TS, TL, TLS|Production<br>MPF200T, TS, TL, TLS|
|MPF300T, TS, TL, TLS|MPF300T, TS, TL, TLS|MPF300T, TS, TL, TLS|Production<br>MPF300T, TS, TL, TLS|
|MPF500T, TS, TL, TLS|MPF500T, TS, TL, TLS|MPF500T, TS, TL, TLS|Production<br>MPF500T, TS, TL, TLS|



## **Table 3 • PolarFire FPGA Tool Status** 

|**Product**|**Status**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|
|---|---|---|---|---|---|---|---|---|---|
|||**Timing**||||**Power**||||
|||**Extended Commercial**||**Industrial**||**Extended Commercial**||**Industrial**||
|||**STD**|**–1**|**STD**|**–1**|**STD**|**–1**|**STD**|**–1**|
|MPF100T,<br>TS, TL, TLS|Prelimi-<br>nary|12.0|12.0|12.0|12.0|12.0|12.0|12.0|12.0|
||Produc-<br>tion Vdd =<br>1.0 V|12.1|12.1|12.1|12.1|12.1|12.1|12.1|12.1|
||Produc-<br>tion Vdd =<br>1.05 V|12.2|12.2|12.2|12.2|12.2|12.2|12.2|12.2|
|MPF200T,<br>TS, TL, TLS|Prelimi-<br>nary|12.0|12.0|12.0|12.0|12.0|12.0|12.0|12.0|
||Produc-<br>tion Vdd =<br>1.0 V|12.1|12.1|12.1|12.1|12.1|12.1|12.1|12.1|
||Produc-<br>tion Vdd =<br>1.05 V|12.2|12.2|12.2|12.2|12.2|12.2|12.2|12.2|
|MPF300T,<br>TS, TL, TLS|Prelimi-<br>nary|12.0|12.0|12.0|12.0|12.0|12.0|12.0|12.0|



Microsemi Proprietary and Confidential. DS0141 Revision 1.7 

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Silicon and Libero Tool Status 

|**Product**|**Status**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|**Libero Version**|
|---|---|---|---|---|---|---|---|---|---|
|||**Timing**||||**Power**||||
|||**Extended Commercial**||**Industrial**||**Extended Commercial**||**Industrial**||
|||**STD**|**–1**|**STD**|**–1**|**STD**|**–1**|**STD**|**–1**|
||Produc-<br>tion Vdd =<br>1.0 V|12.1|12.0|12.1|12.1|12.1|12.1|12.1|12.1|
||Produc-<br>tion Vdd =<br>1.05 V|12.2|12.2|12.2|12.2|12.2|12.2|12.2|12.2|
|MPF500T,<br>TS, TL, TLS|Prelimi-<br>nary|12.0|12.0|12.0|12.0|12.0|12.0|12.0|12.0|
||Produc-<br>tion Vdd =<br>1.0 V|12.2|12.2|12.2|12.2|12.2|12.2|12.2|12.2|
||Produc-<br>tion Vdd =<br>1.05 V|12.2|12.2|12.2|12.2|12.2|12.2|12.2|12.2|



Microsemi Proprietary and Confidential. DS0141 Revision 1.7 

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DC Characteristics 

## **6 DC Characteristics** 

This section lists the DC characteristics of the PolarFire FPGA device. 

## **6.1 Absolute Maximum Rating** 

The following table lists the absolute maximum ratings for PolarFire devices. 

## **Table 4 • Absolute Maximum Rating** 

|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|FPGAcorepowersupply|VDD|–0.5|1.13|V|
|Transceiver Tx and Rx<br>lanes supply|VDDA|–0.5|1.13|V|
|Programming and HSIO<br>receiver supply|VDD18|–0.5|2.0|V|
|FPGA core and FPGA PL-<br>L high-voltage supply|VDD25|–0.5|2.7|V|
|Transceiver PLL high-<br>voltage supply|VDDA25|–0.5|2.7|V|
|Transceiver reference<br>clock supply|VDD_XCVR_CLK|–0.5|3.6|V|
|Global VREFfor<br>transceiver reference<br>clocks|XCVRVREF|–0.5|3.6|V|
|HSIO DC I/O supply2|VDDIx|–0.5|2.0|V|
|GPIO DC I/O supply2|VDDIx|–0.5|3.6|V|
|Dedicated I/O DC supply<br>for JTAG and SPI|VDDI3|–0.5|3.6|V|
|GPIO auxiliary power<br>supply for I/O bank x2|VDDAUXx|–0.5|3.6|V|
|Maximum DC input<br>voltage on GPIO|VIN|–0.5|3.8|V|
|Maximum DC input<br>voltage on HSIO|VIN|–0.5|2.2|V|
|Transceiver receiver ab-<br>solute input voltage|Transceiver VIN|–0.5|1.26|V|
|Transceiver reference<br>clock absolute input<br>voltage|Transceiver REFCLK VIN|–0.5|3.6|V|



Microsemi Proprietary and Confidential. DS0141 Revision 1.7 

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DC Characteristics 

|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|Storage temperature<br>(ambient)1|TSTG|–65|150|°C|
|Junction temperature1|TJ|–55|135|°C|
|Maximum soldering<br>temperature RoHS|TSOLROHS||260|°C|



**1.** See FPGA Programming Cycles vs Retention Characteristics for retention time vs temperature. The total time used in calculating the device retention includes the device operating temperature time and temperature during storage time. 

**2.** The power supplies for a given I/O bank x are shown as VDDIx and VDDAUXx. 

## **6.2 Recommended Operating Conditions** 

The following table lists the recommended operating conditions. 

## **Table 5 • Recommended Operating Conditions** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|FPGA core sup-<br>ply at 1.0 V<br>mode1, 6|VDD|0.97|1.00|1.03|V||
|FPGA core sup-<br>ply at 1.05 V<br>mode1, 6|VDD|1.02|1.05|1.08|V||
|Transceiver TX<br>and RX lanes<br>supply (1.0 V<br>mode)6, 7|VDDA|0.97|1.00|1.03|V|When all lane<br>rates are 10.312<br>5 Gbps or less.1|
|Transceiver TX<br>and RX lanes<br>supply (1.05 V<br>mode)6|VDDA|1.02|1.05|1.08|V|Must when any<br>lane rate is<br>greater than 10.<br>3125 Gbps. L-<br>ane rates 10.31<br>25 Gbps or less<br>may also be<br>powered in 1.05<br>V mode.1|
|Programming<br>and HSIO receiv-<br>er supply6|VDD18|1.71|1.80|1.89|V||
|FPGA core and<br>FPGA PLL high-<br>voltage supply6|VDD25|2.425|2.50|2.575|V||
|Transceiver PLL<br>high-voltage<br>supply6|VDDA25|2.425|2.50|2.575|V||



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DC Characteristics 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|Transceiver ref-<br>erence clock<br>supply6, 7|VDD_XCVR_CLK|3.135|3.3|3.465|V|3.3 V nominal|
|||2.375|2.5|2.625|V|2.5 V nominal|
|Global VREFfor<br>transceiverrefer-<br>ence clocks3|XCVRVREF|Ground||VDD_XCVR_ CLK|V||
|HSIO DC I/O<br>supply6|VDDIx|1.14|Various|1.89|V|Allowed nomi-<br>nal options: 1.2<br>V, 1.35 V, 1.5 V,<br>and 1.8 V4, 5|
|GPIO DC I/O<br>supply6|VDDIx|1.14|Various|3.465|V|Allowed nomi-<br>nal options: 1.2<br>V, 1.5 V, 1.8 V, 2<br>.5 V, and 3.3 V2,<br>4, 5|
|Dedicated I/O<br>DC supply for JT-<br>AG and SPI (GPI-<br>O Bank 3)6|VDDI3|1.71|Various|3.465|V|Allowed nomi-<br>nal options: 1.8<br>V, 2.5 V, and 3.3<br>V|
|GPIO auxiliary<br>supply6|VDDAUXx|3.135|3.3|3.465|V|For I/O bank x<br>with VDDIx= 3.3<br>V nominal2, 4, 5|
|||2.375|2.5|2.625|V|For I/O bank x<br>with VDDIx= 2.5<br>V nominal or<br>lower2, 4, 5|
|Extended com-<br>mercial temper-<br>ature range|TJ|0||100|°C||
|Industrial tem-<br>perature range|TJ|–40||100|°C||
|Extended com-<br>mercialprogram-<br>ming tempera-<br>ture range|TPRG|0||100|°C||
|Industrial pro-<br>gramming tem-<br>perature range|TPRG|–40||100|°C||



**1.** VDD and VDDA can independently operate at 1.0 V or 1.05 V nominal. These supplies are not dynamically adjustable. 

**2.** For GPIO buffers where I/O bank is designated as bank number, if VDDIx is 2.5 V nominal or 3.3 V nominal, VDDAUXx must be connected to the VDDIx supply for that bank. If VDDIx for a given GPIO bank is <2.5 V nominal, VDDAUXx per I/O bank must be powered at 2.5 V nominal. 

**3.** XCVRVREF globally sets the reference voltage of the transceiver's single-ended reference clock input buffers. It is typically near VDD_XCVR _CLK/2 V but is allowed in the specified range. 

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DC Characteristics 

**4.** The power supplies for a given I/O bank x are shown as VDDIx and VDDAUXx. 

**5.** At power up and power down the VDDIx and VDDAUXx supply sequencing can cause signal glitches. Refer to UG0686: PolarFire FPGA I/O User Guide and UG0726: PolarFire FPGA Board Design User Guide for detailed explanation and recommended steps. 

**6.** The recommended power supply tolerances include DC offset of the supply plus any power supply ripple over the customer design frequencies of interest, as measured at the device package pins. An example for a valid power supply that meets the recommendations for the VDD supply is 1.0 V ±10 mV or 1.05 V ±10 mV for DC offset with an additional power supply ripple of ±20 mV for a total of 1.0 V ±30 mV or 1.05 V ±30 mV. 

**7.** Both VDDA and VDD_XCVR_CLK supplies must be powered when any of the transceivers are used. VDD_XCVR_CLK must power on within the I/O calibration time (as specified for the device in Libero). VDDA and VDD_XCVR_CLK must both then remain powered during operation. If VDDA needs to be powered down, VDD_XCVR_CLK must also be powered down. There is no required sequence for powering up or down VDDA and VDD_XCVR_CLK. 

## **6.2.1 DC Characteristics over Recommended Operating Conditions** 

The following table lists the DC characteristics over recommended operating conditions. 

**Table 6 • DC Characteristics over Recommended Operating Conditions** 

|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|
|Input pin capacitance1|CIN(GPIO)<br>Dedicated input pins||5.6|pf||
||CIN(HSIO)||2.8|pf||
|Input or output leakage current<br>per pin|IL(GPIO)||10|µA|I/O disabled, high—Z|
||IL(HSIO)||10|µA|I/O disabled, high—Z|
|Pad pull-up when VIN= 0|IPU|137|220|µA|VDDIx= 3.3 V|
|Pad pull-up when VIN= 0||102|166|µA|VDDIx= 2.5 V|
|Pad pull-up when VIN= 0||68|115|µA|VDDIx= 1.8 V|
|Pad pull-up when VIN= 0||51|88|µA|VDDIx= 1.5 V|
|Pad pull-up when VIN= 0||29|73|µA|VDDIx= 1.35 V|
|Pad pull-up when VIN= 0||16|46|µA|VDDIx= 1.2 V|
|Pad pull-down when VIN= 3.3<br>V (GPIO only)|IPD|65|187|µA|VDDIx= 3.3 V|
|Pad pull-down when VIN= 2.5<br>V (GPIO only)||63|160|µA|VDDIx= 2.5 V|
|Pad pull-down when VIN= 1.8<br>V||60|117|µA|VDDIx= 1.8 V|
|Pad pull-down when VIN= 1.5<br>V||57|95|µA|VDDIx= 1.5 V|



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**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Symbol|Min|Max|Unit|Condition|
|Pad pull-down when VIN = 1.35|52|86|µA|VDDIx = 1.35 V|
|V|
|Pad pull-down when VIN = 1.2|47|79|µA|VDDIx = 1.2 V|
|V|

**----- End of picture text -----**<br>


**1.** Represents the die input capacitance at the pad (not the package). 

**Table 7 • Minimum and Maximum Rise and Fall times** 

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**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|Parameter|Symbol|Min|Max|Unit|Maximum fre-|Condition|
|quency|
|Input rise time|[1,4]|TRISE|200 ps|[2,3]|10% bit period|ps|100 KHz|Not to exceed 1|
|Input fall time|[1,4]|TFALL|μs|
|12.5% bit period|ps|400 KHz|Not to exceed 30|
|0 ns|
|20% bit period|ps|50 MHz|Not to exceed 50|
|ns|
|4|ns|800 MHz|

**----- End of picture text -----**<br>


**1.** Voltage ramp must be monotonic. For single-ended IO standards, input rise time is specified from 10%–90% of VDDIx and input fall time is specified from 90%–10% of VDDIx. For voltage referenced and differential IO configurations, ramp times must always comply with I/O standard requirements to ensure compliance. 

**2.** Input slew rates must be controlled to never exceed PAD overshoot/undershoot requirements. Input pad overshoot and undershoot specifications are shown in section Maximum Allowed Overshoot and Undershoot. 

**3.** Rise and fall times in this table are for unterminated inputs. When inputs are terminated, minimum ramp time is not restricted. Recommended minimum ramp time is 25% of bit period, not to exceed a rate of 5 V/ns. 

**4.** Ramp times must not exceed I/O standard requirements to ensure compliance. 

## **6.2.2 Maximum Allowed Overshoot and Undershoot** 

The following table lists the maximum AC input voltage (VIN) overshoot duration for HSIO. 

During transitions, input signals may overshoot and undershoot the voltage listed as follows. Input currents must be limited to less than 100 mA per latch-up specifications. 

The maximum overshoot duration is specified as a high-time percentage over the lifetime of the device. A DC signal is equivalent to 100% of the duty-cycle. 

**Table 8 • Maximum Overshoot During Transitions for HSIO** 

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|||
|---|---|
|AC (VIN) Overshoot Duration as % at TJ = 100 °C|Condition (V)|
|100|1.8|
|100|1.85|
|100|1.9|

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|||
|---|---|
|AC (VIN) Overshoot Duration as % at TJ = 100 °C|Condition (V)|
|100|1.95|
|100|2|
|100|2.05|
|100|2.1|
|100|2.15|
|100|2.2|
|90|2.25|
|30|2.3|
|7.5|2.35|
|1.9|2.4|

**----- End of picture text -----**<br>


Note: Overshoot level is for VDDI at 1.8 V. 

The following table lists the maximum AC input voltage (VIN) undershoot duration for HSIO. 

## **Table 9 • Maximum Undershoot During Transitions for HSIO** 

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|||
|---|---|
|AC (VIN) Undershoot Duration as % at TJ = 100 °C|Condition (V)|
|100|–0.05|
|100|–0.1|
|100|–0.15|
|100|–0.2|
|100|–0.25|
|100|–0.3|
|100|–0.35|
|100|–0.4|
|44|–0.45|
|14|–0.5|
|4.8|–0.55|
|1.6|–0.6|

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The following table lists the maximum AC input voltage (VIN) overshoot duration for GPIO. 

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**Table 10 • Maximum Overshoot During Transitions for GPIO** 

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|||
|---|---|
|AC (VIN) Overshoot Duration as % at TJ = 100 °C|Condition (V)|
|100|3.8|
|100|3.85|
|100|3.9|
|100|3.95|
|70|4|
|50|4.05|
|33|4.1|
|22|4.15|
|14|4.2|
|9.8|4.25|
|6.5|4.3|
|4.4|4.35|
|3|4.4|
|2|4.45|
|1.4|4.5|
|0.9|4.55|
|0.6|4.6|

**----- End of picture text -----**<br>


Note: Overshoot level is for VDDI at 3.3 V. 

The following table lists the maximum AC input voltage (VIN) undershoot duration for GPIO. 

**Table 11 • Maximum Undershoot During Transitions for GPIO** 

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|||
|---|---|
|AC (VIN) Undershoot Duration as % at TJ = 100 °C|Condition (V)|
|100|–0.5|
|100|–0.55|
|100|–0.6|
|100|–0.65|
|100|–0.7|
|100|–0.75|
|100|–0.8|

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|||
|---|---|
|AC (VIN) Undershoot Duration as % at TJ = 100 °C|Condition (V)|
|100|–0.85|
|100|–0.9|
|100|–0.95|
|100|–1|
|100|–1.05|
|100|–1.1|
|100|–1.15|
|100|–1.2|
|69|–1.25|
|45|–1.3|

**----- End of picture text -----**<br>


## **6.2.2.1 Power Supply Ramp Times** 

The following table lists the allowable power-up ramp times. Times shown correspond to the ramp of the supply from 0 V to the minimum recommended voltage as specified in the section Recommended Operating Conditions. All supplies must rise and fall monotonically. 

**Table 12 • Power Supply Ramp Times** 

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||||||
|---|---|---|---|---|
|Parameter|Symbol|Min|Max|Unit|
|FPGA core supply|VDD|0.2|50|ms|
|Transceiver core supply|VDDA|0.2|50|ms|
|Must connect to 1.8 V|VDD18|0.2|50|ms|
|supply|
|Must connect to 2.5 V|VDD25|0.2|50|ms|
|supply|
|Must connect to 2.5 V|VDDA25|0.2|50|ms|
|supply|
|HSIO bank I/O power|VDDI[0,1,6,7]|0.2|50|ms|
|supplies|
|GPIO bank I/O power|VDDI[2,4,5]|0.2|50|ms|
|supplies|
|Bank 3 dedicated I/O|VDDI3|0.2|50|ms|
|buffers (GPIO)|
|GPIO bank auxiliary|VDDAUX[2,4,5]|0.2|50|ms|
|power supplies|

**----- End of picture text -----**<br>


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|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|Transceiver reference<br>clock supply|VDD_XCVR_CLK|0.2|50|ms|
|Global VREFfor<br>transceiver reference<br>clocks|XCVRVREF|0.2|50|ms|



Note: For proper operation of programming recovery mode, if a VDD supply brownout occurs during programming, a minimum supply ramp down time for only the VDD supply is recommended to be 10 ms or longer by using a programmable regulator or on-board capacitors. 

## **6.2.2.2 Hot Socketing** 

The following table lists the hot socketing DC characteristics over recommended operating conditions. 

## **Table 13 • Hot Socketing DC Characteristics over Recommended Operating Conditions** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|Current per<br>transceiver Rx<br>input pin (P or<br>Nsingle-ended)1<br>, 2|XCVRRX_HS|||±4|mA|VDDA= 0 V|
|Current per<br>transceiver Tx<br>output pin (P or<br>Nsingle-ended)3|XCVRTX_HS|||±10|mA|VDDA= 0 V|
|Current per<br>transceiverrefer-<br>ence clock input<br>pin (P or N sin-<br>gle-ended)4|XCVRREF_HS|||±1|mA|VDD_XCVR_CLK= 0<br>V|
|Current per GPI-<br>O pin (P or N<br>single-ended)5|IGPIO_HS|||±1|mA|VDDIx= 0 V|
|Current per HSI-<br>O pin (P or N<br>single-ended)||||||Hot socketing is<br>not supported<br>in HSIO.|



**1.** Assumes device is powered-down, all supplies are grounded, AC-coupled interface, and input pin pairs are driven by a CML driver at the maximum amplitude (1 V pk–pk) that is toggling at any rate with PRBS7 data. 

**2.** Each P and N transceiver input has less than the specified maximum input current. 

**3.** Each P and N transceiver output is connected to a 40 Ω resistor (50 Ω CML termination—20% tolerance) to the maximum allowed output voltage (VDDAmax + 0.3 V = 1.4 V) through an AC-coupling capacitor with all PolarFire device supplies grounded. This shows the current for a worst-case DC coupled interface. As an AC-coupled interface, the output signal will settle at ground and no hot socket current will be seen. 

**4.** VDD_XCVR_CLK is powered down and the device is driven to –0.3 V < VIN < VDD_XCVR_CLK. 

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**5.** VDDIx is powered down and the device is driven to –0.3 V < VIN < GPIO VDDImax. 

Note: The following dedicated pins do not support hot socketing: TMS, TDI, TRSTB, and DEVRST_N. Weak pull-up (as specified in GPIO) is always enabled. 

## **6.3 Input and Output** 

The following section describes DC I/O levels, differential and complementary differential DC I/O levels, HSIO and GPIO on-die termination specifications, and LVDS specifications. 

## **6.3.1 DC Input and Output Levels** 

The following tables list the DC I/O levels. 

## **Table 14 • DC Input Levels** 

|**I/O Standard**|**VDDI**<br>**Min (V)**|**VDDI**<br>**Typ (V)**|**VDDI**<br>**Max (V)**|**VIL**<br>**Min (V)**|**VIL**<br>**Max (V)**|**VIH**<br>**Min (V)**|**VIH**<br>**1**<br>**Max (V)**|
|---|---|---|---|---|---|---|---|
|PCI|3.15|3.3|3.45|–0.3|0.3 × VDDI|0.5 × VDDI|3.45|
|LVTTL|3.15|3.3|3.45|–0.3|0.8|2|3.45|
|LVCMOS33|3.15|3.3|3.45|–0.3|0.8|2|3.45|
|LVCMOS25|2.375|2.5|2.625|–0.3|0.7|1.7|2.625|
|LVCMOS18|1.71|1.8|1.89|–0.3|0.35 × VDDI|0.65 × VDDI|1.89|
|LVCMOS15|1.425|1.5|1.575|–0.3|0.35 × VDDI|0.65 × VDDI|1.575|
|LVCMOS12|1.14|1.2|1.26|–0.3|0.35 × VDDI|0.65 × VDDI|1.26|
|SSTL25I2|2.375|2.5|2.625|–0.3|VREF– 0.15|VREF+ 0.15|2.625|
|SSTL25II2|2.375|2.5|2.625|–0.3|VREF– 0.15|VREF+ 0.15|2.625|
|SSTL18I2|1.71|1.8|1.89|–0.3|VREF– 0.125|VREF+ 0.125|1.89|
|SSTL18II2|1.71|1.8|1.89|–0.3|VREF– 0.125|VREF+ 0.125|1.89|
|SSTL15I|1.425|1.5|1.575|–0.3|VREF– 0.1|VREF+ 0.1|1.575|
|SSTL15II|1.425|1.5|1.575|–0.3|VREF– 0.1|VREF+ 0.1|1.575|
|SSTL135I|1.283|1.35|1.418|–0.3|VREF– 0.09|VREF+ 0.09|1.418|
|SSTL135II|1.283|1.35|1.418|–0.3|VREF– 0.09|VREF+ 0.09|1.418|
|HSTL15I|1.425|1.5|1.575|–0.3|VREF– 0.1|VREF+ 0.1|1.575|
|HSTL15II|1.425|1.5|1.575|–0.3|VREF– 0.1|VREF+ 0.1|1.575|
|HSTL135I|1.283|1.35|1.418|–0.3|VREF– 0.09|VREF+ 0.09|1.418|
|HSTL135II|1.283|1.35|1.418|–0.3|VREF– 0.09|VREF+ 0.09|1.418|



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|**I/O Standard**|**VDDI**<br>**Min (V)**|**VDDI**<br>**Typ (V)**|**VDDI**<br>**Max (V)**|**VIL**<br>**Min (V)**|**VIL**<br>**Max (V)**|**VIH**<br>**Min (V)**|**VIH**<br>**1**<br>**Max (V)**|
|---|---|---|---|---|---|---|---|
|HSTL12I|1.14|1.2|1.26|–0.3|VREF– 0.1|VREF+ 0.1|1.26|
|HSTL12II|1.14|1.2|1.26|–0.3|VREF– 0.1|VREF+ 0.1|1.26|
|HSUL18I|1.71|1.8|1.89|–0.3|0.3 × VDDI|0.7 × VDDI|1.89|
|HSUL18II|1.71|1.8|1.89|–0.3|0.3 × VDDI|0.7 × VDDI|1.89|
|HSUL12I|1.14|1.2|1.26|–0.3|VREF– 0.1|VREF+ 0.1|1.26|
|POD12I|1.14|1.2|1.26|–0.3|VREF– 0.08|VREF+ 0.08|1.26|
|POD12II|1.14|1.2|1.26|–0.3|VREF– 0.08|VREF+ 0.08|1.26|



**1.** GPIO VIH max is 3.45 V with PCI clamp diode turned off regardless of mode, that is, over-voltage tolerant. 

**2.** For external stub-series resistance. This resistance is on-die for GPIO. 

Note: 3.3 V and 2.5 V are only supported in GPIO banks. 

## **Table 15 • DC Output Levels** 

|**I/O Standard**|**VDDI**<br>**Min (V)**|**VDDI**<br>**Typ (V)**|**VDDI**<br>**Max (V)**|**VOL**<br>**Max (V)**|**VOH**<br>**Min (V)**|**IOL**<br>**2,6**<br>**mA**|**IOH**<br>**2,6**<br>**mA**|
|---|---|---|---|---|---|---|---|
|PCI1|3.15|3.3|3.45|0.1 × VDDI|0.9 × VDDI|1.5|0.5|
|LVTTL|3.15|3.3|3.45|0.4|2.4|Refer to note<br>2|8.1|
|LVCMOS33|3.15|3.3|3.45|0.4|VDDI– 0.4|||
|LVCMOS25|2.375|2.5|2.625|0.4|VDDI– 0.4|||
|LVCMOS18|1.71|1.8|1.89|0.45|VDDI– 0.45|||
|LVCMOS15|1.425|1.5|1.575|0.25 × VDDI|0.75 × VDDI|||
|LVCMOS12|1.14|1.2|1.26|0.25 × VDDI|0.75 × VDDI|||
|SSTL25I3|2.375|2.5|2.625|VTT– 0.608|VTT+ 0.608|8.1||
|SSTL25II3|2.375|2.5|2.625|VTT– 0.810|VTT+ 0.810|16.2|16.2|
|SSTL18I3|1.71|1.8|1.89|VTT– 0.603|VTT+ 0.603|6.7|6.7|
|SSTL18II3|1.71|1.8|1.89|VTT– 0.603|VTT+ 0.603|13.4|13.4|
|SSTL15I4|1.425|1.5|1.575|0.2 × VDDI|0.8 × VDDI|VOL/40|(VDDI– VOH)/4<br>0|
|SSTL15II4|1.425|1.5|1.575|0.2 × VDDI|0.8 × VDDI|VOL/34|(VDDI– VOH)/3<br>4|
|SSTL135I4|1.283|1.35|1.418|0.2 × VDDI|0.8 × VDDI|VOL/40|(VDDI– VOH)/4<br>0|



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|**I/O Standard**|**VDDI**<br>**Min (V)**|**VDDI**<br>**Typ (V)**|**VDDI**<br>**Max (V)**|**VOL**<br>**Max (V)**|**VOH**<br>**Min (V)**|**IOL**<br>**2,6**<br>**mA**|**IOH**<br>**2,6**<br>**mA**|
|---|---|---|---|---|---|---|---|
|SSTL135II4|1.283|1.35|1.418|0.2 × VDDI|0.8 × VDDI|VOL/34|(VDDI– VOH)/3<br>4|
|HSTL15I|1.425|1.5|1.575|0.4|VDDI– 0.4|8|8|
|HSTL15II|1.425|1.5|1.575|0.4|VDDI– 0.4|16|16|
|HSTL135I4|1.283|1.35|1.418|0.2 × VDDI|0.8 × VDDI|VOL/50|(VDDI– VOH)/5<br>0|
|HSTL135II4|1.283|1.35|1.418|0.2 × VDDI|0.8 × VDDI|VOL/25|(VDDI– VOH)/2<br>5|
|HSTL12I4|1.14|1.2|1.26|0.1 × VDDI|0.9 × VDDI|VOL/50|(VDDI– VOH)/5<br>0|
|HSTL12II4|1.14|1.2|1.26|0.1 × VDDI|0.9 × VDDI|VOL/25|(VDDI– VOH)/2<br>5|
|HSUL18I4|1.71|1.8|1.89|0.1 × VDDI|0.9 × VDDI|VOL/55|(VDDI– VOH)/5<br>5|
|HSUL18II4|1.71|1.8|1.89|0.1 × VDDI|0.9 × VDDI|VOL/25|(VDDI– VOH)/2<br>5|
|HSUL12I4|1.14|1.2|1.26|0.1 × VDDI|0.9 × VDDI|VOL/40|(VDDI– VOH)/4<br>0|
|POD12I4,5|1.14|1.2|1.26|0.5 × VDDI||VOL/48|(VDDI– VOH)/4<br>8|
|POD12II4,5|1.14|1.2|1.26|0.5 × VDDI||VOL/34|(VDDI– VOH)/3<br>4|



**1.** Drive strengths per PCI specification V/I curves. 

**2.** Refer to UG0686: PolarFire FPGA User I/O User Guide for details on supported drive strengths. 

**3.** For external stub-series resistance. This resistance is on-die for GPIO. 

**4.** IOL/IOH units for impedance standards in amps (not mA). 

**5.** VOH_MAX based on external pull-up termination (pseudo-open drain). 

**6.** The total DC sink/source current of all IOs within a lane is limited as follows: 

   - **a.** HSIO lane: 120 mA per 12 IO buffers. 

   - **b.** GPIO lane: 160 mA per 12 IO buffers. 

Note: 3.3 V and 2.5 V are only supported in GPIO banks. 

## **6.3.2 Differential DC Input and Output Levels** 

The follow tables list the differential DC I/O levels. 

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**Table 16 • Differential DC Input Levels** 

|**I/O Stan-**<br>**dard**|**Bank Type**|**VICM_RAN-**<br>**GE Libero S-**<br>**etting**|**VICM**<br>**1,3**<br>**Min (V)**|**VICM**<br>**1,3**<br>**Typ (V)**|**VICM**<br>**1,3**<br>**Max (V)**|**VID**<br>**2**<br>**Min (V)**|**VID**<br>**Typ (V)**|**VID**<br>**Max (V)**|
|---|---|---|---|---|---|---|---|---|
|LVDS33|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.35|0.6|
|||Low|0.05|0.4|0.8|0.1|0.35|0.6|
|LVDS25 7|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.35|0.6|
|||Low|0.05|0.4|0.8|0.1|0.35|0.6|
|LVDS184|GPIO|Mid (de-<br>fault)|0.6|1.25|1.65|0.1|0.35|0.6|
|||Low|0.05|0.4|0.8|0.1|0.35|0.6|
|LVDS18 7|HSIO|Mid (de-<br>fault)|0.6|1.25|1.65|0.1|0.35|0.6|
|||Low|0.05|0.4|0.8|0.1|0.35|0.6|
|LCMDS33|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.35|0.6|
|||Low|0.05|0.4|0.8|0.1|0.35|0.6|
|LCMDS18|HSIO|Mid (de-<br>fault)|0.6|1.25|1.65|0.1|0.35|0.6|
|||Low|0.05|0.4|0.8|0.1|0.35|0.6|
|LCMDS25|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.35|0.6|
|||Low|0.05|0.4|0.8|0.1|0.35|0.6|
|RSDS33|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.2|0.6|
|||Low|0.05|0.4|0.8|0.1|0.2|0.6|
|RSDS25|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.2|0.6|
|||Low|0.05|0.4|0.8|0.1|0.2|0.6|
|RSDS185|HSIO|Mid (de-<br>fault)|0.6|1.25|1.65|0.1|0.2|0.6|
|||Low|0.05|0.4|0.8|0.1|0.2|0.6|
|MINILVDS3<br>3|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.3|0.6|
|||Low|0.05|0.4|0.8|0.1|0.3|0.6|



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|**I/O Stan-**<br>**dard**|**Bank Type**|**VICM_RAN-**<br>**GE Libero S-**<br>**etting**|**VICM**<br>**1,3**<br>**Min (V)**|**VICM**<br>**1,3**<br>**Typ (V)**|**VICM**<br>**1,3**<br>**Max (V)**|**VID**<br>**2**<br>**Min (V)**|**VID**<br>**Typ (V)**|**VID**<br>**Max (V)**|
|---|---|---|---|---|---|---|---|---|
|MINILVDS2<br>5|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.3|0.6|
|||Low|0.05|0.4|0.8|0.1|0.3|0.6|
|MINILVDS1<br>85|HSIO|Mid (de-<br>fault)|0.6|1.25|1.65|0.1|0.3|0.6|
|||Low|0.05|0.4|0.8|0.1|0.3|0.6|
|SUBLVDS33|GPIO|Mid (de-<br>fault)|0.6|0.9|2.35|0.1|0.15|0.3|
|||Low|0.05|0.4|0.8|0.1|0.15|0.3|
|SUBLVDS25|GPIO|Mid (de-<br>fault)|0.6|0.9|2.35|0.1|0.15|0.3|
|||Low|0.05|0.4|0.8|0.1|0.15|0.3|
|SUBLVDS1<br>85|HSIO|Mid (de-<br>fault)|0.6|0.9|1.65|0.1|0.15|0.3|
|||Low|0.05|0.4|0.8|0.1|0.15|0.3|
|PPDS33|GPIO|Mid (de-<br>fault)|0.6|0.8|2.35|0.1|0.2|0.6|
|||Low|0.05|0.4|0.8|0.1|0.2|0.6|
|PPDS25|GPIO|Mid (de-<br>fault)|0.6|0.8|2.35|0.1|0.2|0.6|
|||Low|0.05|0.4|0.8|0.1|0.2|0.6|
|PPDS185|HSIO|Mid (de-<br>fault)|0.6|0.8|1.65|0.1|0.2|0.6|
|||Low|0.05|0.4|0.8|0.1|0.2|0.6|
|SLVS336|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.2|0.3|
|||Low|0.05|0.2|0.8|0.1|0.2|0.3|
|SLVS256|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.2|0.3|
|||Low|0.05|0.2|0.8|0.1|0.2|0.3|
|SLVS185|HSIO|Mid (de-<br>fault)|0.6|1.00|1.65|0.1|0.2|0.3|
|||Low|0.05|0.4|0.8|0.1|0.2|0.3|



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|**I/O Stan-**<br>**dard**|**Bank Type**|**VICM_RAN-**<br>**GE Libero S-**<br>**etting**|**VICM**<br>**1,3**<br>**Min (V)**|**VICM**<br>**1,3**<br>**Typ (V)**|**VICM**<br>**1,3**<br>**Max (V)**|**VID**<br>**2**<br>**Min (V)**|**VID**<br>**Typ (V)**|**VID**<br>**Max (V)**|
|---|---|---|---|---|---|---|---|---|
|HCSL336|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.55|1.1|
|||Low|0.05|0.35|0.8|0.1|0.55|1.1|
|HCSL256|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.1|0.55|1.1|
|||Low|0.05|0.35|0.8|0.1|0.55|1.1|
|HCSL185|HSIO|Mid (de-<br>fault)|0.6|1.0|1.65|0.1|0.55|1.1|
|||Low|0.05|0.4|0.8|0.1|0.55|1.1|
|BUSLVDSE2<br>5|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.05|0.1|VDDIn|
|||Low|0.05|0.4|0.8|0.05|0.1|VDDIn|
|MLVDSE25|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.05|0.35|2.4|
|||Low|0.05|0.4|0.8|0.05|0.35|2.4|
|LVPECL33|GPIO|Mid (de-<br>fault)|0.6|1.65|2.35|0.05|0.8|2.4|
|||Low|0.05|0.4|0.8|0.05|0.8|2.4|
|LVPECLE33|GPIO|Mid (de-<br>fault)|0.6|1.65|2.35|0.05|0.8|2.4|
|||Low|0.05|0.4|0.8|0.05|0.8|2.4|
|MIPI25|GPIO|Mid (de-<br>fault)|0.6|1.25|2.35|0.05|0.2|0.3|
|||Low|0.05|0.2|0.8|0.05|0.2|0.3|



**1.** V ICM is the input common mode. 

**2.** VID is the input differential voltage. 

**3.** VICM rules are as follows: 

   - **a.** VICM must be less than VDDI – 0.4 V; 

   - **b.** VICM + VID/2 must be <VDDI + 0.4 V; 

   - **c.** VICM – VID/2 must be >VSS – 0.3 V; 

   - **d.** Any differential input with VICM ≤0.6 V requires the low common mode setting in Libero (VICM_RANGE=LOW). 

**4.** VDDI = 1.8 V, VDDAUX = 2.5 V. 

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DC Characteristics 

**5.** HSIO receiver only. 

**6.** GPIO receiver only. 

**7.** LVDS25 (GPIO) and LVDS18 (HSIO) configurations should be used in conjunction with I/O CDR when implementing SGMII receivers. 

## **Table 17 • Differential DC Output Levels** 

|**I/O Standard**|**Bank Type**|**VOCM**<br>**1**<br>**Min (V)**|**VOCM**<br>**Typ (V)**|**VOCM**<br>**Max (V)**|**VOD**<br>**2**<br>**Min (V)**|**VOD**<br>**2**<br>**Typ (V)**|**VOD**<br>**2**<br>**Max (V)**|
|---|---|---|---|---|---|---|---|
|LVDS33|GPIO|1.125|1.2|1.375|0.25|0.35|0.45|
|LVDS25 4|GPIO|1.125|1.2|1.375|0.25|0.35|0.45|
|LCMDS33|GPIO|0.45|0.6|0.7|0.25|0.35|0.45|
|LCMDS25|GPIO|0.45|0.6|0.7|0.25|0.35|0.45|
|RSDS33|GPIO|1.125|1.2|1.375|0.17|0.2|0.23|
|RSDS25|GPIO|1.125|1.2|1.375|0.17|0.2|0.23|
|MINILVDS33|GPIO|1.125|1.2|2.375|0.3|0.4|0.6|
|MINILVDS25|GPIO|1.125|1.2|2.375|0.3|0.4|0.6|
|SUBLVDS33|GPIO|0.8|0.9|1.0|0.1|0.15|0.3|
|SUBLVDS25|GPIO|0.8|0.9|1.0|0.1|0.15|0.3|
|PPDS33|GPIO|0.05|0.8|1.4|0.17|0.2|0.23|
|PPDS25|GPIO|0.05|0.8|1.4|0.17|0.2|0.23|
|SLVSE153|GPIO, HSIO|0.1|0.2|0.3|0.12|0.135|0.15|
|BUSLVDSE253|GPIO|1.15|1.25|1.31|0.24|0.262|0.272|
|MLVDSE253|GPIO|1.15|1.25|1.31|0.396|0.442|0.453|
|LVPECLE333|GPIO|1.51|1.65|1.74|0.664|0.722|0.755|
|MIPIE25 3|GPIO|0.15|0.2|0.25|0.14|0.2|0.27|



**1.** VOCM is the output common mode voltage. 

**2.** VOD is the output differential voltage. 

**3.** Emulated output only, using external resistors. 

**4.** LVDS25 configuration should be used when implementing SGMII transmitters. 

## **6.3.3 Complementary Differential DC Input and Output Levels** 

The following tables list the complementary differential DC I/O levels. 

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**Table 18 • Complementary Differential DC Input Levels** 

|**I/O Stan-**<br>**dard**|**VDDI**<br>**Min (V)**|**VDDI**<br>**Typ (V)**|**VDDI**<br>**Max (V)**|**VICM**<br>**1,3**<br>**Min (V)**|**VICM**<br>**1,3**<br>**Typ (V)**|**VICM**<br>**1,3**<br>**Max (V)**|**VID**<br>**2**<br>**Min (V)**|**VID2**<br>**Max (V)**|
|---|---|---|---|---|---|---|---|---|
|SSTL25I|2.375|2.5|2.625|1.164|1.250|1.339|0.1|VDDAUX(GPI-<br>O)|
|SSTL25II|2.375|2.5|2.625|1.164|1.250|1.339|0.1|VDDAUX(GPI-<br>O)|
|SSTL18I|1.71|1.8|1.89|0.838|0.900|0.964|0.1|VDDAUX(GPI-<br>O)VDDI(HSI-<br>O)|
|SSTL18II|1.71|1.8|1.89|0.838|0.900|0.964|0.1|VDDAUX(GPI-<br>O)VDDI(HSI-<br>O)|
|SSTL15I|1.425|1.5|1.575|0.698|0.750|0.803|0.1|VDDAUX(GPI-<br>O)VDDI(HSI-<br>O)|
|SSTL15II|1.425|1.5|1.575|0.698|0.750|0.803|0.1|VDDAUX(GPI-<br>O)VDDI(HSI-<br>O)|
|SSTL135I|1.283|1.35|1.418|0.629|0.675|0.723|0.1|VDDI(HSIO)|
|SSTL135II|1.283|1.35|1.418|0.629|0.675|0.723|0.1|VDDI(HSIO)|
|HSTL15I|1.425|1.5|1.575|0.698|0.750|0.803|0.1|VDDAUX(GPI-<br>O)VDDI(HSI-<br>O)|
|HSTL15II|1.425|1.5|1.575|0.698|0.750|0.803|0.1|VDDAUX(GPI-<br>O)VDDI(HSI-<br>O)|
|HSTL135I|1.283|1.35|1.418|0.629|0.675|0.723|0.1|VDDI(HSIO)|
|HSTL135II|1.283|1.35|1.418|0.629|0.675|0.723|0.1|VDDI(HSIO)|
|HSTL12I|1.14|1.2|1.26|0.559|0.600|0.643|0.1|VDDI(HSIO)|
|HSTL12II|1.14|1.2|1.26|0.559|0.600|0.643|0.1|VDDI(HSIO)|
|HSUL18I|1.71|1.8|1.89|0.838|0.900|0.964|0.1|VDDI(HSIO)|
|HSUL18II|1.71|1.8|1.89|0.838|0.900|0.964|0.1|VDDI(HSIO)|
|HSUL12I|1.14|1.2|1.26|0.559|0.600|0.643|0.1|VDDI(HSIO)|
|POD12I|1.14|1.2|1.26|0.787|0.840|0.895|0.1|VDDI(HSIO)|
|POD12II|1.14|1.2|1.26|0.787|0.840|0.895|0.1|VDDI(HSIO)|



**1.** VICM is the input common mode voltage. 

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DC Characteristics 

**2.** VID is the input differential voltage. 

**3.** VICM rules are as follows: 

   - **a.** VICM must be less than VDDI – 0.4 V; 

   - **b.** VICM + VID/2 must be <VDDI + 0.4 V; 

   - **c.** VICM – VID/2 must be >VSS – 0.3 V. 

**Table 19 • Complementary Differential DC Output Levels** 

|**I/O Stan-**<br>**dard**|**VDDI**<br>**Min (V)**|**VDDI**<br>**Typ (V)**|**VDDI**<br>**Max (V)**|**VOL**<br>**Min (V)**|**VOL**<br>**Max (V)**|**VOH**<br>**1,3**<br>**Min (V)**|**IOL**<br>**2**<br>**Min (mA)**|**IOH**<br>**2**<br>**Min (mA)**|
|---|---|---|---|---|---|---|---|---|
|SSTL25I|2.375|2.5|2.625||VTT– 0.608|VTT+ 0.608|8.1|8.1|
|SSTL25II|2.375|2.5|2.625||VTT– 0.810|VTT+ 0.810|16.2|16.2|
|SSTL18I|1.71|1.8|1.89||VTT– 0.603|VTT+ 0.603|6.7|6.7|
|SSTL18II|1.71|1.8|1.89||VTT– 0.603|VTT+ 0.603|13.4|13.4|
|SSTL15I4|1.425|1.5|1.575||0.2 × VDDI|0.8 × VDDI|VOL/40|(VDDI– VO-<br>H)/40|
|SSTL15II4|1.425|1.5|1.575||0.2 × VDDI|0.8 × VDDI|VOL/34|(VDDI– VO-<br>H)/34|
|SSTL135I4|1.283|1.35|1.418||0.2 × VDDI|0.8 × VDDI|VOL/40|(VDDI– VO-<br>H)/40|
|SSTL135II4|1.283|1.35|1.418||0.2 × VDDI|0.8 × VDDI|VOL/34|(VDDI– VO-<br>H)/34|
|HSTL15I|1.425|1.5|1.575||0.4|VDDI– 0.4|8|8|
|HSTL15II|1.425|1.5|1.575||0.4|VDDI– 0.4|16|16|
|HSTL135I4|1.283|1.35|1.418||0.2 × VDDI|0.8 × VDDI|VOL/50|(VDDI– VO-<br>H)/50|
|HSTL135II4|1.283|1.35|1.418||0.2 × VDDI|0.8 × VDDI|VOL/25|(VDDI– VO-<br>H)/25|
|HSTL12I4|1.14|1.2|1.26||0.1 × VDDI|0.9 × VDDI|VOL/50|(VDDI– VO-<br>H)/50|
|HSTL12II4|1.14|1.2|1.26||0.1 × VDDI|0.9 × VDDI|VOL/25|(VDDI– VO-<br>H)/25|
|HSUL18I4|1.71|1.8|1.89||0.1 × VDDI|0.9 × VDDI|VOL/55|(VDDI– VO-<br>H)/55|
|HSUL18II4|1.71|1.8|1.89||0.1 × VDDI|0.9 × VDDI|VOL/25|(VDDI– VO-<br>H)/25|
|HSUL12I4|1.14|1.2|1.26||0.1 × VDDI|0.9 × VDDI|VOL/40|(VDDI– VO-<br>H)/40|



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**==> picture [415 x 90] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|I/O Stan-|VDDI|VDDI|VDDI|VOL|VOL|VOH|1,3|IOL|2|IOH|2|
|dard|
|Min (V)|Typ (V)|Max (V)|Min (V)|Max (V)|Min (V)|Min (mA)|Min (mA)|
|POD12I|[3,4]|1.14|1.2|1.26|0.5 × VDDI|VOL/48|(VDDI – VO-|
|H|[)/48]|
|POD12II|[3,4]|1.14|1.2|1.26|0.5 × VDDI|VOL/34|(VDDI – VO-|
|H|[)/34]|

**----- End of picture text -----**<br>


**1.** VOH is the single-ended high-output voltage. 

**2.** The total DC sink/source current of all I/Os within a lane is limited as follows: 

   - **a.** HSIO lane: 120 mA per 12 I/O buffers. 

   - **b.** GPIO lane: 160 mA per 12 I/O buffers. 

**3.** VOH_MAX is based on external pull-up termination (pseudo-open drain). 

**4.** IOL/IOH units for impedance standards are in amps (not mA). 

## **6.3.4 HSIO On-Die Termination** 

The following tables list the on-die termination calibration accuracy specifications for the HSIO bank. 

## **Table 20 • Single-Ended (Internal Parallel) Thevenin Termination** 

**==> picture [417 x 246] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Min (%)|Typ|Max (%)|Unit|Condition|
|–40|50|20|Ω|VDDI = 1.8 V/1.5 V/1.35|
|V/1.2 V|
|–40|75|20|Ω|VDDI = 1.8 V|
|–40|150|20|Ω|VDDI = 1.8 V|
|–20|20|20|Ω|VDDI = 1.5 V/1.35 V|
|–20|30|20|Ω|VDDI = 1.5 V/1.35 V|
|–20|40|20|Ω|VDDI = 1.5 V/1.35 V|
|–20|60|20|Ω|VDDI = 1.5 V/1.35 V|
|–20|120|20|Ω|VDDI = 1.5 V/1.35 V|
|–20|60|20|Ω|VDDI = 1.2 V|
|–20|120|20|Ω|VDDI = 1.2 V|

**----- End of picture text -----**<br>


Note: Thevenin impedance is calculated based on independent P and N as measured at 50% of VDDI. For 50 Ω/75 Ω/150 Ω cases, the nearest supported values of 40 Ω/60 Ω/120 Ω are used. 

**Table 21 • Single-Ended (Internal Parallel) Termination to VDDI** 

**==> picture [381 x 31] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Min (%)|Typ|Max (%)|Unit|Condition|
|–20|34|20|Ω|VDDI = 1.2 V|

**----- End of picture text -----**<br>


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|**Min (%)**|**Typ**|**Max (%)**|**Unit**|**Condition**|
|---|---|---|---|---|
|–20|40|20|Ω|VDDI= 1.2 V|
|–20|48|20|Ω|VDDI= 1.2 V|
|–20|60|20|Ω|VDDI= 1.2 V|
|–20|80|20|Ω|VDDI= 1.2 V|
|–20|120|20|Ω|VDDI= 1.2 V|
|–20|240|20|Ω|VDDI= 1.2 V|



Note: Measured at 80% of VDDI. 

**Table 22 • Single-Ended (Internal Parallel) Termination to VSS** 

|**Min (%)**|**Typ**|**Max (%)**|**Unit**|**Condition**|
|---|---|---|---|---|
|–20|120|20|Ω|VDDI= 1.8 V/1.5 V|
|–20|240|20|Ω|VDDI= 1.8 V/1.5 V|
|–20|120|20|Ω|VDDI= 1.2 V|
|–20|240|20|Ω|VDDI= 1.2 V|



Note: Measured at 50% of VDDI. 

## **6.3.5 GPIO On-Die Termination** 

The following table lists the on-die termination calibration accuracy specifications for the GPIO bank. **Table 23 • On-Die Termination Calibration Accuracy Specifications for GPIO Bank** 

|**Parameter**|**Description**|**Min (%)**|**Typ**|**Max (%)**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|Differential ter-<br>mination1|Internaldifferen-<br>tial termination|–20|100|20|Ω|VICM< 0.8 V 6|
|||–20|100|40|Ω|0.6 V < VICM< 1.<br>65 V 6|
|||–20|100|80|Ω|1.4 V < VICM<br>6|
|Single-ended<br>thevenin termi-<br>nation2, 3|Internal parallel<br>thevenin termi-<br>nation|–40|50|20|Ω|VDDI= 1.8 V/1.5<br>V|
|||–40|75|20|Ω|VDDI= 1.8 V|
|||–40|150|20|Ω|VDDI= 1.8 V|
|||–20|20|20|Ω|VDDI= 1.5 V|
|||–20|30|20|Ω|VDDI= 1.5 V|
|||–20|40|20|Ω|VDDI= 1.5 V|



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|**Parameter**|**Description**|**Min (%)**|**Typ**|**Max (%)**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|||–20|60|20|Ω|VDDI= 1.5 V|
|||–20|120|20|Ω|VDDI= 1.5 V|
|Single-ended<br>termination to<br>VSS<br>4, 5|Internal parallel<br>termination to<br>VSS|–20|120|20|Ω|VDDI= 2.5 V/1.8<br>V/1.5 V/1.2 V|
|||–20|240|20|Ω|VDDI= 2.5 V/1.8<br>V/1.5 V/1.2 V|



**1.** Measured across P to N with 400 mV bias. 

**2.** Thevenin impedance is calculated based on independent P and N as measured at 50% of VDDI. 

**3.** For 50 Ω/75 Ω/150 Ω cases, the nearest supported values of 40 Ω/60 Ω/120 Ω are used. 

**4.** Measured at 50% of VDDI. 

**5.** Supported terminations vary with the I/O type regardless of VDDI nominal voltage. Refer to Libero for available combinations and default settings. 

**6.** When VICM complies with more than one range, use the maximum percentage tolerance of the two ranges. 

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## **7 AC Switching Characteristics** 

This section contains the AC switching characteristics of the PolarFire FPGA device. 

## **7.1 I/O Standards Specifications** 

This section describes I/O delay measurement methodology, buffer speed, switching characteristics, digital latency, gearing training calibration, and maximum physical interface (PHY) rate for memory interface IP. 

## **7.1.1 Input Delay Measurement Methodology Maximum PHY Rate for Memory Interface IP** 

The following table provides information about the methodology for input delay measurement. 

## **Table 24 • Input Delay Measurement Methodology** 

|**Standard**|**Description**|**VL**<br>**1**|**VH**<br>**1**|**VID**<br>**2**|**VICM**<br>**2**|**VMEAS**<br>**3, 4**|**VREF**<br>**1, 5**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|PCI|PCIE 3.3 V|0|VDDI|||VDDI/2||V|
|LVTTL|LVTTL 3.3 V|0|VDDI|||VDDI/2||V|
|LVCMOS33|LVCMOS3.3<br>V|0|VDDI|||VDDI/2||V|
|LVCMOS25|LVCMOS2.5<br>V|0|VDDI|||VDDI/2||V|
|LVCMOS18|LVCMOS1.8<br>V|0|VDDI|||VDDI/2||V|
|LVCMOS15|LVCMOS1.5<br>V|0|VDDI|||VDDI/2||V|
|LVCMOS12|LVCMOS1.2<br>V|0|VDDI|||VDDI/2||V|
|SSTL25I|SSTL 2.5 V<br>Class I|VREF– 0.5|VREF+ 0.5|||VREF|1.25|V|
|SSTL25II|SSTL 2.5 V<br>Class II|VREF– 0.5|VREF+ 0.5|||VREF|1.25|V|
|SSTL18I|SSTL 1.8 V<br>Class I|VREF– 0.5|VREF+ 0.5|||VREF|0.90|V|
|SSTL18II|SSTL 1.8 V<br>Class II|VREF– 0.5|VREF+ 0.5|||VREF|0.90|V|
|SSTL15I|SSTL 1.5 V<br>Class I|VREF– .175|VREF+ .175|||VREF|0.75|V|
|SSTL15II|SSTL 1.5 V<br>Class II|VREF– .175|VREF+ .175|||VREF|0.75|V|
|SSTL135I|SSTL 1.35 V<br>Class I|VREF– .16|VREF+ .16|||VREF|0.675|V|



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|**Standard**|**Description**|**VL**<br>**1**|**VH**<br>**1**|**VID**<br>**2**|**VICM**<br>**2**|**VMEAS**<br>**3, 4**|**VREF**<br>**1, 5**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|SSTL135II|SSTL 1.35 V<br>Class II|VREF– .16|VREF+ .16|||VREF|0.675|V|
|HSTL15I|HSTL 1.5 V<br>Class I|VREF– .5|VREF+ .5|||VREF|0.75|V|
|HSTL15II|HSTL 1.5 V<br>Class II|VREF– .5|VREF+ .5|||VREF|0.75|V|
|HSTL135I|HSTL 1.35<br>V Class I|VREF– .45|VREF+ .45|||VREF|0.675|V|
|HSTL135II|HSTL 1.35<br>V Class II|VREF– .45|VREF+ .45|||VREF|0.675|V|
|HSTL12I|HSTL 1.2 V<br>Class I|VREF– .4|VREF+ .4|||VREF|0.60|V|
|HSTL12II|HSTL 1.2 V<br>Class II|VREF– .4|VREF+ .4|||VREF|0.60|V|
|HSUL18I|HSUL 1.8 V<br>Class I|VREF– .54|VREF+ .54|||VREF|0.90|V|
|HSUL18II|HSUL 1.8 V<br>Class II|VREF– .54|VREF+ 0.54|||VREF|0.90|V|
|HSUL12I|HSUL 1.2 V|VREF– .22|VREF+ .22|||VREF|0.60|V|
|POD12I|Pseudo<br>open drain<br>(POD) logic<br>1.2 V Class I|VREF– .15|VREF+ .15|||VREF|0.84|V|
|POD12II|POD 1.2 V<br>Class II|VREF– .15|VREF+ .15|||VREF|0.84|V|
|LVDS33|Low-voltage<br>differential<br>signaling (L-<br>VDS) 3.3 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|LVDS25|LVDS 2.5 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|LVDS18|LVDS 1.8 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|LCMDS33|Low-com-<br>mon mode<br>differential<br>signaling (L-<br>CMDS) 3.3<br>V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|LCMDS25|LCMDS 2.5<br>V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|LCMDS18|LCMDS 1.8<br>V|VICM– .125|VICM+ .125|0.250|1.250|0||V|



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|**Standard**|**Description**|**VL**<br>**1**|**VH**<br>**1**|**VID**<br>**2**|**VICM**<br>**2**|**VMEAS**<br>**3, 4**|**VREF**<br>**1, 5**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|RSDS33|RSDS 3.3 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|RSDS25|RSDS 2.5 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|RSDS18|RSDS 1.8 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|MINILVDS3<br>3|Mini-LVDS 3<br>.3 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|MINILVDS2<br>5|Mini-LVDS 2<br>.5 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|MINILVDS1<br>8|Mini-LVDS 1<br>.8 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|SUBLVDS33|Sub-LVDS 3.<br>3 V|VICM– .125|VICM+ .125|0.250|0.900|0||V|
|SUBLVDS25|Sub-LVDS 2.<br>5 V|VICM– .125|VICM+ .125|0.250|0.900|0||V|
|SUBLVDS18|Sub-LVDS 1.<br>8 V|VICM– .125|VICM+ .125|0.250|0.900|0||V|
|PPDS33|Point-to-<br>point differ-<br>entialsignal-<br>ing 3.3 V|VICM– .125|VICM+ .125|0.250|0.800|0||V|
|PPDS25|PPDS 2.5 V|VICM– .125|VICM+ .125|0.250|0.800|0||V|
|PPDS18|PPDS 1.8 V|VICM– .125|VICM+ .125|0.250|0.800|0||V|
|SLVS33|Scalable<br>low-voltage<br>signaling 3.<br>3 V|VICM– .125|VICM+ .125|0.250|0.200|0||V|
|SLVS25|SLVS 2.5 V|VICM– .125|VICM+ .125|0.250|0.200|0||V|
|SLVS18|SLVS 1.8 V|VICM– .125|VICM+ .125|0.250|0.200|0||V|
|HCSL33|High-speed<br>current<br>steeringlog-<br>ic (HCSL) 3.<br>3 V|VICM– .125|VICM+ .125|0.250|0.350|0||V|
|HCSL25|HCSL 2.5 V|VICM– .125|VICM+ .125|0.250|0.350|0||V|
|HCSL18|HCSL 1.8 V|VICM– .125|VICM+ .125|0.250|0.350|0||V|
|BLVDSE256|Bus LVDS 2.<br>5 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|MLVDSE256|Multipoint<br>LVDS 2.5 V|VICM– .125|VICM+ .125|0.250|1.250|0||V|



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|**Standard**|**Description**|**VL**<br>**1**|**VH**<br>**1**|**VID**<br>**2**|**VICM**<br>**2**|**VMEAS**<br>**3, 4**|**VREF**<br>**1, 5**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|LVPECL33|Low-voltage<br>positive<br>emittercou-<br>pled logic|VICM– .125|VICM+ .125|0.250|1.650|0||V|
|LVPECLE336|Low-voltage<br>positive<br>emittercou-<br>pled logic|VICM– .125|VICM+ .125|0.250|1.650|0||V|
|SSTL25I|Differential<br>SSTL 2.5 V<br>Class I|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|SSTL25II|Differential<br>SSTL 2.5 V<br>Class II|VICM– .125|VICM+ .125|0.250|1.250|0||V|
|SSTL18I|Differential<br>SSTL 1.8 V<br>Class I|VICM– .125|VICM+ .125|0.250|0.900|0||V|
|SSTL18II|Differential<br>SSTL 1.8 V<br>Class II|VICM– .125|VICM+ .125|0.250|0.900|0||V|
|SSTL15I|Differential<br>SSTL 1.5 V<br>Class I|VICM– .125|VICM+ .125|0.250|0.750|0||V|
|SSTL15II|Differential<br>SSTL 1.5 V<br>Class II|VICM– .125|VICM+ .125|0.250|0.750|0||V|
|SSTL135I|Differential<br>SSTL 1.35 V<br>Class I|VICM– .125|VICM+ .125|0.250|0.675|0||V|
|SSTL135II|Differential<br>SSTL 1.35 V<br>Class I|VICM– .125|VICM+ .125|0.250|0.675|0||V|
|HSTL15I|Differential<br>HSTL 1.5 V<br>Class I|VICM– .125|VICM+ .125|0.250|0.750|0||V|
|HSTL15II|Differential<br>HSTL 1.5 V<br>Class II|VICM– .125|VICM+ .125|0.250|0.750|0||V|
|HSTL135I|Differential<br>HSTL 1.35<br>V Class I|VICM– .125|VICM+ .125|0.250|0.675|0||V|
|HSTL135II|Differential<br>HSTL 1.35<br>V Class II|VICM– .125|VICM+ .125|0.250|0.675|0||V|



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**==> picture [396 x 347] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Standard|Description|VL|1|VH|1|VID|2|VICM|2|VMEAS|3, 4|VREF|1, 5|Unit|
|HSTL12I|Differential|VICM – .125|VICM + .125|0.250|0.600|0|V|
|HSTL 1.2 V|
|Class I|
|HSTL12II|Differential|VICM – .125|VICM + .125|0.250|0.600|0|V|
|HSTL 1.2 V|
|Class II|
|HSUL18I|Differential|VICM – .125|VICM + .125|0.250|0.900|0|V|
|HSUL 1.8 V|
|Class I|
|HSUL18II|Differential|VICM – .125|VICM + .125|0.250|0.900|0|V|
|HSUL 1.8 V|
|Class II|
|HSUL12I|Differential|VICM – .125|VICM + .125|0.250|0.600|0|V|
|HSUL 1.2 V|
|POD12I|Differential|VICM – .125|VICM + .125|0.250|0.840|0|V|
|POD 1.2 V|
|Class I|
|POD12II|Differential|VICM – .125|VICM + .125|0.250|0.840|0|V|
|POD 1.2 V|
|Class II|
|MIPI25|Mobile I-|VICM –|.125|VICM +|.125|0.250|0.200|0|V|
|ndustryPro-|
|cessorInter-|
|face|

**----- End of picture text -----**<br>


**1.** Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst-case of these measurements. VREF values listed are typical. Input waveform switches between VIL and VIH. All rise and fall rates must be 1 V/ns for non-mixed mode input buffers as one-third the minimum period for mixed-mode input buffers. 

**2.** Differential receiver standards all use 250 mV VID for timing. V ICM is different between different standards. 

**3.** Input voltage level from which measurement starts. 

**4.** The value given is the differential input voltage. 

**5.** This is an input voltage reference that bears no relation to the VREF/VMEAS parameters found in IBIS models or shown in the figure Output Delay Measurement—Single-Ended Test Setup. 

**6.** Emulated bidirectional interface. 

## **7.1.2 Output Delay Measurement Methodology** 

The following section provides information about the methodology for output delay measurement. 

## **Table 25 • Output Delay Measurement Methodology** 

**==> picture [383 x 30] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Standard|Description|RREF (Ω)|CREF (pF)|VMEAS (V)|VREF (V)|
|PCI|PCIE 3.3 V|25|10|1.65|

**----- End of picture text -----**<br>


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|**Standard**|**Description**|**RREF (Ω)**|**CREF (pF)**|**VMEAS (V)**|**VREF (V)**|
|---|---|---|---|---|---|
|LVTTL|LVTTL 3.3 V|1M|0|1.65||
|LVCMOS33|LVCMOS 3.3 V|1M|0|1.65||
|LVCMOS25|LVCMOS 2.5 V|1M|0|1.25||
|LVCMOS18|LVCMOS 1.8 V|1M|0|0.90||
|LVCMOS15|LVCMOS 1.5 V|1M|0|0.75||
|LVCMOS12|LVCMOS 1.2 V|1M|0|0.60||
|SSTL25I|Stub-series termi-<br>nated logic 2.5 V C-<br>lass I|50|0|VREF|1.25|
|SSTL25II|SSTL 2.5 V Class II|50|0|VREF|1.25|
|SSTL18I|SSTL 1.8 V Class I|50|0|VREF|0.9|
|SSTL18II|SSTL 1.8 V Class II|50|0|VREF|0.9|
|SSTL15I|SSTL 1.5 V Class I|50|0|VREF|0.75|
|SSTL15II|SSTL 1.5 V Class II|50|0|VREF|0.75|
|SSTL135I|SSTL 1.35 V Class I|50|0|VREF|0.675|
|SSTL135II|SSTL 1.35 V Class II|50|0|VREF|0.675|
|HSTL15I|High-speed<br>transceiver logic<br>(HSTL) 1.5 V Class I|50|0|VREF|0.75|
|HSTL15II|HSTL 1.5 V Class II|50|0|VREF|0.75|
|HSTL135I|HSTL 1.35 V Class I|50|0|VREF|0.675|
|HSTL135II|HSTL 1.35 V Class II|50|0|VREF|0.675|
|HSTL12I|HSTL 1.2 V Class I|50|0|VREF|0.6|
|HSTL12II|HSTL 1.2 V Class II|50|0|VREF|0.6|
|HSUL18I|High-speeduntermi-<br>nated logic 1.8 V C-<br>lass I|50|0|VREF|0.9|
|HSUL18II|HSUL 1.8 V Class II|50|0|VREF|0.9|
|HSUL12I|HSUL 1.2 V Class I|50|0|VREF|0.6|
|POD12I|Pseudo open drain<br>(POD) logic 1.2 V C-<br>lass I|50|0|VREF|0.84|
|POD12II|POD 1.2 V Class II|50|0|VREF|0.84|



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|**Standard**|**Description**|**RREF (Ω)**|**CREF (pF)**|**VMEAS (V)**|**VREF (V)**|
|---|---|---|---|---|---|
|LVDS33|LVDS 3.3 V|100|0|01|0|
|LVDS25|LVDS 2.5 V|100|0|01|0|
|LCMDS33|Low-common<br>mode differential<br>signaling (LCMDS)<br>3.3 V|100|0|01|0|
|LCMDS25|LCMDS 2.5 V|100|0|0|0|
|RSDS33|Reduced swing dif-<br>ferential signaling 3<br>.3 V|100|0|01|0|
|RSDS25|RSDS 2.5 V|100|0|01|0|
|MINILVDS33|Mini-LVDS 3.3 V|100|0|01|0|
|MINILVDS25|Mini-LVDS 2.5 V|100|0|01|0|
|SUBLVDS33|Sub-LVDS 3.3 V|100|0|01|0|
|SUBLVDS25|Sub-LVDS 2.5 V|100|0|01|0|
|PPDS33|Point-to-point dif-<br>ferential signaling 3<br>.3 V|100|0|01|0|
|PPDS25|PPDS 2.5 V|100|0|01|0|
|SLVS33|Scalable low-volt-<br>age signaling 3.3 V|100|0|01|0|
|SLVS25|SLVS 2.5 V|100|0|01|0|
|SLVSE15|SLVS 1.5 V|100|0|01|0|
|HCSL33|High-speed current<br>steering logic 3.3 V|100|0|01|0|
|HCSL25|HCSL 2.5 V|100|0|01|0|
|BUSLVDSE25|Bus LVDS|100|0|01|0|
|MLVDSE25|Multipoint LVDS 2.<br>5 V|100|0|01|0|
|LVPECLE33|Low-voltage posi-<br>tive emitter-cou-<br>pled logic|100|0|01|0|
|MIPIE25|Mobile industry<br>processor interface<br>2.5 V|100|0|01|0|



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|**Standard**|**Description**|**RREF (Ω)**|**CREF (pF)**|**VMEAS (V)**|**VREF (V)**|
|---|---|---|---|---|---|
|SSTL25I|Differential SSTL 2.<br>5 V Class I|50|0|01|0|
|SSTL25II|Differential SSTL 2.<br>5 V Class II|50|0|01|0|
|SSTL18I|Differential SSTL 1.<br>8 V Class I|50|0|01|0|
|SSTL18II|Differential SSTL 1.<br>8 V Class II|50|0|01|0|
|SSTL15I|Differential SSTL 1.<br>5 V Class I|50|0|01|0|
|SSTL15II|Differential SSTL 1.<br>5 V Class II|50|0|01|0|
|SSTL135I|Differential SSTL 1.<br>35 V Class I|50|0|01|0|
|SSTL135II|Differential SSTL 1.<br>35 V Class II|50|0|01|0|
|HSTL15I|Differential HSTL 1.<br>5 V Class I|50|0|01|0|
|HSTL15II|Differential HSTL 1.<br>5 V Class II|50|0|01|0|
|HSTL135I|Differential HSTL 1.<br>35 V Class I|50|0|01|0|
|HSTL135II|Differential HSTL 1.<br>35 V Class II|50|0|01|0|
|HSTL12I|Differential HSTL 1.<br>2 V Class I|50|0|01|0|
|HSTL12II|Differential HSTL 1.<br>2 V Class II|50|0|01|0|
|HSUL18I|Differential HSUL 1<br>.8 V Class I|50|0|01|0|
|HSUL18II|Differential HSUL 1<br>.8 V Class II|50|0|01|0|
|HSUL12I|Differential HSUL 1<br>.2 V Class I|50|0|01|0|
|POD12I|Differential POD 1.<br>2 V Class II|50|0|01|0|
|POD12II|Differential POD 1.<br>2 V Class II|50|0|01|0|



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AC Switching Characteristics 

**1.** The value given is the differential output voltage. 

## **Figure 1 • Output Delay Measurement—Single-Ended Test Setup** 

**Figure 2 • Output Delay Measurement—Differential Test Setup** 

## **7.1.3 Input Buffer Speed** 

The following tables describe input buffer speed. 

**Table 26 • HSIO Maximum Input Buffer Speed** 

|**Standard**|**STD**|**–1**|**Unit**|
|---|---|---|---|
|LVDS18|1250|1250|Mbps|
|LCMDS18|1250|1250|Mbps|
|HCSL18|800|800|Mbps|
|RSDS18|800|800|Mbps|
|MINILVDS18|800|800|Mbps|



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**==> picture [340 x 520] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|Standard|STD|–1|Unit|
|SUBLVDS18|800|800|Mbps|
|PPDS18|800|800|Mbps|
|SLVS18|800|800|Mbps|
|SSTL18I|800|1066|Mbps|
|SSTL18II|800|1066|Mbps|
|SSTL15I|1066|1333|Mbps|
|SSTL15II|1066|1333|Mbps|
|SSTL135I|1066|1333|Mbps|
|SSTL135II|1066|1333|Mbps|
|HSTL15I|900|1100|Mbps|
|HSTL15II|900|1100|Mbps|
|HSTL135I|1066|1066|Mbps|
|HSTL135II|1066|1066|Mbps|
|HSUL18I|400|400|Mbps|
|HSUL18II|400|400|Mbps|
|HSUL12I|1066|1333|Mbps|
|HSTL12I|1066|1266|Mbps|
|HSTL12II|1066|1266|Mbps|
|POD12I|1333|1600|Mbps|
|POD12II|1333|1600|Mbps|
|LVCMOS18 (12 mA)|500|500|Mbps|
|LVCMOS15 (10 mA)|500|500|Mbps|
|LVCMOS12 (8 mA)|300|300|Mbps|

**----- End of picture text -----**<br>


Notes: 

- Performance is achieved with VID ≥200 mV. 

- LVDS18 configuration should be used in conjunction with I/O CDR when implementing SGMII receivers. 

## **Table 27 • GPIO Maximum Input Buffer Speed** 

**==> picture [340 x 39] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|Standard|STD|–1|Unit|
|LVDS25/LVDS33/LCMDS25/LC-|1250|1600|Mbps|
|MDS33|

**----- End of picture text -----**<br>


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|**Standard**|**STD**|**–1**|**Unit**|
|---|---|---|---|
|RSDS25/RSDS33|800|800|Mbps|
|MINILVDS25/MINILVDS33|800|800|Mbps|
|SUBLVDS25/SUBLVDS33|800|800|Mbps|
|PPDS25/PPDS33|800|800|Mbps|
|SLVS25/SLVS33|800|800|Mbps|
|SLVSE15|800|800|Mbps|
|HCSL25/HCSL33|800|800|Mbps|
|BUSLVDSE25|800|800|Mbps|
|MLVDSE25|800|800|Mbps|
|LVPECL33|800|800|Mbps|
|SSTL25I|800|800|Mbps|
|SSTL25II|800|800|Mbps|
|SSTL18I|800|800|Mbps|
|SSTL18II|800|800|Mbps|
|SSTL15I|800|1066|Mbps|
|SSTL15II|800|1066|Mbps|
|HSTL15I|800|900|Mbps|
|HSTL15II|800|900|Mbps|
|HSUL18I|400|400|Mbps|
|HSUL18II|400|400|Mbps|
|PCI|500|500|Mbps|
|LVTTL|500|500|Mbps|
|LVCMOS33|500|500|Mbps|
|LVCMOS25|500|500|Mbps|
|LVCMOS18|500|500|Mbps|
|LVCMOS15|500|500|Mbps|
|LVCMOS12|300|300|Mbps|
|MIPI253|1000|1500|Mbps|



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AC Switching Characteristics 

**1.** All SSTLD/HSTLD/HSULD/LVSTLD/POD type receivers use the LVDS differential receiver. 

**2.** Performance is achieved with VID ≥200 mV. 

**3.** VID ≥200 mV, VICM ≥100 mV, Tj= 0.4 UI. 

**4.** LVDS25 configuration should be used in conjunction with I/O CDR when implementing SGMII receivers. 

## **7.1.4 Output Buffer Speed** 

The following tables describe output buffer speed. 

## **Table 28 • HSIO Maximum Output Buffer Speed** 

|**Standard**|**STD**|**–1**|**Unit**|
|---|---|---|---|
|SSTL18I|800|1066|Mbps|
|SSTL18II|800|1066|Mbps|
|SSTL18I (differential)|800|1066|Mbps|
|SSTL18II (differential)|800|1066|Mbps|
|SSTL15I|1066|1333|Mbps|
|SSTL15II|1066|1333|Mbps|
|SSTL15I (differential)|1066|1333|Mbps|
|SSTL15II (differential)|1066|1333|Mbps|
|SSTL135I|1066|1333|Mbps|
|SSTL135II|1066|1333|Mbps|
|SSTL135I (differential)|1066|1333|Mbps|
|SSTL135II (differential)|1066|1333|Mbps|
|HSTL15I|900|1100|Mbps|
|HSTL15II|900|1100|Mbps|
|HSTL15I (differential)|900|1100|Mbps|
|HSTL15II (differential)|900|1100|Mbps|
|HSTL135I|1066|1066|Mbps|
|HSTL135II|1066|1066|Mbps|
|HSTL135I (differential)|1066|1066|Mbps|
|HSTL135II (differential)|1066|1066|Mbps|
|HSUL18I|400|400|Mbps|
|HSUL18II|400|400|Mbps|



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|**Standard**|**STD**|**–1**|**Unit**|
|---|---|---|---|
|HSUL18I (differential)|400|400|Mbps|
|HSUL18II (differential)|400|400|Mbps|
|HSUL12I|1066|1333|Mbps|
|HSUL12I (differential)|1066|1333|Mbps|
|HSTL12I|1066|1266|Mbps|
|HSTL12II|1066|1266|Mbps|
|HSTL12I (differential)|1066|1266|Mbps|
|HSTL12II (differential)|1066|1266|Mbps|
|POD12I|1333|1600|Mbps|
|POD12II|1333|1600|Mbps|
|LVCMOS18 (12 mA)|500|500|Mbps|
|LVCMOS15 (10 mA)|500|500|Mbps|
|LVCMOS12 (8 mA)|250|300|Mbps|



**Table 29 • GPIO Maximum Output Buffer Speed** 

|**Standard**|**STD**|**–1**|**Unit**|
|---|---|---|---|
|LVDS25/LCMDS25|1250|1250|Mbps|
|LVDS33/LCMDS33|1250|1600|Mbps|
|RSDS25|800|800|Mbps|
|MINILVDS25|800|800|Mbps|
|SUBLVDS25|800|800|Mbps|
|PPDS25|800|800|Mbps|
|SLVSE15|500|500|Mbps|
|BUSLVDSE25|500|500|Mbps|
|MLVDSE25|500|500|Mbps|
|LVPECLE33|500|500|Mbps|
|SSTL25I|800|800|Mbps|
|SSTL25II|800|800|Mbps|
|SSTL25I (differential)|800|800|Mbps|



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|**Standard**|**STD**|**–1**|**Unit**|
|---|---|---|---|
|SSTL25II (differential)|800|800|Mbps|
|SSTL18I|800|800|Mbps|
|SSTL18II|800|800|Mbps|
|SSTL18I (differential)|800|800|Mbps|
|SSTL18II (differential)|800|800|Mbps|
|SSTL15I|800|1066|Mbps|
|SSTL15II|800|1066|Mbps|
|SSTL15I (differential)|800|1066|Mbps|
|SSTL15II (differential)|800|1066|Mbps|
|HSTL15I|900|900|Mbps|
|HSTL15II|900|900|Mbps|
|HSTL15I (differential)|900|900|Mbps|
|HSTL15II (differential)|900|900|Mbps|
|HSUL18I|400|400|Mbps|
|HSUL18II|400|400|Mbps|
|HSUL18I (differential)|400|400|Mbps|
|HSUL18II (differential)|400|400|Mbps|
|PCI|500|500|Mbps|
|LVTTL (20 mA)|500|500|Mbps|
|LVCMOS33 (20 mA)|500|500|Mbps|
|LVCMOS25 (16 mA)|500|500|Mbps|
|LVCMOS18 (12 mA)|500|500|Mbps|
|LVCMOS15 (10 mA)|500|500|Mbps|
|LVCMOS12 (8 mA)|250|300|Mbps|
|MIPIE25|1000|1000|Mbps|



Note: LVDS25 configuration should be used when implementing SGMII transmitters. 

## **7.1.5 Maximum PHY Rate for Memory Interface IP** 

The following tables describe the maximum PHY rate for memory interface IP. 

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**Table 30 • Maximum PHY Rate for Memory Interfaces IP for HSIO Banks** 

|**MemoryStan-**<br>**dard**|**Gearing Ratio**|**VDDAUX**|**VDDI**|**STD (Mbps)**|**–1 (Mbps)**|**Fabric STD**<br>**(MHz)**|**Fabric –1 (M-**<br>**Hz)**|
|---|---|---|---|---|---|---|---|
|DDR4|8:1|1.8 V|1.2 V|1333|1600|167|200|
|DDR3|8:1|1.8 V|1.5 V|1067|1333|133|167|
|DDR3L1|8:1|1.8 V|1.35 V|1067|1333|133|167|
|LPDDR3|8:1|1.8 V|1.2 V|800|1333|133|167|
|QDRII+|8:1|1.8 V|1.5 V|900|1100|112.5|137.5|
|RLDRAM31|8:1|1.8 V|1.35 V|1067|1067|133|133|
|RLDRAM31|4:1|1.8 V|1.35 V|667|800|167|200|
|RLDRAM31|2:1|1.8 V|1.35 V|333|400|167|200|
|RLDRAMII 1|8:1|1.8 V|1.8 V|800|1067|100|133|
|RLDRAMII 1|4:1|1.8 V|1.8 V|667|800|167|200|
|RLDRAMII 1|2:1|1.8 V|1.8 V|333|400|167|200|



**1.** Simulation data only. Microchip does not provide a soft controller for RLDRAMII, RLDRAM3, or DDR3L. 

**2.** Simulation data only. RLDRAMII is currently not supported with a soft IP controller. 

**Table 31 • Maximum PHY Rate for Memory Interfaces IP for GPIO Banks** 

|**MemoryStan-**<br>**dard**|**Gearing Ratio**|**VDDAUX**|**VDDI**|**STD (Mbps)**|**–1 (Mbps)**|**Fabric STD**<br>**(MHz)**|**Fabric –1 (M-**<br>**Hz)**|
|---|---|---|---|---|---|---|---|
|DDR3|8:1|2.5 V|1.5 V|800|1067|100|133|
|QDRII+|8:1|2.5 V|1.5 V|900|900|113|113|
|RLDRAMII1|4:1|2.5 V|1.8 V|800|800|200|200|
|RLDRAMII1|2:1|2.5 V|1.8 V|400|400|200|200|



**1.** Simulation data only. RLDRAMII is currently not supported with a soft IP controller. 

## **7.1.6 User I/O Switching Characteristics** 

The following section describes user I/O switching characteristics. For more information about user I/O timing, see the PolarFire I/O Timing Spreadsheet (to be released). The following interface names are described in UG0686: PolarFire FPGA User I/O User Guide. 

## **7.1.6.1 I/O Digital** 

The following tables describe I/O digital. 

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**Table 32 • I/O Digital Receive Single-Data Rate Switching Characteristics** 

|**Parameter**|**STD (MHz)**<br>**I/O Type**<br>**Topology**<br>**Interface N-**||**Clock-to-D-**<br>**–1 (Mbps)**<br>**STD (Mbps)**<br>**–1 (MHz)**|
|---|---|---|---|
|Input FMAX|**ame**<br>500<br>HSIO, GPIO<br>Rx SDR<br>RX_SDR_G_||**ata Condi-**<br>**tion**<br>From a<br>500<br>500<br>500|
|Input FMAX|A<br>250<br>HSIO, GPIO<br>Rx SDR<br>RX_SDR_R_||global clock<br>source,<br>aligned<br>From a re-<br>250<br>250<br>250|
|Input FMAX|A<br>500<br>HSIO, GPIO<br>Rx SDR<br>RX_SDR_G_||gional clock<br>source,<br>aligned<br>From a<br>500<br>500<br>500|
|Input FMAX|C<br>250<br>HSIO, GPIO<br>Rx SDR<br>RX_SDR_R_||global clock<br>source, cen-<br>tered<br>From a re-<br>250<br>250<br>250|
||C||gional clock<br>source, cen-<br>tered|
|**Table 33 • I/O Digital Receive Double Data Rate Switching Characteristics**|**Table 33 • I/O Digital Receive Double Data Rate Switching Characteristics**||**Table 33 • I/O Digital Receive Double Data Rate Switching Characteristics**|
|**Parameter**|**STD (MHz)**<br>**I/O Type**<br>**Topology**<br>**Interface N-**||**Clock-to-D-**<br>**–1 (Mbps)**<br>**STD (Mbps)**<br>**–1 (MHz)**|
|Input FMAX|**ame**<br>335<br>HSIO<br>Rx DDR<br>RX_DDR_G_||**ata Condi-**<br>**tion**<br>From a<br>690<br>670<br>345|
|Input FMAX|A<br>310<br>GPIO<br>250<br>HSIO<br>Rx DDR<br>RX_DDR_R_||global clock<br>650<br>620<br>325<br>source,<br>aligned<br>From a re-<br>500<br>500<br>250|
|Input FMAX|A<br>250<br>GPIO<br>335<br>HSIO<br>Rx DDR<br>RX_DDR_G_||gional clock<br>500<br>500<br>250<br>source,<br>aligned<br>From a<br>690<br>670<br>345|
|Input FMAX|C<br>310<br>GPIO<br>250<br>HSIO<br>Rx DDR<br>RX_DDR_R_||global clock<br>650<br>620<br>325<br>source, cen-<br>tered<br>From a re-<br>500<br>500<br>250|
|Input FMAX|C<br>250<br>GPIO<br>350<br>HSIO<br>Rx DDR digi-<br>RX_DDRX_||gional clock<br>500<br>500<br>250<br>source, cen-<br>tered<br>From a HS_<br>700<br>700<br>350|
|2:1|tal mode<br>B_G_A<br>300<br>GPIO||IO_CLK<br>620<br>600<br>310<br>clock<br>source,<br>aligned,<br>global fab-<br>ric clock|



**Table 33 • I/O Digital Receive Double Data Rate Switching Characteristics** 

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|**Parameter**|**Interface N-**<br>**ame**|**Topology**|**I/O Type**|**STD (MHz)**|**–1 (MHz)**|**STD (Mbps)**|**–1 (Mbps)**|**Clock-to-D-**<br>**ata Condi-**<br>**tion**|
|---|---|---|---|---|---|---|---|---|
|Input FMAX<br>4:1|RX_DDRX_<br>B_G_A|Rx DDR digi-<br>tal mode|HSIO|350|350|700|700|From a HS_<br>IO_CLK<br>clock<br>source,<br>aligned,<br>global fab-<br>ric clock|
||||GPIO|300|310|600|620||
|Input FMAX<br>3.5:1|RX_DDRX_<br>B_G_FA|Rx DDR digi-<br>tal mode<br>for fraction-<br>al|HSIO|350|350|700|700|From a HS_<br>IO_CLK<br>clock<br>source,<br>aligned,<br>global fab-<br>ric clock,<br>fractional<br>input|
||||GPIO|320|320|640|640||
|Input FMAX<br>2:1|RX_DDRX_<br>B_G_C|Rx DDR digi-<br>tal mode|HSIO|350|350|700|700|From a HS_<br>IO_CLK<br>clock<br>source, cen-<br>tered, glob-<br>al fabric<br>clock|
||||GPIO|300|310|600|620||
|Input FMAX<br>4:1 Input<br>FMAX5:1|RX_DDRX_<br>B_G_C|Rx DDR digi-<br>tal mode|HSIO|350|350|700|700|From a HS_<br>IO_CLK<br>clock<br>source, cen-<br>tered, glob-<br>al fabric<br>clock|
||||GPIO|300|310|600|620||
|Input FMAX<br>4:1|RX_DDRX_<br>B_G_DYN_<br>MIPI|Rx DDR digi-<br>tal mode<br>for MIPI|GPIO|5001|7501|10001|15001|From a HS_<br>IO_CLK<br>clock<br>source,cen-<br>tered, glob-<br>al fabric<br>clock|
|Input FMAX<br>2:1|RX_DDRX_<br>B_R_A|Rx DDR digi-<br>tal mode|HSIO|220|270|440|540|From a HS_<br>IO_CLK<br>clock<br>source,<br>aligned, re-<br>gional fab-<br>ric clock|
||||GPIO|205|250|410|500||
|Input FMAX<br>4:1 Input<br>FMAX5:1|RX_DDRX_<br>B_R_A|Rx DDR digi-<br>tal mode|HSIO|220|270|440|540|From a HS_<br>IO_CLK<br>clock<br>source,<br>aligned, re-<br>gional fab-<br>ric clock|
||||GPIO|205|250|410|500||



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|**Parameter**|**Interface N-**<br>**ame**|**Topology**|**I/O Type**|**STD (MHz)**|**–1 (MHz)**|**STD (Mbps)**|**–1 (Mbps)**|**Clock-to-D-**<br>**ata Condi-**<br>**tion**|
|---|---|---|---|---|---|---|---|---|
|Input FMAX<br>2:1|RX_DDRX_<br>B_R_C|Rx DDR digi-<br>tal mode|HSIO|220|270|440|540|From a HS_<br>IO_CLK<br>clock<br>source, cen-<br>tered, re-<br>gional fab-<br>ric clock|
||||GPIO|205|250|410|500||
|Input FMAX<br>4:1 Input<br>FMAX5:1|RX_DDRX_<br>B_R_C|Rx DDR digi-<br>tal mode|HSIO|220|270|440|540|From a HS_<br>IO_CLK<br>clock<br>source, cen-<br>tered, re-<br>gional fab-<br>ric clock|
||||GPIO|205|250|410|500||



**1.** VID ≥200 mV, VICM ≥100 mV, Tj=0.4 UI. 

**2.** A centered clock-to-data interface can be created with a negedge launch of the data. 

**Table 34 • I/O Digital Transmit Single Data Rate Switching Characteristics** 

|**Parameter**|**Interface N-**<br>**ame**|**Topology**|**I/O Type**|**STD (MHz)**|**–1 (MHz)**|**STD (Mbps)**|**–1 (Mbps)**|**Forwarded**<br>**Clock-to-D-**<br>**ata Skew**|
|---|---|---|---|---|---|---|---|---|
|Output FMA-<br>X|TX_SDR_G_<br>A|Tx SDR|HSIO, GPIO|500|500|500|500|From a<br>global clock<br>source,<br>aligned1|
||TX_SDR_G_<br>C|Tx SDR|HSIO, GPIO|500|500|500|500|From a<br>global clock<br>source, cen-<br>tered1|



**1.** A centered clock-to-data interface can be created with a negedge launch of the data. 

**Table 35 • I/O Digital Transmit Double Data Rate Switching Characteristics** 

|**Parameter**|**Interface N-**<br>**ame**|**Topology**|**I/O Type**|**STD (MHz)**|**–1 (MHz)**|**STD (Mbps)**|**–1 (Mbps)**|**Forwarded**<br>**Clock-to-D-**<br>**ata Skew**|
|---|---|---|---|---|---|---|---|---|
|Output FMA-<br>X|TX_DDR_G_<br>A|Tx DDR|HSIO, GPIO|500|500|1000|1000|From a<br>global clock<br>source,<br>aligned|
||TX_DDR_G_<br>C|Tx DDR|HSIO, GPIO|500|500|1000|1000|From a<br>global clock<br>source, cen-<br>tered|
|Output FMA-<br>X 2:1|TX_DDRX_<br>B_A|Tx DDR digi-<br>tal mode|HSIO|400|500|800|1000|From a HS_<br>IO_CLK<br>clock|



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|**Parameter**|**Interface N-**<br>**ame**|**Topology**|**I/O Type**|**STD (MHz)**|**–1 (MHz)**|**STD (Mbps)**|**–1 (Mbps)**|**Forwarded**<br>**Clock-to-D-**<br>**ata Skew**|
|---|---|---|---|---|---|---|---|---|
|||||||||source,<br>aligned|
|Output FMA-<br>X 4:1<br>Output FMA-<br>X 5:1|TX_DDRX_<br>B_A|Tx DDR digi-<br>tal mode|HSIO|667|800|1333|1600|From a HS_<br>IO_CLK<br>clock<br>source,<br>aligned|
|Output FMA-<br>X 2:1|TX_DDRX_<br>B_C|Tx DDR digi-<br>tal mode|HSIO|400|500|800|1000|From a HS_<br>IO_CLK<br>clock<br>source,cen-<br>tered with<br>PLL|
|Output FMA-<br>X 4:1<br>Output FMA-<br>X 5:1|TX_DDRX_<br>B_C|Tx DDR digi-<br>tal mode|HSIO|667|800|1333|1600|From a HS_<br>IO_CLK<br>clock<br>source, cen-<br>tered with<br>PLL|
|Output FMA-<br>X 2:1|TX_DDRX_<br>B_A|Tx DDR digi-<br>tal mode|GPIO|400|500|800|1000|From a HS_<br>IO_CLK<br>clock<br>source,<br>aligned|
|Output FMA-<br>X 4:1<br>Output FMA-<br>X 5:1|TX_DDRX_<br>B_A|Tx DDR digi-<br>tal mode|GPIO|625|800|1250|1600|From a HS_<br>IO_CLK<br>clock<br>source,<br>aligned|
|Output FMA-<br>X 2:1|TX_DDRX_<br>B_C|Tx DDR digi-<br>tal mode|GPIO|400|500|800|1000|From a HS_<br>IO_CLK<br>clock<br>source, cen-<br>tered with<br>PLL|
|Output FMA-<br>X 4:1<br>Output FMA-<br>X 5:1|TX_DDRX_<br>B_C|Tx DDR digi-<br>tal mode|GPIO|625|800|1250|1600|From a HS_<br>IO_CLK<br>clock<br>source, cen-<br>tered with<br>PLL|
|Output FMA-<br>X 4:1|TX_DDRX_<br>B_C_ MIPI|Tx DDR digi-<br>tal mode<br>for MIPI|GPIO|400|500|800|1000|From a HS_<br>IO_CLK<br>clock<br>source, cen-<br>tered with<br>PLL|



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**Table 36 • Programmable Delay** 

|**Parameter**|**STD Min**|**STD Typ**|**STD Max**|**–1 Min**|**–1 Typ**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|In delay, out<br>delay, DLL<br>delay step<br>sizes|12.7|30|35|12.7|25|29.5|ps|



Note: Refer to Libero timing reports for configuration specific intrinsic and incremental delays. 

## **Figure 3 • LVDS Jitter Tolerance Plot** 

**Table 37 • I/O CDR Switching Characteristics** 

|**Buffer Type**|**I/O Configuration**|**Min Data Rate (M-**<br>**bps)**|**Max Data Rate (M-**<br>**bps)**|**Max Tx to Rx Fre-**<br>**quency Offset**<br>**(ppm)**|**Jtolmin (UI)**|
|---|---|---|---|---|---|
|HSIO1, 2|LVDS18|266|1250|±200|0.08|
|HSIO1, 2|LVDS18|266|1250|±100|0.1|
|GPIO1, 3|LVDS25|266|1250|±100|0.1|



**1.** Jitter tolerance of applied sinusoidal jitter from 1 KHz to 120 MHz, as shown in figure LVDS Jitter Tolerance Plot. It is measured in addition to a stressed eye of Tj= 0.24 UI with VICM of 1.25 V and VIDmin of 250 mV, with the CDR operating at a rate of 1250 Mbps plus or minus the ppm offset listed. 

**2.** HSIO LVDS uses an external 100 Ω differential termination resistor. For more information, see LVDS specification in table Differential DC Input Levels. 

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**3.** GPIO LVDS uses an internal 100 Ω differential termination resistor. For more information, see LVDS specification in table Differential DC Input Levels. 

## **7.2 Clocking Specifications** 

This section describes the PLL and DLL clocking and oscillator specifications. 

## **7.2.1 Clocking** 

The following table describes clocking specifications. 

**Table 38 • Global and Regional Clock Characteristics (–40 °C to 100 °C)** 

|**Parameter**|**Symbol**|**V DD= 1.0 V S-**<br>**TD**|**V DD = 1.0 V**<br>**–1**|**V DD = 1.05 V**<br>**STD**|**V DD = 1.05 V**<br>**–1**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|---|
|Global clock<br>FMAX|FMAXG|500|500|500|500|MHz||
|Regional<br>clock FMAX|FMAXR|375|375|375|375|MHz|Transceiver<br>interfaces on-<br>ly|
||FMAXR|250|250|250|250|MHz|Allotherinter-<br>faces|
|Global clock<br>duty cycle dis-<br>tortion|TDCDG|190|190|190|190|ps|At 500 MHz|
|Regional<br>clock duty cy-<br>cle distortion|TDCDR|120|120|120|120|ps|At 250 MHz|



The following table describes clocking specifications from –40 °C to 100 °C. 

**Table 39 • High-Speed I/O Clock Characteristics (–40 °C to 100 °C)** 

|**Parameter**|**Symbol**|**VDD=1.0VST-**<br>**D**|**VDD= 1.0 V –1**|**VDD = 1.05 V**<br>**STD**|**VDD = 1.05 V**<br>**–1**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|---|
|High-speed I/<br>O clock FMAX|FMAXB|1000|1250|1000|1250|MHz|HSIO and GPI-<br>O|
|High-speed I/<br>O clock skew1|FSKEWB|30|20|30|20|ps|HSIO without<br>bridging|
||FSKEWB|See table HSI-<br>O Clock Skew<br>with Bridging.|ps|HSIO with<br>bridging|GPIO without<br>bridging<br>ps<br>35|||
||FSKEWB|45|35|45||||
||FSKEWB|75|60|75|60|ps|GPIO with<br>bridging|
|High-speed I/<br>O clock duty|TDCB|90|90|90|90|ps|HSIO without<br>bridging|



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|**Parameter**|**Symbol**|**VDD=1.0VST-**<br>**D**|**VDD= 1.0 V –1**|**VDD = 1.05 V**<br>**STD**|**VDD = 1.05 V**<br>**–1**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|---|
|cycle distor-<br>tion2|TDCB|115|115|115|115|ps|HSIO with<br>bridging|
||TDCB|90|90|90|90|ps|GPIO without<br>bridging|
||TDCB|115|115|115|115|ps|GPIO with<br>bridging|



**1.** FSKEWB is the worst-case clock-tree skew observable between sequential I/O elements. Clock-tree skew is significantly smaller at I/O registers close to each other because they are fed by the same or adjacent clock-tree branches. Use the Microsemi Timing Analyzer tool to evaluate clock skew specific to the design. 

**2.** Parameters listed in this table correspond to the worst-case duty cycle distortion observable at the I/O flip flops. IBIS should be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times for any I/O standard. 

The following table describes high-speed I/O clock skew (FSKEWB) with bridging from –40 °C to 100 °C. 

Note: FSKEWB is the worst-case clock-tree skew observable between sequential I/O elements. Clock-tree skew is significantly smaller at I/O registers close to each other and fed by the same or adjacent clock-tree branches. Use the Microsemi Timing Analyzer tool to evaluate clock skew specific to the design. 

**Table 40 • HSIO Clock Skew with Bridging (–40 °C to 100 °C)** 

|**Device**|**Total I/O B-**<br>**anks**|**Bridging S-**<br>**ource**|**VDD=1.0VST-**<br>**D**|**VDD= 1.0 V –1**|**VDD = 1.05 V**<br>**STD**|**VDD = 1.05 V**<br>**–1**|**Unit**|
|---|---|---|---|---|---|---|---|
|MPF100T|2|NNW1|120|80|120|80|ps|
||2|NNE2|110|70|110|70|ps|
|MPF200T|2|NNW1|120|80|120|80|ps|
||2|NNE2|110|70|110|70|ps|
|MPF300T|3|NNW1|120|80|120|80|ps|
||3|NNE2|280|200|280|200|ps|
|MPF500T|3|NNW1|125|85|125|85|ps|
||3|NNE2|300|220|300|220|ps|



**1.** NNW source designates bridging that originates from the North West Corner or PIOs inside I/O bank 0 (the most western I/O bank at the north edge). 

**2.** NNE source designates bridging that originates from the North East Corner or PIOs inside I/O bank 1 (the most eastern I/O bank at the north edge). 

## **7.2.2 PLL** 

The following table describes PLL. 

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## **Table 41 • PLL Electrical Characteristics** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|Input clock fre-<br>quency (integer<br>mode)|FINI|1||1250|MHz||
|Input clock fre-<br>quency(fraction-<br>al mode)|FINF|10||1250|MHz||
|Minimum refer-<br>ence or feed-<br>back pulse<br>width1|FINPULSE|200|||ps||
|Frequency at<br>the Frequency<br>Phase Detector<br>(PFD) (integer<br>mode)|FPHDETI|1||312|MHz||
|Frequency at<br>the PFD (frac-<br>tional mode)|FPHDETF|10||225|MHz||
|Allowable input<br>duty cycle|FINDUTY|25||75|%||
|Maximum input<br>period clock jit-<br>ter (reference<br>and feedback<br>clocks)2|FMAXINJ||120|1000|ps||
|PLL VCO fre-<br>quency|FVCO|800||5000|MHz||
|Loopbandwidth<br>(Int)3|FBW|FPHDET/55|FPHDET/44|FPHDET/30|MHz||
|Loopbandwidth<br>(FRAC)3|FBW|FPHDET/91|FPHDET/77|FPHDET/56|MHz||
|Static phase off-<br>set of the PLL<br>outputs4|TSPO|||Max (±60 ps, ±0<br>.5 degrees)|ps||
|PLL output peri-<br>od jitter10|TOUTJITTER|||0.025*output_<br>period|ps|1.5 MHz ≤Fout<br>< 15 MHz|
|135|ps|Fout ≥15 MHz|%<br>54||||
|PLL output duty<br>cycle precision|TOUTDUTY|48|||||
|PLL lock time5|TLOCK|||Max (6.0 μs, 62<br>5 PFD cycles)|μs||
|PLL unlock time6|TUNLOCK|2||8|PFD cycles||



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|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|PLL output fre-<br>quency|FOUT|0.050||1250|MHz||
|Minimum pow-<br>er-down pulse<br>width|TMPDPW|1|||μs||
|Maximum delay<br>in the feedback<br>path7|FMAXDFB|||1.5|PFD cycles||
|Spread spec-<br>trum modula-<br>tion spread8|Mod_Spread|0.1||3.1|%||
|Spread spec-<br>trum modula-<br>tion frequency9|Mod_Freq|FPHDETF/ (128x6<br>3)|32|FPHDETF/(128)|KHz||



**1.** Minimum time for high or low pulse width. 

**2.** Maximum jitter the PLL can tolerate without losing lock. 

**3.** Default bandwidth setting of BW_PROP_CTRL = "01" for Integer and Fraction modes leads to the typical estimated bandwidth. This bandwidth can be lowered by setting BW_PROP_CTRL = "00" and can be increased if BW_PROP_CTRL = "10" and will be at the highest value if BW_PROP_CTRL = "11". 

**4.** Maximum (±3-Sigma) phase error between any two outputs with nominally aligned phases. 

**5.** Input clock cycle is REFDIV/FREF. For example, FREF = 25 MHz, REFDIV = 1, lock time = 10.0 (assumes LOCKCOUNTSEL setting = 4'd8 (256 cycles)). 

**6.** Unlock occurs if two cycles slip within LOCKCOUNT/4 PFD cycles. 

**7.** Maximum propagation delay of external feedback path in Deskew mode. 

**8.** Programmable capability for depth of down spread or center spread modulation. 

**9.** Programmable modulation rate based on the modulation divider setting (1 to 63). 

**10.** Period jitter is measured at the output of the device using HSUL12 output buffers and includes the jitter effects of the reference clock source, PLL, clock routing networks, and output buffer. PLL is configured with internal feedback enabled and in integer mode. FPGA fabric is active during testing (75% utilization). 

Note: In order to meet all datasheet specifications, the PLL must be programmed such that the PLL Loop Bandwidth < (0.0017 * VCO Frequency) – 0.4863 MHz. The Libero PLL configuration tool will enforce this rule when creating PLL configurations. 

## **7.2.3 DLL** 

The following table provides information about DLL. 

## **Table 42 • DLL Electrical Characteristics** 

|**Parameter1**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Input reference<br>clock frequency|FINF|133||800|MHz|



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|**Parameter1**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Input feedback<br>clock frequency|FINFDBF|133||800|MHz|
|Primary output<br>clock frequency|FOUTPF|133||800|MHz|
|Secondary output<br>clock frequency2|FOUTSF|33.3||800|MHz|
|Input clock cycle-<br>to-cycle jitter|FINJ|||200|ps|
|Output clock cycle-<br>to-cycle jitter (with<br>clean input clock)|TOUTJITTERCC|||Max (250 ps, 15%<br>of clock period)|ps|
|Outputclockperiod<br>jitter (with clean in-<br>put clock)|TOUTJITTERP|||Max (300 ps, 20%<br>of clock period)|ps|
|Output clock-to-<br>clock skew be-<br>tween two outputs<br>with the same<br>phase settings|TSKEW|||±150|ps|
|DLL lock time|TLOCK|16||16K|Reference clock cy-<br>cles|
|Minimum reset<br>pulse width|TMRPW|3|||ns|
|Minimum input<br>pulse width3|TMIPW|20|||ns|
|Minimum input<br>clock pulse width<br>high|TMPWH|400|||ps|
|Minimum input<br>clock pulse width<br>low|TMPWL|400|||ps|
|Delay step size|TDEL|12.7|30|35|ps|
|Maximum delay<br>block delay4|TDELMAX|1.8||4.8|ns|
|Output clock duty<br>cycle (with 50% du-<br>ty cycle input)5|TDUTY|40||60|%|
|Output clock duty<br>cycle (with 50% du-<br>ty cycle input)6|TDUTY50|45||55|%|



**1.** For all DLL modes. 

**2.** Secondary output clock divided by four option. 

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**3.** On load, direction, move, hold, and update input signals. 

**4.** 128 delay taps in one delay block. 

**5.** Without duty cycle correction enabled. 

**6.** With duty cycle correction enabled. 

## **7.2.4 RC Oscillators** 

The following tables describe internal RC clock resources for user designs. They also describe system design with RF front-end information about emitters generated on-chip to support programming operations. 

## **Table 43 • 2 MHz RC Oscillator Electrical Characteristics** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Operating frequen-<br>cy|RC2FREQ||2||MHz|
|Accuracy|RC2FACC|–4||4|%|
|Duty cycle|RC2DC|46||54|%|
|Peak-to-peak out-<br>put period jitter|RC2PJIT||5|10|ns|
|Peak-to-peak out-<br>put cycle-to-cycle<br>jitter|RC2CJIT||5|10|ns|
|Operating current<br>(VDD25)|RC2IVPPA|||60|µA|
|Operating current<br>(VDD)|RC2IVDD|||2.6|µA|



**Table 44 • 160 MHz RC Oscillator Electrical Characteristics** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Operating frequen-<br>cy|RCSCFREQ||160||MHz|
|Accuracy|RCSCFACC|–4||4|%|
|Duty cycle|RCSCDC|47||52|%|
|Peak-to-peak out-<br>put period jitter|RCSCPJIT|||600|ps|
|Peak-to-peak out-<br>put cycle-to-cycle<br>jitter|RCSCCJIT|||172|ps|
|Operating current<br>(VDD25)|RCSCVPPA|||599|µA|
|Operating current<br>(VDD18)|RCSCVPP|||0.1|µA|



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|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Operating current<br>(VDD)|RCSCVDD|||60.7|µA|



## **7.3 Fabric Specifications** 

The following section describes specifications for the fabric. 

## **7.3.1 Math Blocks** 

The following table lists the maximum operating frequency (FMAX) of the math block in the extended commercial temperature range (0 °C to 100 °C). 

## **Table 45 • Math Block Performance Extended Commercial Range (0 °C to 100 °C)** 

|**Modes**|**VDD = 1.0 V – STD**|**VDD = 1.0 V – 1**|**VDD = 1.05 V – STD**|**VDD = 1.05 V – 1**|**Unit**|
|---|---|---|---|---|---|
|18 × 18 multiplica-<br>tion|370|470|440|500|MHz|
|18 × 18 multiplica-<br>tion summed with<br>48-bit input|370|470|440|500|MHz|
|18 × 19 multiplier<br>pre-adder ROM<br>mode|365|465|435|500|MHz|
|Two 9 × 9 multipli-<br>cation|370|470|440|500|MHz|
|9 × 9 dot product<br>(DOTP)|370|470|440|500|MHz|
|Complex 18 × 19<br>multiplication|360|455|430|500|MHz|



The following table lists the maximum operating frequency (FMAX) of the math block in the industrial temperature range (–40 °C to 100 °C). 

**Table 46 • Math Block Performance Industrial Range (–40 °C to 100 °C)** 

|**Modes**|**VDD = 1.0 V – STD**|**VDD = 1.0 V – 1**|**VDD = 1.05 V – STD**|**VDD = 1.05 V – 1**|**Unit**|
|---|---|---|---|---|---|
|18 × 18 multiplica-<br>tion|365|465|435|500|MHz|
|18 × 18 multiplica-<br>tion summed with<br>48-bit input|365|465|435|500|MHz|
|18 × 19 multiplier<br>pre-adder ROM<br>mode|355|460|430|500|MHz|
|Two 9 × 9 multipli-<br>cation|365|465|435|500|MHz|



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|**Modes**|**VDD = 1.0 V – STD**|**VDD = 1.0 V – 1**|**VDD = 1.05 V – STD**|**VDD = 1.05 V – 1**|**Unit**|
|---|---|---|---|---|---|
|9 × 9 DOTP|365|465|435|500|MHz|
|Complex 18 × 19<br>multiplication|350|450|425|500|MHz|



## **7.3.2 SRAM Blocks** 

The following table lists the maximum operating frequency (FMAX) of the LSRAM block in the industrial temperature range (–40 °C to 100 °C). 

## **Table 47 • LSRAM Performance Industrial Temperature Range (–40 °C to 100 °C)** 

|**V DD = 1.0 V – STD**|**V DD = 1.0 V – 1**|**V DD = 1.05 V – STD**|**V DD = 1.05 V – 1**|**Unit**|**Condition**|
|---|---|---|---|---|---|
|343|428|343|428|MHz|Two-port, all sup-<br>ported widths,<br>pipelined, simple-<br>write, and write-<br>feed-through|
|309|428|309|428|MHz|Two-port, all sup-<br>portedwidths,non-<br>pipelined, simple-<br>write, and write-<br>feed-through|
|343|428|343|428|MHz|Dual-port, all sup-<br>ported widths,<br>pipelined, simple-<br>write, and write-<br>feed-through|
|309|428|309|428|MHz|Dual-port, all sup-<br>portedwidths,non-<br>pipelined, simple-<br>write, and write-<br>feed-through|
|343|428|343|428|MHz|Two-port pipelined<br>ECC mode,<br>pipelined, simple-<br>write, and write-<br>feed-through|
|279|295|279|295|MHz|Two-port non-<br>pipelined ECC<br>mode, pipelined,<br>simple-write, and<br>write-feed-through|
|343|428|343|428|MHz|Two-port pipelined<br>ECC mode, non-<br>pipelined, simple-<br>write, and write-<br>feed-through|
|196|285|196|285|MHz|Two-port non-<br>pipelined ECC<br>mode, non-|



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|**V DD = 1.0 V – STD**|**V DD = 1.0 V – 1**|**V DD = 1.05 V – STD**|**V DD = 1.05 V – 1**|**Unit**|**Condition**|
|---|---|---|---|---|---|
||||||pipelined, simple-<br>write, and write-<br>feed-through|
|274|285|274|285|MHz|Two-port, all sup-<br>ported widths,<br>pipelined, and<br>read-before-write|
|274|285|274|285|MHz|Two-port, all sup-<br>portedwidths,non-<br>pipelined, and<br>read-before-write|
|274|285|274|285|MHz|Dual-port, all sup-<br>ported widths,<br>pipelined, and<br>read-before-write|
|274|285|274|285|MHz|Dual-port, all sup-<br>portedwidths,non-<br>pipelined, and<br>read-before-write|
|274|285|274|285|MHz|Two-port pipelined<br>ECC mode,<br>pipelined, and<br>read-before-write|
|274|285|274|285|MHz|Two-port non-<br>pipelined ECC<br>mode, pipelined,<br>and read-before-<br>write|
|274|285|274|285|MHz|Two-port pipelined<br>ECC mode, non-<br>pipelined, and<br>read-before-write|
|193|285|193|285|MHz|Two-port non-<br>pipelined ECC<br>mode, non-<br>pipelined, and<br>read-before-write|



The following table lists the maximum operating frequency (FMAX) of the µSRAM block in the industrial temperature range (–40 °C to 100 °C). 

## **Table 48 • µSRAM Performance** 

|**Parameter**|**Symbol**|**V DD = 1.0 V –**<br>**STD**|**V DD = 1.0 V –**<br>**1**|**V DD = 1.05 V**<br>**– STD**|**V DD = 1.05 V**<br>**– 1**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|---|
|Operatingfre-<br>quency|FMAX|400|415|450|480|MHz|Write-port|
|Read access<br>time|Tac||2||2|ns|Read-port|



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The following table lists the maximum operating frequency (FMAX) of the µPROM block in the industrial temperature range (–40 °C to 100 °C). 

## **Table 49 • µPROM Performance** 

|**Parameter**|**Symbol**|**V DD= 1.0V – ST-**<br>**D**|**V DD = 1.0 V – 1**|**V DD = 1.05 V –**<br>**STD**|**V DD = 1.05 V –**<br>**1**|**Unit**|
|---|---|---|---|---|---|---|
|Read access<br>time|Tac|10|10|10|10|ns|



## **7.4 Transceiver Switching Characteristics** 

This section describes transceiver switching characteristics. 

## **7.4.1 Transceiver Performance** 

The following table describes transceiver performance. 

## **Table 50 • PolarFire Transceiver and TXPLL Performance** 

|**Parameter**|**Symbol**|**STD Min**|**STD Typ**|**STD Max**|**–1 Min**|**–1 Typ**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|Tx data<br>rate1,2|FTXRate|0.25||10.3125|0.25||12.7|Gbps|
|Tx OOB (se-<br>rializer by-<br>pass) data<br>rate|FTXRateOOB|DC||1.5|DC||1.5|Gbps|
|Rx data rate<br>when AC<br>coupled2|FRxRateAC|0.25||10.3125|0.25||12.7|Gbps|
|Rx data rate<br>when DC<br>coupled|FRxRateDC|0.25||3.2|0.25||3.2|Gbps|
|Rx OOB (de-<br>serializer<br>bypass) da-<br>ta rate|FTXRateOOB|DC||1.25|DC||1.25|Gbps|
|TXPLL out-<br>putfrequen-<br>cy3|FTXPLL|1.6||5.1563|1.6||6.35|GHz|
|Rx CDR<br>mode|FRXCDR|0.25||10.3125|0.25||10.3125|Gbps|
|Rx DFE and<br>CDR auto-<br>calibration<br>modes2|FRXAUTOCAL|3.0||10.3125|3.0||12.7|Gbps|
|RxEyeMon-<br>itor mode 2|FRXEyeMon|3.0||10.3125|3.0||12.7|Gbps|



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|**Parameter**|**Symbol**|**STD Min**|**STD Typ**|**STD Max**|**–1 Min**|**–1 Typ**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|PCS reset<br>minimum<br>pulse width|MPWPCS_RES-<br>ET|16|||16|||[Tx|Rx]_CLK<br>Cycles4|
|PMA reset<br>minimum<br>pulse width|MPWPMA_RE-<br>SET|16|||16|||[Tx|Rx]_CLK<br>Cycles4|



**1.** The reference clock is required to be a minimum of 75 MHz for data rates of 10 Gbps and above. 

**2.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

**3.** The Tx PLL rate is between 0.5x to 5.5x the Tx data rate. The Tx data rate depends on per XCVR lane Tx post-divider settings. 

**4.** Minimum pulse width should reference TX_CLK when Tx only or both Tx and Rx are used. Reference RX_CLK if only Rx is used. 

## **7.4.2 Transceiver Reference Clock Performance** 

The following table describes performance of the transceiver reference clock. 

## **Table 51 • PolarFire Transceiver Reference Clock AC Requirements** 

|**Parameter**|**Symbol**|**STD Min**|**STD Typ**|**STD Max**|**–1 Min**|**–1 Typ**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|Reference<br>clock input<br>rate1, 2|FTXREFCLK|20||400|20||400|MHz|
|Reference<br>clock input<br>rate1, 2, 3|FXCVRREFCLKM-<br>AX CASCADE|20||156|20||156|MHz|
|Reference<br>clock rate at<br>the Tx PLL<br>PFD4|FTXREFCLKPFD|20||156|20||175|MHz|
|Reference<br>clock rate<br>recommend-<br>edatthePF-<br>D for Tx<br>rates 10 G-<br>bps and<br>above4|FTXREFCLKPFD-<br>10G|75||156|75||175|MHz|
|Tx refer-<br>ence clock<br>phase noise<br>require-<br>ments to<br>meet jitter<br>specifica-<br>tions (156<br>MHz clock<br>at reference|FTXREFPN|||–110|||–110|dBc/Hz|



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|**Parameter**|**Symbol**|**STD Min**|**STD Typ**|**STD Max**|**–1 Min**|**–1 Typ**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|---|---|---|
|clock in-<br>put)5|||||||||
|Phase noise<br>at 10 KHz|FTXREFPN|||–110|||–110|dBc/Hz|
|Phase noise<br>at 100 KHz|FTXREFPN|||–115|||–115|dBc/Hz|
|Phase noise<br>at 1 MHz|FTXREFPN|||–135|||–135|dBc/Hz|
|Reference<br>clock input<br>rise time (1<br>0%–90%)|TREFRISE||200|500||200|500|ps|
|Reference<br>clock input<br>fall time (90<br>%–10%)|TREFFALL||200|500||200|500|ps|
|Reference<br>clock rate at<br>RX CDR|FRXREFCLKCDR|20||156|20||156|MHz|
|Reference<br>clock duty<br>cycle|TREFDUTY|40||60|40||60|%|
|Spread<br>spectrum<br>modulation<br>spread6|Mod_S-<br>pread|0.1||3.1|0.1||3.1|%|
|Spread<br>spectrum<br>modulation<br>frequency7|Mod_Freq|TxREF CLKP-<br>FD/ (128)|32|TxREF CLKP-<br>FD/ (128*6<br>3)|TxREF CLKP-<br>FD/ (128)|32|TxREF CLKP-<br>FD/ (128*6<br>3)|KHz|



**1.** See the maximum reference clock rate allowed per input buffer standard. 

**2.** The minimum value applies to this clock when used as an XCVR reference clock. It does not apply when used as a non-XCVR input buffer (DC input allowed). 

**3.** Cascaded reference clock. 

**4.** After reference clock input divider. 

**5.** To calculate the FTXREFPN phase noise requirement at frequencies other than 156 MHz use the following formula: FTXREFPN at f(MHz) = FTXREFPN at 156 MHz + 20*log(f/156) 

**6.** Programmable capability for depth of down-spread or center-spread modulation. 

**7.** Programmable modulation rate based on the modulation divider setting (1 to 63). 

## **7.4.3 Transceiver Reference Clock I/O Standards** 

The following differential I/O standards are supported as transceiver reference clocks. 

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- LVDS25/33 

- HCLS25 (for PCIe) 

- RSDS25/33 

- MINILVDS25/33 

- SUBLVDS25/33 

- PPDS25/33 

- SLVS25/33 

- BUSLVDS25 

- MLVDS25 

- LVPECL33 

- MIPI25 

For DC input levels, see table Differential DC Input and Output Levels. 

Note: The transceiver reference clock differential receiver supports VICM common mode. 

Note: The amount of jitter from the input receiver increases at common modes of less 0.2 V or greater than VDDSREF–0.4 V. Therefore, for improved SerDes operation, it is recommended that the VCM of the signal into the SerDes reference clock input be at a minimum of 0.2 V and below VDDSREF–0.4 V. 

The following single-ended I/O standards are supported as transceiver reference clocks. 

- LVTTL 

- LVCMOS33 

- LVCMOS25 

- LVCMOS18 

- SSTL25I/II 

- SSTL18I/II 

- HSUL18I/II 

For DC input levels, see table DC Input and Output Levels. 

Note: Generally, Hysteresis = Off is recommended. In extremely high noise systems with degraded reference clock input, Hysteresis = On may improve results. 

## **7.4.4 Transmitter Performance** 

The following tables describe performance of the transmitter. 

**Table 52 • Transceiver Reference Clock Input Termination** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Single-endedtermi-<br>nation|RefTerm||50||Ω|
|Single-endedtermi-<br>nation|RefTerm||75||Ω|
|Single-endedtermi-<br>nation|RefTerm||150||Ω|
|Differentialtermina-<br>tion|RefDiffTerm||1151||Ω|
|Power-up termina-<br>tion|||>50K||Ω|



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## **1.** Measured at VCM= 1.2 V and VID= 350 mV. 

Note: All pull-ups are disabled at power-up to allow hot plug capability. 

The following tables describe the PolarFire Transceiver User Interface Clocks 

Note: Until specified, all modes are non-deterministic. For more information, see _UG0677: PolarFire FPGA Transceiver User Guide_ . 

**Table 53 • Transceiver TX_CLK Range (Nondeterministic PCS Mode with Global or Regional Fabric Clocks)** 

|**Mode**|**STD Min**|**STD Max**|**–1 Min**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|
|8-bit, max data rate<br>= 1.6 Gbps||200||200|MHz|
|10-bit, max data<br>rate = 1.6 Gbps||160||160|MHz|
|16-bit, max data<br>rate = 4.8 Gbps||300||300|MHz|
|20-bit, max data<br>rate = 6.0 Gbps||300||300|MHz|
|32-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||325||325|MHz|
|40-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||260||320|MHz|
|64-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||165||200|MHz|
|80-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||130||160|MHz|
|Fabric pipe mode 3<br>2-bit, max data rate<br>= 6.0 Gbps||150||150|MHz|



**1.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

**Table 54 • Transceiver RX_CLK Range (Non-Deterministic PCS Mode with Global or Regional Fabric Clocks)** 

|**Mode**|**STD Min**|**STD Max**|**–1 Min**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|
|8-bit, max data rate<br>= 1.6 Gbps||200||200|MHz|
|10-bit, max data<br>rate = 1.6 Gbps||160||160|MHz|



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|**Mode**|**STD Min**|**STD Max**|**–1 Min**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|
|16-bit, max data<br>rate = 4.8 Gbps||300||300|MHz|
|20-bit, max data<br>rate = 6.0 Gbps||300||300|MHz|
|32-bit, max data<br>rate = 10.3125 G-<br>bps||325||325|MHz|
|40-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||260||320|MHz|
|64-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||165||200|MHz|
|80-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||130||160|MHz|
|Fabric pipe mode 3<br>2-bit, max data rate<br>= 6.0 Gbps||150||150|MHz|



**1.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

**Table 55 • Transceiver TX_CLK Range (Deterministic PCS Mode with Regional Fabric Clocks)** 

|**Mode**|**STD Min**|**STD Max**|**–1 Min**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|
|8-bit, max data rate<br>= 1.6 Gbps||200||200|MHz|
|10-bit, max data<br>rate = 1.6 Gbps||160||160|MHz|
|16-bit, max data<br>rate = 3.6 Gbps (–S-<br>TD) / 4.25 Gbps (–1<br>)||225||266|MHz|
|20-bit, max data<br>rate = 4.5 Gbps (–S-<br>TD) / 5.32 Gbps (–1<br>)||225||266|MHz|
|32-bit, max data<br>rate = 7.2 Gbps (–S-<br>TD) / 8.5 Gbps (–1)||225||266|MHz|
|40-bit, max data<br>rate = 9.0 Gbps (–S-||225||266|Mhz|



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|**Mode**|**STD Min**|**STD Max**|**–1 Min**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|
|TD) / 10.6 Gbps (–1<br>)1||||||
|64-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||165||200|MHz|
|80-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||130||160|MHz|



**1.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

**Table 56 • Transceiver RX_CLK Range (Deterministic PCS Mode with Regional Fabric Clocks)** 

|**Mode**|**STD Min**|**STD Max**|**–1 Min**|**–1 Max**|**Unit**|
|---|---|---|---|---|---|
|8-bit, max data rate<br>= 1.6 Gbps||200||200|MHz|
|10-bit, max data<br>rate = 1.6 Gbps||160||160|MHz|
|16-bit, max data<br>rate = 3.6 Gbps (–S-<br>TD) / 4.25 Gbps (–1<br>)||225||266|MHz|
|20-bit, max data<br>rate = 4.5 Gbps (–S-<br>TD) / 5.32 Gbps (–1<br>)||225||266|MHz|
|32-bit, max data<br>rate = 7.2 Gbps (–S-<br>TD) / 8.5 Gbps (–1)||225||266|MHz|
|40-bit, max data<br>rate = 9.0 Gbps (–S-<br>TD) / 10.6 Gbps (–1<br>)1||225||266|MHz|
|64-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||165||200|MHz|
|80-bit, max data<br>rate = 10.3125 G-<br>bps (–STD) / 12.7<br>Gbps (–1)1||130||160|MHz|



**1.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

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**Table 57 • PolarFire Transceiver Transmitter Characteristics** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|Differential ter-<br>mination|VOTERM||85||Ω||
||VOTERM||100||Ω||
||VOTERM||150||Ω||
|Common mode<br>voltage1|VOCM|0.44 × VDDA|0.525 × VDDA|0.59 × VDDA|V|DC coupled 50%<br>setting|
||VOCM|0.52 × VDDA|0.6 × VDDA|0.66 × VDDA|V|DC coupled 60%<br>setting|
||VOCM|0.61 × VDDA|0.7 × VDDA|0.75 × VDDA|V|DC coupled 70%<br>setting|
||VOCM|0.63 × VDDA|0.8 × VDDA|0.83 × VDDA|V|DC coupled 80%<br>setting|
|Rise time2 Fall<br>time2|TTxRF|40||61|ps|20% to 80%|
|||39||58|ps|80% to 20%|
|Differential<br>peak-to-peak<br>amplitude|VODPP|1080|1140|1320|mV|1000mVsetting|
||VODPP|1010|1060|1220|mV|800 mV setting|
||VODPP|550|580|670|mV|500 mV setting|
||VODPP|465|490|560|mV|400 mV setting|
||VODPP|350|370|425|mV|300 mV setting|
||VODPP|250|260|300|mV|200 mV setting|
||VODPP|150|160|185|mV|100 mV setting|
|Transmit lane P<br>to N skew3|TOSKEW||8|15|ps||
|Lane to lane<br>transmit skew4|TLLSKEW|||75|ps|Single PLL, 2–4<br>bonded lanes, 8<br>–40-bit fabric<br>width10|
|||||8|UI|Single PLL, 2–4<br>bonded lanes, 6<br>4–80-bit fabric<br>width11|
|||||8 + Refclk skew|UI|Multiple PLL, 2<br>–4 bonded<br>lanes, 8–40-bit<br>fabric width11, 1<br>2|



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|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|||||32 + Refclk skew|UI|Multiple PLL, 2<br>–4 bonded<br>lanes, 64–80-bit<br>fabric width11, 1<br>2|
|Electrical idle<br>transition entry<br>time7|TTxEITrEntry|||20|ns||
|Electrical idle<br>transition exit<br>time7|TTxEITrExit|||19|ns||
|Electrical idle<br>amplitude|VTxEIpp|||7|mV||
|TXPLL lock time|TTXLock|||1600|PFD cycles||
|Digital PLL lock<br>time8|TDPLLLock|||75,000|REFCLK UIs|Frequency lock|
|||||150,000|REFCLK UIs|Phase lock|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.22 0.1|UI UI|Data rate ≥10.3<br>125 Gbps to 12.<br>7 Gbps9 (Tx VCO<br>rate 5.16 GHz to<br>6.35 GHz)<br>TXPLL in integer<br>mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.28 0.1|UI UI|Data rate ≥10.3<br>125 to 12.7 G-<br>bps9 (Tx VCO<br>rate 5.16 GHz to<br>6.35 GHz)<br>TXPLLinfraction-<br>al mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.22 0.09|UI UI|Data rate ≥8.5<br>Gbps to 10.3125<br>Gbps (Tx VCO<br>rate 4.25 GHz to<br>5.16 GHz)<br>TXPLL in integer<br>mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.28 0.09|UI UI|Data rate ≥8.5<br>Gbps to 10.3125<br>Gbps (Tx VCO<br>rate 4.25 GHz to<br>5.16 GHz) TXPLL<br>in fractional<br>mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5,6|TJTDJ|||0.21 0.09|UI<br>UI|Data rate ≥5.0<br>Gbps to 8.5 G-<br>bps (Tx VCOrate|



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|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|||||||2.5 GHz to 4.25<br>GHz)<br>TXPLL in integer<br>mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.25 0.09|UI UI|Data rate ≥5.0<br>Gbps to 8.5 G-<br>bps (Tx VCOrate<br>2.5 GHz to 4.25<br>GHz)<br>TXPLLinfraction-<br>al mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.17 0.03|UI UI|Data rate ≥1.6<br>Gbps to 5.0 G-<br>bps (Tx VCOrate<br>1.6 GHz to 2.5<br>GHz)<br>TXPLL in integer<br>mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.2 0.03|UI UI|Data rate ≥1.6<br>Gbps to 5.0 G-<br>bps (Tx VCOrate<br>1.6 GHz to 2.5<br>GHz)<br>TXPLLinfraction-<br>al mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.08 0.02|UI UI|Data rate ≥800<br>Mbps to 1.6 G-<br>bps (Tx VCOrate<br>1.6 GHz)<br>TXPLL in integer<br>mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.11 0.02|UI UI|Data rate ≥800<br>Mbps to 1.6 G-<br>bps (Tx VCOrate<br>1.6 GHz)<br>TXPLLinfraction-<br>al mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.05 0.01|UI UI|Data rate = 250<br>Mbps to 800 M-<br>bps (Tx VCOrate<br>1.48 GHz to 1.6<br>GHz)<br>TXPLL in integer<br>mode|
|Total jitter5, 6, 13<br>Deterministic<br>jitter5, 6|TJTDJ|||0.06 0.01|UI UI|Data rate = 250<br>Mbps to 800 M-<br>bps (Tx VCOrate<br>1.48 GHz to 1.6<br>GHz)<br>TXPLLinfraction-<br>al mode|



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**1.** Increased DC common mode settings above 50% reduce allowed VOD output swing capabilities. 

**2.** Adjustable through transmit emphasis. 

**3.** With estimated package differences. 

**4.** Single PLL applies to all four lanes in the same quad location with the same TxPLL. Multiple PLL applies to N lanes using multiple TxPLLs from different quad locations. 

**5.** Improved jitter characteristics for a specific industry standard are possible in many cases due to improved reference clock or higher VCO rate used. 

**6.** Tx jitter is specified with all transmitters on the device enabled, a 10–12-bit error rate (BER) and Tx data pattern of PRBS7. 

**7.** From the PMA mode, the TX_ELEC_IDLE port to the XVCR TXP/N pins. 

**8.** FTxRefClk = 75 MHz with typical settings. 

**9.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

**10.** Transmit alignment in this case will automatically align upon the TX PLL obtaining lock. For details on transmit alignment, see UG0677: PolarFire FPGA Transceiver User Guide. 

**11.** In order to obtain the required alignment for these configurations, an FPGA fabric TX alignment circuit must be implemented. For details on transmit alignment, see _UG0677: PolarFire FPGA Transceiver User Guide_ . 

**12.** Refclk skew is the amount of skew between the reference clocks of the two PLL. 

**13.** Jitter decomposition can be found in the protocol characterization reports. 

## **7.4.5 Receiver Performance** 

The following table describes performance of the receiver. 

## **Table 58 • PolarFire Transceiver Receiver Characteristics** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|Input voltage<br>range|VIN|0||VDDA+ 0.3|V||
|Differential<br>peak-to-peak<br>amplitude|VIDPP|140||1250|mV||
|Differential ter-<br>mination|VITERM||85||Ω||
||||100||Ω||
||||150||Ω||
|Common mode<br>voltage|VICMDC<br>1|0.7 × VDDA||0.9 × VDDA|V|DC coupled|
|Exit electrical<br>idle detection<br>time|TEIDET||50|100|ns||



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|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|Run length of<br>consecutive<br>identical digits<br>(CID)|CID|||200|UI||
|CDR PPM toler-<br>ance2|CDRPPM|||1.17|%UI||
|CDR lock-to-da-<br>ta time13|TLTD|512 * CDRREFDIV||1024 * CDRREFDI-<br>V|CDRREFCLKcycles|Disabled: E-<br>nhancedReceiv-<br>er Management<br>14|
|||(1900/TCDRREF+<br>(512 + (1020 *<br>(WXCVRFABRX/CD-<br>RFBDIV)) * CDRRE-<br>FDIV)||(5200/TCDRREF+<br>(1024 + (6380 *<br>(WXCVRFABRX/CD-<br>RFBDIV)) * CDRRE-<br>FDIV)||Enabled: E-<br>nhancedReceiv-<br>er Management<br>14|
|CDR lock-to-ref<br>time13|TLTF|(1000/TCDRREF) +<br>(1024*CDRREFD-<br>IV)||(13000/TCDRREF)<br>+ (1536 * CDRRE-<br>FDIV)|CDRREFCLKcycles||
|High-gain lock<br>time|THGLT|10.8|||ns|For Burst mode<br>receiver (BMR)|
|High-gain state<br>time12|THGSTATE|||3264|ns|For Burst mode<br>receiver (BMR)|
|Loss-of-signal<br>detect (peak de-<br>tect range set-<br>ting= high)9,10|VDETHIGH|145||295|mV|Setting= 3|
|||155||340|mV|Setting= 4|
|||180||365|mV|Setting= 5|
|||195||375|mV|Setting= 6|
|||210||385|mV|Setting= 7|
|Loss-of-signal<br>detect (peak de-<br>tect range set-<br>ting=low)9,10|VDETLOW|65||175|mV|Setting= PCIe3, 7|
|||95||190|mV|Setting= SATA4,<br>8|
|||75||170|mV|Setting= 1|
|||95||185|mV|Setting= 2|
|||100||190|mV|Setting= 3|
|||140||210|mV|Setting= 4|
|||155||240|mV|Setting= 5|
|||165||245|mV|Setting= 6|
|||170||250|mV|Setting= 7|



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|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|Sinusoidal jitter<br>tolerance|TSJTOL|0.34|||UI|>8.5 Gbps –12.7<br>Gbps5, 11|
|||0.43|||UI|>8.0–8.5 Gbps5|
|||0.45|||UI|>3.2–8.0 Gbps5|
|||0.45|||UI|>1.6 to 3.2 G-<br>bps5|
|||0.42|||UI|>0.8 to 1.6 G-<br>bps5|
|||0.41|||UI|250 to 800 M-<br>bps5|
|Total jitter toler-<br>ance with<br>stressed eye|TTJTOLSE|0.65|||UI|3.125 Gbps5|
|||0.65|||UI|6.25 Gbps6|
|||0.7|||UI|10.3125 Gbps6|
|||0.7|||UI|12.7 Gbps6, 11|
|Sinusoidal jitter<br>tolerance with<br>stressed eye|TSJTOLSE|0.1|||UI|3.125 Gbps5|
|||0.05|||UI|6.25 Gbps6|
|||0.05|||UI|10.3125 Gbps6|
|||0.05|||UI|12.7 Gbps6, 11|
|CTLE DC gain (all<br>stages, max set-<br>tings)||0.1||10|dB||
|CTLE AC gain (all<br>stages, max set-<br>tings)||0.05||16|dB||
|DFE AC gain (per<br>5 stages, max<br>settings)||0.05||7.5|dB||
|Auto adaptive<br>calibration time<br>(CTLE)|TCTLE|12||45|ms||
|Auto adaptive<br>calibration time<br>(CTLE+DFE)|TCTLE+DFE||1.4||s||
|Enhancedreceiv-<br>er mangement<br>control clock in-<br>put (CTRL_CLK)|FERMCTRLCLK|38.4|40|41.6|MHz||



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**1.** Valid at 3.2 Gbps and below. 

**2.** Data vs Rx reference clock frequency. 

**3.** Achieves compliance with PCIe electrical idle detection. 

**4.** Achieves compliance with SATA OOB specification. 

**5.** Rx jitter values based on bit error ratio (BER) of 10–12, AC-coupled input with 400 mV VID, all stages of Rx CTLE enabled, DFE disabled, 80 MHz sinusoidal jitter injected to Rx data. 

**6.** Rx jitter values based on bit error ratio (BER) of 10–12, AC-coupled input with 400 mV VID, all stages of Rx CTLE enabled, DFE enabled, 80 MHz sinusoidal jitter injected to Rx data. 

**7.** For PCIe: Low Threshold Setting= 0, High Threshold Setting= 2. 

**8.** For SATA: Low Threshold Setting= 2, High Threshold Setting= 3. 

**9.** Loss of signal is valid for data rates of 1 Gbps to 5 Gbps for PRBS7 (8B/10B) or PRBS31 (64b/6xb) data formats. It is also valid for detection of SATA out-of-band signals at data rates up to 6 Gbps. If the default settings for the low threshold (0x0) and high threshold (0x2) using the low range option for the peak detector are used, then the Rx VAmplitude pk-pk (outside of data eye) at the receiver input package pins must be a minimum of 300 mV for short reach (6.5 dB insertion loss at 5 GHz) applications, 350 mV for medium reach (17.0 dB insertion loss at 5 GHz) applications, and 450 mV for long reach (25.0 dB insertion loss at 5 GHz) applications—generally the settings are less limiting than what is required for good BER operation of the SerDes. Note that if the option to force CDR Lock2Ref upon Rx Idle is set (default at data rates of 5 Gbps and below), this minimum VAmplitude pk-pk must be enforced for proper CDR operation. 

**10.** Detect values measured at 1.5 Gbps with PRBS7 data pattern. 

**11.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

**12.** THGSTATE is based on the condition where the CDR was in lock (to reference or data) for at least 5.2 μs before moving to the high-gain state. At this point, if the receive data is outside the ppm tolerance of the CDR, the CDR will unlock after the time specified by the parameter. 

**13.** The following definitions apply: 

   - **a.** TCDRREF is the transceiver CDR reference clock period in nanoseconds. 

   - **b.** WXCVRFABRX is the parallel interface width of the transceiver receive fabric interface. 

   - **c.** CDRFBDIV is the feedback divider of the transceiver. 

   - **d.** CDRCDRREFDIV is the reference divider of the transceiver CDR. 

**14.** For details on the Enhanced Receiver Management feature, refer to UG0677: PolarFire FPGA Transceiver User Guide. 

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## **7.4.6 Transceiver and Receiver Return Loss Characteristics** 

This section describes transmitter and receiver return loss characteristics compliant with OIF-CEI-03.1. 

## **Figure 4 • Differential Return Loss** 

**Table 59 • Differential Return Loss** 

|**Parameter**|**Value**|**Unit**|
|---|---|---|
|A0|–8|dB|
|f0|100|MHz|
|f1|(3/4) * T_Baud|Hz|
|f2|T_Baud|Hz|



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**==> picture [310 x 31] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Parameter|Value|Unit|
|Slope|16.6|dB/dec|

**----- End of picture text -----**<br>


**Figure 5 • Common Mode Return Loss** 

**Table 60 • Common Mode Return Loss** 

**==> picture [301 x 75] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Parameter|Value|Unit|
|A0|–6|dB|
|f0|100|MHz|
|f1|(3/4) * T_Baud|Hz|

**----- End of picture text -----**<br>


## **7.5 Transceiver Protocol Characteristics** 

The following section describes transceiver protocol characteristics. 

## **7.5.1** 

## **PCI Express** 

The following tables describe the PCI express. 

**Table 61 • PCI Express Gen1** 

**==> picture [358 x 53] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Parameter|Data Rate|Min|Max|Unit|
|Total transmit jitter|2.5 Gbps|0.25|UI|
|Receiver jitter tolerance|2.5 Gbps|0.4|UI|

**----- End of picture text -----**<br>


Note: With add-in card, as specified in PCI Express CEM Rev 2.0. 

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**Table 62 • PCI Express Gen2** 

|**Parameter**|**Data Rate**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|Total transmit jitter|5.0 Gbps||0.35|UI|
|Receiver jitter tolerance|5.0 Gbps|0.4||UI|



Note: With add-in card as specified in PCI Express CEM Rev 2.0. 

## **7.5.2 Interlaken** 

The following table describes Interlaken. 

## **Table 63 • Interlaken** 

|**Parameter**|**Data Rate**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|Total transmit jitter|6.375 Gbps||0.3|UI|
||10.3125 Gbps||0.3|UI|
||12.7 Gbps1||0.3|UI|
|Receiver jitter tolerance|6.375 Gbps|0.6||UI|
||10.3125 Gbps|0.65||UI|
||12.7 Gbps1|0.65||UI|



**1.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

## **7.5.3 10GbE (10GBASE-R and 10GBASE-KR)** 

The following table describes 10GbE (10GBASE-R). 

## **Table 64 • 10GbE (10GBASE-R)** 

|**Parameter**|**Data Rate**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|Total transmit jitter|10.3125 Gbps||0.28|UI|
|Receiver jitter tolerance|10.3125 Gbps|0.7||UI|



The following table describes 10GbE (10GBASE-KR). 

## **Table 65 • 10GbE (10GBASE-KR)** 

|**Parameter**|**Data Rate**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|Total transmit jitter|10.3125 Gbps||0.28|UI|
|Receiver jitter tolerance<br>(SJ)|10.3125 Gbps|0.115||UI|
|Receiver jitter tolerance<br>(RJ)|10.3125 Gbps|0.13||UI|



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**==> picture [358 x 39] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Parameter|Data Rate|Min|Max|Unit|
|Receiver jitter tolerance|10.3125 Gbps|0.035|UI|
|(DCD)|

**----- End of picture text -----**<br>


The following table describes 10GbE (XAUI). 

## **Table 66 • 10GbE (XAUI)** 

**==> picture [358 x 95] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Parameter|Data Rate|Min|Max|Unit|
|Total transmit jitter|3.125 Gbps|0.35|UI|
|(near end)|
|Total transmit jitter (far|0.55|UI|
|end)|
|Receiver jitter tolerance|3.125 Gbps|0.65|UI|

**----- End of picture text -----**<br>


The following table describes 10GbE (RXAUI). 

## **Table 67 • 10GbE (RXAUI)** 

**==> picture [358 x 95] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Parameter|Data Rate|Min|Max|Unit|
|Total transmit jitter|6.25 Gbps|0.35|UI|
|(near-end)|
|Total transmit jitter (far-|6.25 Gbps|0.55|UI|
|end)|
|Receiver jitter tolerance|6.25 Gbps|0.65|UI|

**----- End of picture text -----**<br>


## **7.5.4 1GbE (1000BASE-X)** 

The following table describes 1GbE (1000BASE-X). 

## **Table 68 • 1GbE (1000BASE-X)** 

**==> picture [358 x 53] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Parameter|Data Rate|Min|Max|Unit|
|Total transmit jitter|1.25 Gbps|0.24|UI|
|Receiver jitter tolerance|1.25 Gbps|0.749|UI|

**----- End of picture text -----**<br>


## **7.5.5 SGMII and QSGMII** 

The following table describes SGMII. 

## **Table 69 • SGMII** 

**==> picture [358 x 53] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Parameter|Data Rate|Min|Max|Unit|
|Total transmit jitter|1.25 Gbps|0.24|UI|
|Receiver jitter tolerance|1.25 Gbps|0.749|UI|

**----- End of picture text -----**<br>


The following table describes QSGMII. 

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## **Table 70 • QSGMII** 

**==> picture [358 x 52] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Parameter|Data Rate|Min|Max|Unit|
|Total transmit jitter|5.0 Gbps|0.3|UI|
|Receiver jitter tolerance|5.0 Gbps|0.65|UI|

**----- End of picture text -----**<br>


## **7.5.6 CPRI** 

The following table describes CPRI. 

## **Table 71 • CPRI** 

**==> picture [358 x 364] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Parameter|Data Rate|Min|Max|Unit|
|Total transmit jitter|0.6144 Gbps|0.35|UI|
|1.2288 Gbps|0.35|UI|
|2.4576 Gbps|0.35|UI|
|3.0720 Gbps|0.35|UI|
|4.9152 Gbps|0.3|UI|
|6.1440 Gbps|0.3|UI|
|8.11008 Gbps|0.335|UI|
|9.8304 Gbps|0.335|UI|
|Receive jitter tolerance|0.6144 Gbps|0.75|UI|
|1.2288 Gbps|0.75|UI|
|2.4576 Gbps|0.75|UI|
|3.0720 Gbps|0.75|UI|
|4.9152 Gbps|0.7|UI|
|6.1440 Gbps|0.7|UI|
|8.11008 Gbps|0.7|UI|
|9.8304 Gbps|0.7|UI|

**----- End of picture text -----**<br>


## **7.5.7 JESD204B** 

The following table describes JESD204B. 

## **Table 72 • JESD204B** 

**==> picture [358 x 30] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Parameter|Data Rate|Min|Max|Unit|
|Total transmit jitter|3.125 Gbps|0.35|UI|

**----- End of picture text -----**<br>


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|**Parameter**|**Data Rate**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
||6.25 Gbps||0.3|UI|
||12.5 Gbps1||0.3|UI|
|Receive jitter tolerance|3.125 Gbps|0.56||UI|
||6.25 Gbps|0.6||UI|
||12.5 Gbps1|0.7||UI|



**1.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

## **7.5.8 Display Port** 

The following table describes Display Port. 

## **Table 73 • Display Port** 

|**Parameter**|**Data Rate**|**Condition**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Total transmit jitter|1.62 Gbps|Test point: TP2||0.27|UI|
||2.7 Gbps|Test point: TP2||0.42|UI|
||5.4 Gbps|Test point: TP3_EQ||0.62|UI|
|Receive jitter toler-<br>ance|1.62 Gbps|SJ at 20 MHz|0.747||UI|
||2.7 Gbps|SJ at 100 MHz|0.491||UI|
||5.4 Gbps|SJ at 10 MHz|0.636||UI|



## **7.5.9 Serial RapidIO** 

The following table describes Serial RapidIO. 

## **Table 74 • Serial RapidIO** 

|**Parameter**|**Data Rate**|**Condition**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Total transmit jitter|1.25 Gbps|||0.35|UI|
||2.5 Gbps|||0.35|UI|
||3.125 Gbps|||0.35|UI|
||5.0 Gbps|||0.3|UI|
||6.25 Gbps|||0.3|UI|
||10.3125 Gbps|||0.28|UI|
|Receive jitter toler-<br>ance|1.25 Gbps||0.65||UI|
|||||||



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**==> picture [372 x 164] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Data Rate|Condition|Min|Max|Unit|
|2.5 Gbps|0.65|UI|
|3.125 Gbps|0.65|UI|
|5.0 Gbps|Short reach|0.6|UI|
|Long reach|0.95|UI|
|6.25 Gbps|Short reach|0.6|UI|
|Long reach|0.95|UI|
|10.3125 Gbps|Short reach|0.62|UI|

**----- End of picture text -----**<br>


## **7.5.10 SDI** 

The following table describes SDI. 

## **Table 75 • SDI** 

**==> picture [372 x 269] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Data Rate|Condition|Min|Max|Unit|
|Total transmit jitter|270 Mbps|Timing jitter (10 H-|1.0|UI|
|z–27 MHz)|
|Alignment jitter (1|0.2|UI|
|KHz–27 MHz)|
|1.485 Gbps|Timing jitter (10 H-|1.0|UI|
|z–148.5 MHz)|
|Alignment jitter (10|0.2|UI|
|0 KHz–148.5 MHz)|
|2.97 Gbps|Timing jitter (10 H-|2.0|UI|
|z–297 MHz)|
|Alignment jitter (10|0.3|UI|
|0 KHz–297 MHz)|
|Receive jitter toler-|270 Mbps|Alignment jitter|0.2|UI|
|ance|
|1.485 Gbps|Alignment jitter|0.2|UI|
|2.97 Gbps|Alignment jitter|0.3|UI|

**----- End of picture text -----**<br>


## **7.5.11 OTN** 

The following table describes OTN. 

## **Table 76 • OTN** 

**==> picture [372 x 39] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Data Rate|Condition|Min|Max|Unit|
|Total transmit jitter|2.66 Gbps|3 dB BW: 5 KHz to|0.3|UI|
|20 MHz|

**----- End of picture text -----**<br>


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|**Parameter**|**Data Rate**|**Condition**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|||3 dB BW: 1 MHz to<br>20 MHz||0.1|UI|
||10.70 Gbps|3 dB BW: 20 KHz to<br>80 MHz||0.3|UI|
|||3 dB BW: 4 MHz to<br>80 MHz||0.1|UI|
||11.09 Gbps1|3 dB BW: 20 KHz to<br>80 MHz||0.3|UI|
|||3 dB BW: 4 MHz to<br>80 MHz||0.1|UI|
|Receive jitter toler-<br>ance|2.66 Mbps|SJ at 5 KHz|1.5||UI|
|||SJ at 20 MHz|0.15||UI|
||10.70 Gbps|SJ at 20 KHz|1.5||UI|
|||SJ at 80 MHz|0.15||UI|
||11.09 Gbps1|SJ at 20 KHz|1.5||UI|
|||SJ at 80 MHz|0.15||UI|



**1.** For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 

## **7.5.12 Fiber Channel** 

The following table describes Fiber Channel. 

## **Table 77 • Fiber Channel** 

|**Parameter**|**Data Rate**|**Condition**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Total transmit jitter|1.0625 Gbps|||0.23|UI|
||2.125 Gbps|||0.33|UI|
||4.25 Gbps|||0.52|UI|
||8.5 Gbps|||0.31|UI|
|Receive jitter toler-<br>ance|1.0625 Gbps|0.68|||UI|
||2.125 Gbps|0.62|||UI|
||4.24 Gbps|0.62|||UI|
||8.5 Gbps|0.71|||UI|



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## **7.5.13 HiGig and HiGig+** 

The following table describes HiGig and HiGig+. 

## **Table 78 • HiGig and HiGig+** 

|**Parameter**|**Data Rate**|**Condition**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Total transmit jitter|3.75 Gbps|Near-end||0.35|UI|
||3.75 Gbps|Far-end||0.55|UI|
|Receive jitter toler-<br>ance|3.75 Gbps||0.65||UI|



## **7.5.14 HiGig II** 

The following table describes HiGig II. 

## **Table 79 • HiGig II** 

|**Parameter**|**Data Rate**|**Condition**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Total transmit jitter|6.875 Gbps|Near-end||0.35|UI|
||6.875 Gbps|Far-end||0.55|UI|
|Receive jitter toler-<br>ance|6.875 Gbps||0.65||UI|



## **7.5.15 Firewire IEEE 1394** 

The following table describes Firewire. 

## **Table 80 • FireWire IEEE1394** 

|**Parameter**|**Data Rate**|**Condition**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Total transmit jitter|393.22 Mbps|S400 Near-end||557|ps|
||786.43 Mbps|S800 Near-end||200|ps|
|Receive jitter toler-<br>ance|393.22 Mbps|S400|1025||ps|
||786.43 Mbps|S800|375||ps|



## **7.6 Non-Volatile Characteristics** 

The following section describes non-volatile characteristics. 

## **7.6.1 FPGA Programming Cycle and Retention** 

The following table describes FPGA programming cycle and retention. 

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**Table 81 • FPGA Programming Cycles vs Retention Characteristics** 

|**Programming TJ**|**Programming Cycles, Max**|**Retention Years**|**Retention Years at TJ**|
|---|---|---|---|
|0 °C to 85 °C|1000|20|85 °C|
|0 °C to 100 °C|500|20|100 °C|
|–20 °C to 100 °C|500|20|100 °C|
|–40 °C to 100 °C|500|20|100 °C|
|–40 °C to 85 °C|1000|16|100 °C|
|–40 °C to 55 °C|2000|12|100 °C|



Note: Power supplied to the device must be valid during programming operations such as programming and verify . Programming recovery mode is available only for in-application programming mode and requires an external SPI flash. 

## **7.6.2 FPGA Programming Time** 

The following tables describe FPGA programming time. 

## **Table 82 • Master SPI Programming Time (IAP)** 

|**Parameter**|**Symbol**|**Devices**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Programming time|TPROG|MPF100T, TL, TS, T-<br>LS|17|25|s|
|||MPF200T, TL, TS, T-<br>LS|17|25|s|
|||MPF300T, TL, TS, T-<br>LS|26|32|s|
|||MPF500T, TL, TS, T-<br>LS|31|37|s|



**Table 83 • Slave SPI Programming Time** 

|**Parameter**|**Symbol**|**Devices**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Programming time|TPROG|MPF100T, TL, TS, T-<br>LS1|27|33|s|
|||MPF200T, TL, TS, T-<br>LS1|41|50|s|
|||MPF300T, TL, TS, T-<br>LS1|50|60|s|
|||MPF500T, TL, TS, T-<br>LS1|90|108|s|



**1.** SmartFusion2 as SPI Master with MSS running at 100 MHz, MSS_SPI_0 port running at 6.67 MHz. Bitstream stored in DDR. DirectC version 4.1. 

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**2.** Programmer: FlashPro5 with TCK 10 MHz. PC Configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10. 

**Table 84 • JTAG Programming Time** 

|**Parameter**|**Symbol**|**Devices**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Programming time|TPROG|MPF100T, TL, TS, T-<br>LS1|35|42|s|
|||MPF200T, TL, TS, T-<br>LS1|56|68|s|
|||MPF300T, TL, TS, T-<br>LS1|95|114|s|
|||MPF500T, TL, TS, T-<br>LS1|122|147|s|



**1.** Programmer: FlashPro5 with TCK 10 MHz. PC Configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10. 

## **7.6.3 FPGA Bitstream Sizes** 

The following table describes FPGA bitstream sizes. 

## **Table 85 • Initialization Client Sizes** 

|**Device**|**Plaintext**|**Ciphertext**|
|---|---|---|
|MPF100T, TL, TS, TLS|1580 KB|1630 KB|
|MPF200T, TL, TS, TLS|2916 KB|3006 KB|
|MPF300T, TL, TS, TLS|4265 KB|4403 KB|
|MPF500T, TL, TS, TLS|6835 KB|7045 KB|



Note: Worst case initializing all fabric LSRAM, USRAM, and UPROM. 

**Table 86 • Bitstream Sizes** 

|**File**|**Devices**|**FPGA**|**Security**|**SNVM (all**<br>**pages)**|**FPGA+SNV-**<br>**M**|**FPGA+ Sec**|**SNVM+ Sec**|**FPGA+SNV-**<br>**M+ Sec**|
|---|---|---|---|---|---|---|---|---|
|SPI|MPF100T,<br>TL, TS, TLS|3.4 MB|3.5 KB|59.7 KB|3.5 MB|3.5 MB|62.2 KB|3.5 MB|
|DAT|MPF100T,<br>TL, TS, TLS|3.4 MB|7.6 KB|61.2 KB|3.5 MB|3.4 MB|66.3 KB|3.5 MB|
|SPI|MPF200T,<br>TL, TS, TLS|5.9 MB|3.5 KB|59.7 KB|5.9 MB|5.9 MB|62.2 KB|6.0 MB|
|DAT|MPF200T,<br>TL, TS, TLS|5.9 MB|7.6 KB|61.2 KB|6.0 MB|5.9 MB|66.3 KB|6.0 MB|
|SPI|MPF300T,<br>TL, TS, TLS|9.3 MB|3.5 KB|59.7 KB|9.6 MB|9.5 MB|62.2 KB|9.6 MB|



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**==> picture [420 x 115] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|File|Devices|FPGA|Security|SNVM (all|FPGA+SNV-|FPGA+ Sec|SNVM+ Sec|FPGA+SNV-|
|pages)|M|M+ Sec|
|DAT|MPF300T,|9.3 MB|7.6 KB|61.2 KB|9.6 MB|9.5 MB|66.3 KB|9.6 MB|
|TL, TS, TLS|
|SPI|MPF500T,|14.3 MB|3.5 KB|59.7 KB|14.4 MB|14.3 MB|62.2 KB|14.4 MB|
|TL, TS, TLS|
|DAT|MPF500T,|14.3 MB|7.6 KB|61.2 KB|14.4 MB|14.3 MB|66.3 KB|14.4 MB|
|TL, TS, TLS|

**----- End of picture text -----**<br>


## **7.6.4 Digest Cycles** 

Digests verify the integrity of the programmed non-volatile data. Digests are a cryptographic hash of various data areas. Any digest that reports back an error raises the digest tamper flag. 

## **Table 87 • Maximum Number of Digest Cycles** 

**==> picture [410 x 171] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|
|Retention Since Programmed (N = Number Digests During that Time)|[1]|
|Digest TJ|Storage and|N ≤30|N = 500|N = 1000|N = 1500|N = 2000|N = 4000|N = 6000|Unit|Reten-|
|Operating TJ|0|tion|
|–40 to 1|–40 to 100|20 × L-|17 × LF|12 × LF|10 × LF|8 × LF|4 × LF|2 × LF|°C|Years|
|00|F|
|–40 to 1|0 to 100|20 × L-|17 × LF|12 × LF|10 × LF|8 × LF|4 × LF|2 × LF|°C|Years|
|00|F|
|–40 to 8|–40 to 85|20 × L-|20 × LF|20 × LF|20 × LF|16 × LF|8 × LF|4 × LF|°C|Years|
|5|F|
|–40 to 5|–40 to 55|20 × L-|20 × LF|20 × LF|20 × LF|20 × LF|20 × LF|20 × LF|°C|Years|
|5|F|

**----- End of picture text -----**<br>


**1.** LF = Lifetime factor as defined by the number of programming cycles the device has seen under the conditions listed in the following table. 

**Table 88 • FPGA Programming Cycles Lifetime Factor** 

**==> picture [297 x 74] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Programming TJ|Programming Cycles|LF|
|–40 °C to 100 °C|500|1|
|–40 °C to 85 °C|1000|0.8|
|–40 °C to 55 °C|2000|0.6|

**----- End of picture text -----**<br>


Notes: 

- The maximum number of device digest cycles is 100K. 

- Digests are operational only over the –40 °C to 100 °C temperature range. 

- After a program cycle, an additional N digests cycles are allowed with the resultant retention characteristics for the total operating and storage temperature shown. 

- Retention is specified for total device storage and operating temperature. 

- All temperatures are junction temperatures (TJ). 

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- Example 1—500 digests cycles are performed between programming cycles. N = 500. The operating conditions are –40 °C to 85 °C TJ. 501 programming cycles have occurred. The retention under these operating conditions is 20 × LF = 20 × .8 = 16 years. 

- Example 2—one programming cycle has occurred, N = 1500 digest cycles have occurred. Temperature range is –40 °C to 100 °C. The resultant retention is 10 × LF or 10 years over the industrial temperature range. 

## **7.6.5 Digest Time** 

The following table describes digest time. 

## **Table 89 • Digest Times** 

|**Parameter**|**Devices**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|Setup time|All|2||μs|
|Fabric digest run time|MPF100T, TL, TS, TLS|880|910|ms|
||MPF200T, TL, TS, TLS|1005|1072|ms|
||MPF300T, TL, TS, TLS|1503.9|1582|ms|
||MPF500T, TL, TS, TLS|2085|2150|ms|
|UFS CC digest run time|MPF100T, TL, TS, TLS|33.5|35|μs|
||MPF200T, TL, TS, TLS|33.5|35|μs|
||MPF300T, TL, TS, TLS|33.5|35|μs|
||MPF500T, TL, TS, TLS|33.5|35|μs|
|sNVM digest run time1|MPF100T, TL, TS, TLS|4.5|5|ms|
||MPF200T, TL, TS, TLS|4.5|5|ms|
||MPF300T, TL, TS, TLS|4.5|5|ms|
||MPF500T, TL, TS, TLS|4.5|5|ms|
|UFS UL digest run time|MPF100T, TL, TS, TLS|47|49|μs|
||MPF200T, TL, TS, TLS|47|49|μs|
||MPF300T, TL, TS, TLS|47|49|μs|
||MPF500T, TL, TS, TLS|47|49|μs|
|User key digest run<br>time2|MPF100T, TL, TS, TLS|526|544|μs|
||MPF200T, TL, TS, TLS|526|544|μs|
||MPF300T, TL, TS, TLS|526|544|μs|
||MPF500T, TL, TS, TLS|526|544|μs|
|UFS UPERM digest run<br>time|MPF100T, TL, TS, TLS|33.2|35|μs|
||||||



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|**Parameter**|**Devices**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
||MPF200T, TL, TS, TLS|33.2|35|μs|
||MPF300T, TL, TS, TLS|33.2|35|μs|
||MPF500T, TL, TS, TLS|33.2|35|μs|
|Factory digest run time|MPF100T, TL, TS, TLS|494|511|μs|
||MPF200T, TL, TS, TLS|494|511|μs|
||MPF300T, TL, TS, TLS|494|511|μs|
||MPF500T, TL, TS, TLS|494|511|μs|



**1.** The entire sNVM is used as ROM. 

**2.** Valid for user key 0 through 6. 

Note: These times do not include the power-up to functional timing overhead when using digest checks on power-up. 

## **7.6.6 Zeroization Time** 

This section describes zeroization time. A zeroization operation counts as one programming cycle. 

**Table 90 • Zeroization Times for MPF100T, TL, TS, and TLS Devices** 

|**Parameter**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|
|Time to enter zeroiza-<br>tion|8|9|ms|Zip flag set|
|Time to destroy the<br>fabric data1|248|253|ms|Data erased|
|Time to destroy data in<br>non-volatile memory<br>(like new)1, 2|507|522|ms|One iteration of scrub-<br>bing|
|Time to destroy data in<br>non-volatile memory<br>(non-recoverable)1, 3|520|536|ms|One iteration of scrub-<br>bing|
|Time to scrub the fabric<br>data1|0.8|0.9|s|Full scrubbing|
|Time to scrub the pNV-<br>M data (like new)1, 2|1.5|1.6|s|Full scrubbing|
|Time to scrub the fabric<br>data pNVM data (non-<br>recoverable)1, 3|1.7|1.8|s|Full scrubbing|
|Time to verify5|1.1|1.2|s||
|Total time to zeroize<br>(like new)1, 2|2.8|2.9|s||



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|**Parameter**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|
|Total time to zeroize<br>(non-recoverable)1, 3|3.1|3.2|s||



**1.** Total completion time after entering zeroization. 

**2.** Like new mode—zeroizes user design security setting and sNVM content. 

**3.** Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data required for programming. 

**4.** Time to verify after scrubbing completes. 

**Table 91 • Zeroization Times for MPF200T, TL, TS, and TLS Devices** 

|**Parameter**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|
|Time to enter zeroiza-<br>tion|8|9|ms|Zip flag set|
|Time to destroy the<br>fabric data1|250|255|ms|Data erased|
|Time to destroy data in<br>non-volatile memory<br>(like new)1, 2|507|522|ms|One iteration of scrub-<br>bing|
|Time to destroy data in<br>non-volatile memory<br>(non-recoverable)1, 3|520|536|ms|One iteration of scrub-<br>bing|
|Time to scrub the fabric<br>data1|0.9|1.0|s|Full scrubbing|
|Time to scrub the pNV-<br>M data (like new)1, 2|1.5|1.6|s|Full scrubbing|
|Time to scrub the fabric<br>data PNVM data (non-<br>recoverable)1, 3|1.7|1.8|s|Full scrubbing|
|Time to verify5|1.4|1.5|s||
|Total time to zeroize<br>(like new)1, 2|2.9|3.0|s||
|Total time to zeroize<br>(non-recoverable)1, 3|3.1|3.2|s||



**1.** Total completion time after interning zeroization. 

**2.** Like new mode—zeroizes user design security setting and sNVM content. 

**3.** Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data required for programming. 

**4.** Time to verify after scrubbing completes. 

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**Table 92 • Zeroization Times for MPF300T, TL, TS, and TLS Devices** 

|**Parameter**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|
|Time to enter zeroiza-<br>tion|8|9|ms|Zip flag set|
|Time to destroy the<br>fabric data1|390|420|ms|One iteration of scrub-<br>bing|
|Time to destroy data in<br>non-volatile memory<br>(like new)1, 2|507|522|ms|One iteration of scrub-<br>bing|
|Time to destroy data in<br>non-volatile memory<br>(non- recoverable)1, 3|520|536|ms|One iteration of scrub-<br>bing|
|Time to scrub the fabric<br>data1|1.3|1.4|s|Full scrubbing|
|Time to scrub the pNV-<br>M data (like new)1, 2|1.5|1.6|s|Full scrubbing|
|Time to scrub the fabric<br>data pNVM data (non-<br>recoverable)1, 3|1.7|1.8|s|Full scrubbing|
|Time to verify5|1.8|1.9|s||
|Total time to zeroize<br>(like new)1, 2|3.7|3.8|s||
|Total time to zeroize<br>(non-recoverable)1, 3|3.9|4|s||



**1.** Total completion time after interning zeroization. 

**2.** Like new mode—zeroizes user design security setting and sNVM content. 

**3.** Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data required for programming. 

**4.** Time to verify after scrubbing completes. 

**Table 93 • Zeroization Times for MPF500T, TL, TS, and TLS Devices** 

|**Parameter**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|
|Time to enter zeroiza-<br>tion|8|9|ms|Zip flag set|
|Time to destroy the<br>fabric data1|392|422|ms|One iteration of scrub-<br>bing|
|Time to destroy data in<br>non-volatile memory<br>(like new)1, 2|507|522|ms|One iteration of scrub-<br>bing|



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|**Parameter**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|
|Time to destroy data in<br>non-volatile memory<br>(non-recoverable)1, 3|520|536|ms|One iteration of scrub-<br>bing|
|Time to scrub the fabric<br>data1|1.4|1.5|s|Full scrubbing|
|Time to scrub the pNV-<br>M data (like new)1, 2|1.5|1.6|s|Full scrubbing|
|Time to scrub the fabric<br>data pNVM data (non-<br>recoverable)1, 3|1.7|1.8|s|Full scrubbing|
|Time to verify5|1.9|2.0|s||
|Total time to zeroize<br>(like new)1, 2|3.8|3.9|s||
|Total time to zeroize<br>(non-recoverable)1, 3|4.0|4.1|s||



**1.** Total completion time after entering zeroization. 

**2.** Like new mode—zeroizes user design security setting and sNVM content. 

**3.** Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data required for programming. 

**4.** Time to verify after scrubbing completes. 

## **7.6.7 Verify Time** 

The following tables describe verify time. 

## **Table 94 • Standalone Fabric Verify Times** 

|**Parameter**|**Devices**|**Max**|**Unit**|
|---|---|---|---|
|Standalone verification over J-<br>TAG|MPF100T, TL, TS, TLS1|33|s|
||MPF200T, TL, TS, TLS1|53|s|
||MPF300T, TL, TS, TLS1|90|s|
||MPF500T, TL, TS, TLS1|114|s|
|Standalone verification over S-<br>PI|MPF100T, TL, TS, TLS2|24|s|
||MPF200T, TL, TS, TLS2|37|s|
||MPF300T, TL, TS, TLS2|55|s|
||MPF500T, TL, TS, TLS2|89|s|



**1.** Programmer: FlashPro5, TCK 10 MHz; PC configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10. 

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**2.** SmartFusion2 with MSS running at 100 MHz, MSS_SPI_0 port running at 6.67 MHz. Bitstream stored in DDR. DirectC version 4.1. 

## Notes: 

- Standalone verify is limited to 2,000 total device hours over the industrial –40 °C to 100 °C temperature. 

- Use the digest system service, for verify device time more than 2,000 hours. 

- Standalone verify checks the programming margin on both the P and N gates of the push-pull cell. 

- Digest checks only the P side of the push-pull gate. However, the push-pull gates work in tandem. Digest check is recommended if users believe they will exceed the 2,000-hour verify time specification. 

**Table 95 • Verify Time by Programming Hardware** 

|**Devices**|**IAP**|**FlashPro4**|**FlashPro5**|**BP**|**Silicon Sculptor**|**Units**|
|---|---|---|---|---|---|---|
|MPF100T,TL,TS-<br>, TLS|6|42|33|||s|
|MPF200T,TL,TS-<br>, TLS|9|67|53|||s|
|MPF300T,TL,TS-<br>, TLS|14|95|90|||s|
|MPF500T,TL,TS-<br>, TLS|15|169|114|||s|



Notes: 

- FlashPro4 4 MHz TCK. 

- FlashPro5 10 MHz TCK. 

- PC configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10. 

**Table 96 • Verify System Services** 

|**Parameter**|**Symbol**|**ServiceID**|**Devices**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|In application<br>verify by index|TIAP_Ver_Index|44H|MPF100T,TL,TS-<br>, TLS|5.9|6.2|s|
||||MPF200T,TL,TS-<br>, TLS|8.2|9|s|
||||MPF300T,TL,TS-<br>, TLS|12.4|13|s|
||||MPF500T,TL,TS-<br>, TLS|13.4|14|s|
|In application<br>verify by SPI ad-<br>dress|TIAP_Ver_Addr|45H|MPF100T,TL,TS-<br>, TLS|5.9|6.2|s|
||||MPF200T,TL,TS-<br>, TLS|8.2|9|s|
||||MPF300T,TL,TS-<br>, TLS|12.4|13|s|
||||MPF500T,TL,TS-<br>, TLS|13.4|14|s|



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## **7.6.8 Authentication Time** 

The following tables describe authentication system service time. 

## **Table 97 • Authentication Services** 

|**Parameter**|**Symbol**|**ServiceID**|**Devices**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Bitstream A-<br>uthentication|TBIT_AUTH|22H|MPF100T,TL,TS-<br>, TLS|2.1|2.4|s|
||||MPF200T,TL,TS-<br>, TLS|3.3|3.7|s|
||||MPF300T,TL,TS-<br>, TLS|4.9|5.4|s|
||||MPF500T,TL,TS-<br>, TLS|7.6|7.8|s|
|IAP Image A-<br>uthentication|TIAP_AUTH|23H|MPF100T,TL,TS-<br>, TLS|2.1|2.4|s|
||||MPF200T,TL,TS-<br>, TLS|3.3|3.7|s|
||||MPF300T,TL,TS-<br>, TLS|4.9|5.4|s|
||||MPF500T,TL,TS-<br>, TLS|7.6|7.8|s|



## **7.6.9 Secure NVM Performance** 

The following table describes secure NVM performance. 

## **Table 98 • sNVM Read/Write Characteristics** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|---|---|
|Plain text pro-<br>gramming||7.0|7.2|7.9|ms||
|Authenticated<br>text program-<br>ming||7.2|7.4|9.4|ms||
|Authenticated<br>and encrypted<br>text program-<br>ming||7.2|7.4|9.4|ms||
|Authentication<br>R/W 1st access<br>from power-up<br>overhead|TPUF_OVHD|10|13|111|ms|From TFAB_READY|
|Plain text read||8|8.5|9|μs||



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|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|---|---|
|Authenticated<br>text read||113|114.5|119|μs||
|Authenticated<br>and decrypted<br>text read||159|161|167|μs||



Notes: 

- Page size= 256 bytes (non-authenticated), 236 bytes (authenticated). 

- Only page reads and writes allowed. 

- TPUF_OVHD is an additional time that occurs on the first R/W, after cold or warm boot, to sNVM using authenticated or authenticated and encrypted text. 

## **7.6.10 Secure NVM Programming Cycles** 

The following table describes secure NVM programming cycles. 

## **Table 99 • sNVM Programming Cycles vs. Retention Characteristics** 

|**Programming Temperature**|**Programming Cycles per Page,**<br>**Max**|**ProgrammingCyclesperBlock,**<br>**Max**|**Retention Years**|
|---|---|---|---|
|–40 °C to 100 °C|10,000|100,000|20|
|–40 °C to 85 °C|10,000|100,000|20|
|–40 °C to 55 °C|10,000|100,000|20|



Note: Page size = 256 bytes. Block size = 56 KBytes. 

## **7.7 System Services** 

This section describes system switching and throughput characteristics. 

## **7.7.1 System Services Throughput Characteristics** 

The following table describes system services throughput characteristics. 

## **Table 100 • System Services Throughput Characteristics** 

|**Parameter**|**Symbol**|**Service ID**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|---|---|
|Serial number|TSerial|00H|65|67|μs||
|User code|TUser|01H|0.8|1.2|μs||
|Design informa-<br>tion|TDesign|02H|2.5|3|μs||
|Device certifi-<br>cate|TCert|03H|255|271|ms||
|Read digests|Tdigest_read|04H|201|215|μs||



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|**Parameter**|**Symbol**|**Service ID**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|---|---|
|Query security<br>locks|Tsec_Query|05H|15|17|μs||
|Read debug in-<br>formation|TRd_debug|06H|34|38|μs||
|Reserved||07H–0FH|||||
|Secure NVM<br>write plain text|TSNVM_Wr_Plain|10H||||Note 1|
|Secure NVM<br>write authenti-<br>cated plain text|TSNVM_Wr_Auth|11H||||Note 1|
|Secure NVM<br>write authenti-<br>cated cipher<br>text|TSNVM_Wr_Cipher|12H||||Note 1|
|Reserved||13H–17H|||||
|Secure NVM<br>read|TSNVM_Rd|18H||||Note 1|
|Digital signature<br>service raw|TSIG_RAW|19H|174|187|ms||
|Digital signature<br>service DER|TSIG_DER|1AH|174|187|ms||
|Reserved||1BH–1FH|||||
|PUF emulation|TChallenge|20H|1.8|2.0|ms||
|Nonce service|TNonce|21H|1.2|1.5|ms||
|Bitstream au-<br>thentication|TBIT_AUTH|22H||||Note 4|
|IAP Image au-<br>thentication|TIAP_AUTH|23H||||Note 4|
|Reserved||26H–3FH|||||
|In application<br>programmingby<br>index|TIAP_Prg_Index|42H||||Note 2|
|In application<br>programmingby<br>SPI address|TIAP_Prg_Addr|43H||||Note 2|
|In application<br>verify by index|TIAP_Ver_Index|44H||||Note 5|



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|**Parameter**|**Symbol**|**Service ID**|**Typ**|**Max**|**Unit**|**Conditions**|
|---|---|---|---|---|---|---|
|In application<br>verify by SPI ad-<br>dress|TIAP_Ver_Addr|45H||||Note 5|
|Auto update|TAutoUpdate|46H||||Note 2|
|Digest check|Tdigest_chk|47H||||Note 3|



**1.** See sNVM Read/Write Characteristics. 

**2.** See SPI Master Programming Time. 

**3.** See Digest Times. 

**4.** See Authentication Services Time. 

**5.** See Verify Services Time. 

**6.** Throughputs described are measured from SS_REQ assertion to BUSY de-assertion. 

## **7.8 Fabric Macros** 

This section describes switching characteristics of UJTAG, UJTAG_SEC, USPI, system controller, and temper detectors and dynamic reconfiguration. 

## **7.8.1 UJTAG Switching Characteristics** 

The following section describes characteristics of UJTAG switching. 

## **Table 101 • UJTAG Performance Characteristics** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|TCK frequency|FTCK|||25|MHz||



**Figure 6 • UJTAG Timing Diagram** 

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## **7.8.2 UJTAG_SEC Switching Characteristics** 

The following table describes characteristics of UJTAG_SEC switching. 

## **Table 102 • UJTAG Security Performance Characteristics** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|TCK frequency|FTCK||||MHz||



## **7.8.3 USPI Switching Characteristics** 

The following section describes characteristics of USPI switching. 

## **Table 103 • SPI Macro Interface Timing Characteristics** 

|**Parameter**|**Symbol**|**VDDI = 3.3 V**<br>**Max**|**VDDI = 2.5 V**<br>**Max**|**VDDI = 1.8 V**<br>**Max**|**VDDI = 1.5 V**<br>**Max**|**VDDI = 1.2 V**<br>**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|Propagation<br>delay from<br>the fabric to<br>pins1|TPD_MOSI|0.8|1|1.2|1.4|1.6|ns|
||TPD_MISO|3.5|3.75|4|4.25|4.5|ns|
||TPD_SS|3.5|3.75|4|4.25|4.5|ns|
||TPD_SCK|3.5|3.75|4|4.25|4.5|ns|
||TPD_MOSI_O-<br>E|3.5|3.75|4|4.25|4.5|ns|
||TPD_SS_OE|3.5|3.75|4|4.25|4.5|ns|
||TPD_SCK_OE|3.5|3.75|4|4.25|4.5|ns|



**1.** Assumes CL of the relevant I/O standard as described in the input and output delay measurement tables. 

## **Figure 7 • USPI Switching Characteristics** 

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## **7.8.4 Tamper Detectors** 

The following section describes tamper detectors. 

## **Table 104 • ADC Conversion Rate** 

|**Parameter**|**Description**|**Min**|**Typ1**|**Max**|**Unit**|
|---|---|---|---|---|---|
|TCONV1|Time from enable<br>changing from zero<br>to non-zero value<br>to first conversion<br>completes. Mini-<br>mum value applies<br>when POWEROFF =<br>0.|350||470|μs|
|TCONVN|Time between sub-<br>sequent channel<br>conversions.||480||μs|
|TSETUP|Data channel and<br>output to valid as-<br>serted. Data is held<br>until next conver-<br>sion completes,<br>that is >480 μs.|0|||ns|
|TVALID<br>2|Width of the valid<br>pulse.|1.5||2.5|μs|
|TRATE|Time from start of<br>first set of conver-<br>sions to the start of<br>the next set. Can be<br>considered as the<br>conversion rate. Is<br>set by the conver-<br>sion rate parame-<br>ter.||Rate × 32||μs|



**1.** Min, typ, and max refer to variation due to functional configuration and the raw TVS value. The actual internal correction time will vary based on the raw TVS value. 

**2.** The pulse width varies depending on the time taken to complete the internal calibration multiplication, this can be up to 375 ns. 

Note: Once the TVS block is active, the enable signal is sampled 25 ns before the falling edge of valid. The next enabled channel in the sequence 0-1-2-3 is started; that is, if channel 0 has just completed and only channels 0 and 3 are enabled, the next channel will be 3. When all the enabled channels in the sequence 0-1-2-3 are completed, the TVS waits for the conversion rate timer to expire. The enable signal may be changed at any time if it changes to 4’b0000 while valid is asserted (and 25 ns before valid is de-asserted), then no further conversions will be started. 

**Table 105 • Temperature and Voltage Sensor Electrical Characteristics** 

|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|
|Temperature sens-<br>ing range|–40||125|°C||



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|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|
|Temperature sens-<br>ing accuracy|–10||10|°C||
|Voltage sensing<br>range|0.9||2.8|V||
|Voltage sensing ac-<br>curacy|–3.0||3.0|%||



## **Table 106 • Tamper Macro Timing Characteristics—Flags and Clearing** 

|**Parameter**|**Symbol**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|From event detection to<br>flag generation|TJTAG_ACTIVE<br>1|28|35|ns|
||TMESH_ERR<br>1|1.8|2.5|μs|
||TCLK_GLITCH<br>1||50|ns|
||TCLK_FREQ<br>1||4|μs|
||TLOW_VDD<br>1, 3|70|1000|μs|
||THIGH_VDD18<br>1, 3|85|1000|μs|
||THIGH_VDD25<br>1, 3|130|1000|μs|
||TSECDEC<br>1||5|ns|
||TDRI_ERR<br>1|14|18|μs|
||TWDOG<br>1||5|ns|
||TLOCK_ERR<br>1||5|ns|
|Time from system con-<br>trollerinstructionexecu-<br>tion to flag generation|TINST_BUF_ACCESS<br>1, 2|4|5|μs|
||TINST_DEBUG<br>1, 2|3.3|4|μs|
||TINST_CHK_DIGEST<br>1, 2|1.8|3|μs|
||TINST_EC_SETUP<br>1, 2|1.8|2|μs|
||TINST_FACT_PRIV<br>1, 2|3.8|5|μs|
||TINST_KEY_VAL<br>1, 2|2.5|3.5|μs|
||TINST_MISC<br>1, 2|1.5|2|μs|
||TINST_PASSCODE_MATCH<br>1, 2|2.5|3|μs|
||TINST_PASSCODE_SETUP<br>1, 2|4.2|5|μs|
||TINST_PROG<br>1, 2|3.8|4.5|μs|



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|**Parameter**|**Symbol**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
||TINST_PUB_INFO<br>1, 2|4|4.5|μs|
||TINST_ZERO_RECO<br>1, 2|2.5|3|μs|
||TINST_PASSCODE_FAIL<br>1, 2|170|180|μs|
||TINST_KEY_VAL_FAIL<br>1, 2|92|110|μs|
||TINST_UNUSED<br>1, 2|4|5|μs|
|Time from sending the<br>CLEAR to deassertionon<br>FLAG|TCLEAR_FLAG|17|23|ns|



**1.** The timing does not impact the user design, but it is useful for security analysis. 

**2.** System service requests from the fabric will interrupt the system controller delaying the generation of the flag. 

**3.** Timing of these depends highly on supply ramp rate. 

**Table 107 • Tamper Macro Response Timing Characteristics** 

|**Parameter**|**Symbol**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|Timefrom triggeringthe<br>response to all I/Os dis-<br>abled|TIO_DISABLE|45|63|ns|
|Time from negation of<br>RESPONSE to all I/Os re-<br>enabled|TCLR_IO_DISABLE|34|51|ns|
|Timefrom triggeringthe<br>response to security<br>locked|TLOCKDOWN||20|ns|
|Time from negation of<br>RESPONSE to earlier se-<br>curity unlock condition|TCLR_LOCKDOWN||20|ns|
|Timefrom triggeringthe<br>response to device en-<br>ters RESET|Ttr_RESET|11.7|14|μs|
|Timefrom triggeringthe<br>response to start of ze-<br>roization|Ttr_ZEROLISE|7.4|8.2|ms|



## **7.8.5 System Controller Suspend Switching Characteristics** 

The following table describes the characteristics of system controller suspend switching. 

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**Table 108 • System Controller Suspend Entry and Exit Characteristics** 

**==> picture [372 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||
|---|---|---|---|---|---|---|
|Parameter|Symbol|Definition|Typ|Max|Unit|
|Time from TRSTb|Tsuspend_Tr|1, 2|Suspend entry time|42|44|ns|
|falling edge to SUS-|from TRST_N asser-|
|PEND_EN signal as-|tion|
|sertion|
|Time from TRSTb|Tsuspend_exit|Suspend exit time|361|372|ns|
|rising edge to ACTI-|from TRST_N nega-|
|VE signal assertion|tion|

**----- End of picture text -----**<br>


**1.** ACTIVE indicates that the system controller is inactive or active regardless of the state of SUSPEND_EN. 

**2.** ACTIVE signal must never be asserted with SUSPEND_EN is asserted. 

## **7.8.6 Dynamic Reconfiguration Interface** 

The following table provides interface timing information for the DRI, which is an embedded APB slave interface within the FPGA fabric that does not use FPGA resources. 

**Table 109 • Dynamic Reconfiguration Interface Timing Characteristics** 

**==> picture [337 x 32] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|Parameter|Symbol|Max|Unit|
|PCLK frequency|FPD _PCLK|200|MHz|

**----- End of picture text -----**<br>


## **7.8.7 User Voltage Detector Characteristics** 

The following table provides the electrical characteristics of the VDD (1.0 V), VDD18, and VDD25 voltage detectors. For proper operation of the voltage detectors, Vdd must be set to 1.0 V. 

**Table 110 • User Voltage Detector Electrical Characteristics** 

**==> picture [419 x 253] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Min|Typ|Max|Unit|Condition|
|VDD_HIGH_DET|1.04|1.07|V|Temp= –40 ºC to 1|
|00 ºC; VDD18 = 1.8|
|V ±5%; VDD25= 2.5|
|V ±5%|
|VDD18_HIGH_DET|1.9|1.96|V|Temp= –40 ºC to 1|
|00 ºC; VDD = 1.0 V|
|±3%; VDD25= 2.5 V|
|±5%|
|VDD25_HIGH_DET|2.66|2.74|V|Temp= –40 ºC to 1|
|00 ºC; VDD = 1.0 V|
|±3%; VDD18= 1.8 V|
|±5%|
|VDD_LOW_DET|0.945|0.915|V|Temp= –40 ºC to 1|
|00 ºC; VDD18 = 1.8|
|±5%; VDD25= 2.5 V|
|±5%|
|VDD18_LOW_DET|1.62|1.57|V|Temp= –40 ºC to 1|
|00 ºC; VDD = 1.0 ±3|

**----- End of picture text -----**<br>


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|**Parameter**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|
||||||%; VDD25= 2.5 V ±5<br>%|
|VDD25_LOW_DET|2.31||2.21|V|Temp= –40 ºC to 1<br>00 ºC; VDD= 1.0 ±3<br>%; VDD18= 1.8 V ±5<br>%|



## **7.9 Power-Up to Functional Timing** 

Microsemi non-volatile FPGA technology offers the fastest boot-time of any mid-range FPGA in the market. The following tables describes both cold-boot (from power-on) and warm-boot (assertion of DEVRST_N pin or assertion of reset from the tamper macro) timing. The power-up diagrams assume all power supplies to the device are stable. 

## **7.9.1 Power-On (Cold) Reset Initialization Sequence** 

The following cold reset timing diagram shows the initialization sequencing of the device. 

## **Figure 8 • Cold Reset Timing** 

Notes: 

- The previous diagram shows the case where VDDI/VDDAUX of I/O banks are powered either before or sufficiently soon after VDD/VDD18/VDD25 that the I/O bank enable time is measured from the assertion time of VDD/VDD18/VDD25 (that is, the PUFT specification). If VDDI/VDDAUX of I/O banks are powered sufficiently after VDD/VDD18/VDD25, then the I/O bank enable time is measured from the assertion of VDDI/VDDAUX and is not specified by the PUFT specification. In this case, I/O operation is indicated by the assertion of BANK_i_VDDI_STATUS, rather than being measured relative to FABRIC_POR_N negation. 

- AUTOCALIB_DONE assertion indicates the completion of calibration for any I/O banks specified by the user for auto-calibration. AUTOCALIB_DONE asserts independently of DEVICE_INIT_DONE. It may assert before or after DEVICE_INIT_DONE and is determined by the following: 

   - How long after VDD/VDD18/VDD25 that VDDI/VDDAUX are powered on. Note that if any of the user-specified I/O banks are not powered on within the auto-calibration timeout window, then AUTOCALIB_DONE doesn't assert until after this timeout. 

   - The specified ramp times of VDDI of each I/O bank designated for auto-calibration. 

   - How much auto-initialization is to be performed for the PCIe, SERDES transceivers, and fabric LSRAMs. 

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- If any of the I/O banks specified for auto-calibration do not have their VDDI/VDDAUX powered on within the auto-calibration timeout window, then it will be approximately auto-calibrated whenever VDDI/VDDAUX is subsequently powered on. To obtain an accurate calibration however, on such IO banks, it is necessary to initiate a re-calibration (using CALIB_START from fabric). 

- AVM_ACTIVE only asserts if avionics mode is being used. It is asserted when the later of DEVICE_INIT_DONE or AUTOCALIB_DONE assert. 

## **7.9.2 Warm Reset Initialization Sequence** 

The following warm reset timing diagram shows the initialization sequencing of the device when either DEVRST_N or TAMPER_RESET_DEVICE signals are asserted. 

## **Figure 9 • Warm Reset Timing** 

## **7.9.3 Power-On Reset Voltages** 

The following sections describe the power-on reset voltages. 

## **7.9.3.1 Main Supplies** 

The start of power-up to functional time (TPUFT) is defined as the point at which the latest of the main supplies (VDD, VDD18, VDD25) reach the reference voltage levels specified in the following table. This starts the process of releasing the reset of the device and powering on the FPGA fabric and IOs. 

## **Table 111 • POR Ref Voltages** 

|**Supply**|**Power-On Reset Start Point (V)**|**Note**|
|---|---|---|
|VDD|0.95|Applies to both 1.0 V and 1.05 V opera-<br>tion.|
|VDD18|1.71||
|VDD25|2.25||



## **7.9.3.2 I/O-Related Supplies** 

For the I/Os to become functional (for low speed, sub-400 MHz operation), the (per-bank) I/O supplies (VDDI, VDDAUX) must reach the trip point voltage levels specified in the following table and the main supplies above must also be powered on. 

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## **Table 112 • I/O-Related Supplies** 

**==> picture [310 x 52] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||
|---|---|
|Supply|I/O Power-Up Start Point (V)|
|VDDI|0.85|
|VDDAUX|1.6|

**----- End of picture text -----**<br>


There are no sequencing requirements for the power supplies. However, VDDI3 and must be valid at same time as the main supplies. The other I/O supplies (VDDI, VDDAUX) have no effect on power-up of FPGA fabric (that is, the fabric still powers up even if the I/O supplies of some I/O banks remain powered off). 

## **7.9.4 User Design Dependence of Power-Up Times** 

Some phases of the device initialization are user design dependent, as the device automatically initializes certain resources to user-specified configurations if those resources are used in the design. It is necessary to compute the overall power-up to functional time by referencing the following tables and adding the relevant phases, according to the design configuration. The following equation refers to timing parameters specified in the above timing diagrams. Please note TPCIE , TXCVR, TLSRAM, and TUSRAM can be found in the PolarFire FPGA device power-up and resets user guide UG0725. 

TPUFT = TFAB_READY(cold) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB) 

TWRFT = TFAB_READY(warm) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB) 

Note: TPCIE, TXCVR, TLSRAM, TUSRAM, and TCALIB are common to both cold and warm reset scenarios. 

Auto-initialization of FPGA (if required) occurs in parallel with I/O calibration. The device may be considered fully functional only when the later of these two activities has finished, which may be either one, depending on the configuration, as may be calculated from the following tables. Note that I/O calibration may extend beyond TPUFT (as I/O calibration process is independent of main device power-on and is instead dependent on I/O bank supply relative power-on time and ramp times). The previous timing diagram for power-on initialization shows the earliest that I/Os could be enabled, if the I/O power supplies are powered on before or at the same time as the main supplies. 

## **7.9.5 Cold Reset to Fabric and I/Os (Low Speed) Functional** 

The following table specifies the minimum, typical, and maximum times from the power supplies reaching the above trip point levels until the FPGA fabric is operational and the FPGA IOs are functional for low-speed (sub-400 MHz) operation. 

## **Table 113 • Cold Boot** 

**==> picture [358 x 159] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Power-On (Cold) Reset|Min|Typ|Max|Unit|
|to Fabric and I/O Oper-|
|ational|
|Time when input pins|0.92|4.38|7.84|ms|
|start working – TIN_ACTIV-|
|E(cold)|
|Time when weak pull-|0.92|4.38|7.84|ms|
|ups are enabled – TPU_|
|PD_ACTIVE(cold)|
|Time when fabric is op-|0.95|4.41|7.87|ms|
|erational – TFAB_READY-|
|(cold)|

**----- End of picture text -----**<br>


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|**Power-On (Cold) Reset**<br>**to Fabric and I/O Oper-**<br>**ational**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|Time when output pins<br>start driving – TOUT_ACTI-<br>VE(cold)|0.97|4.43|7.89|ms|



## **7.9.6 Warm Reset to Fabric and I/Os (Low Speed) Functional** 

The following table specifies the minimum, typical, and maximum times from the negation of the warm reset event until the FPGA fabric is operational and the FPGA IOs are functional for low-speed (sub-400 MHz) operation. 

## **Table 114 • Warm Boot** 

|**Warm Reset to Fabric**<br>**and I/O Operational**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|
|Time when input pins<br>start working – TIN_ACTIV-<br>E(warm)|0.65|1.63|2.62|ms|
|Time when weak pull-<br>ups/pull-downs are en-<br>abled – TPU_PD_ACTIVE-<br>(warm)|0.65|1.63|2.62|ms|
|Time when fabric is op-<br>erational – TFAB_READY-<br>(warm)|0.68|1.66|2.65|ms|
|Time when output pins<br>start driving – TOUT_ACTI-<br>VE(warm)|0.70|1.68|2.67|ms|



## **7.9.7 Miscellaneous Initialization Parameters** 

In the following table, TFAB_READY refers to either TFAB_READY(cold) or TFAB_READY(warm) as specified in the previous tables, depending on whether the initialization is occurring as a result of a cold or warm reset, respectively. 

## **Table 115 • Cold and Warm Boot** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|The time from<br>TFAB_READYto<br>ready to pro-<br>gramthroughJT-<br>AG/SPI-Slave||0|0|0|ms||
|The time from<br>TFAB_READYto au-<br>to-update start|||TPUF_OVHD<br>1|TPUF_OVHD<br>1|ms||
|The time from<br>TFAB_READYto<br>programming<br>recovery start|||TPUF_OVHD<br>1|TPUF_OVHD<br>1|ms||



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|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|The time from<br>TFAB_READYto the<br>tamper flags be-<br>ing available|TTAMPER_READY|0|0|0|ms||
|The time from<br>TFAB_READYto the<br>Athena Crypto<br>co-processor<br>being available<br>(for S devices<br>only)|TCRYPTO_READY|0|0|0|ms||



**1.** Programming depends on the PUF to power up. Refer to TPUF_OVHD at section Secure NVM Performance. 

## **7.9.8 I/O Calibration** 

The following tables specify the initial I/O calibration time for the fastest and slowest supported VDDI ramp times of 0.2 ms to 50 ms, respectively. This only applies to I/O banks specified by the user to be auto-calibrated. 

**Table 116 • I/O Initial Calibration Time (TCALIB)** 

|Ramp Time|Min (ms)|Max (ms)|Condition|
|---|---|---|---|
|0.2 ms|0.98|2.63|Applies to HSIO and GPIO<br>banks|
|50 ms|41.62|62.19|Applies to HSIO and GPIO<br>banks|



Notes: 

- The user may specify any VDDI ramp time in the range specified above. The nominal initial calibration time is given by the specified VDDI ramp time plus 2 ms. 

- In order for IO calibration to start, VDDI and VDDAUX of the I/O bank must be higher than the trip point levels specified in I/O-Related Supplies. 

**Table 117 • I/O Fast Recalibration Time (TRECALIB)** 

|I/O Type|Min (ms)|Typ (ms)|Max (ms)|Condition|
|---|---|---|---|---|
|GPIO bank|0.04|0.14|0.24|GPIO configured for 3.3<br>V operation|
|HSIO bank|0.11|0.20|0.30|HSIO configured for 1.8<br>V operation|



Note: In order to obtain fast re-calibration, the user must assert the relevant clock request signal from the FPGA fabric to the I/O bank controller. 

## **7.10 Dedicated Pins** 

The following section describes the dedicated pins. 

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## **7.10.1 JTAG Switching Characteristics** 

The following table describes characteristics of JTAG switching. 

## **Table 118 • JTAG Electrical Characteristics** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|TDISU|TDI input setup<br>time|0.0|||ns||
|TDIHD|TDI input hold<br>time|2.0|||ns||
|TTMSSU|TMS input setup<br>time|1.5|||ns||
|TTMSHD|TMS input hold<br>time|1.5|||ns||
|FTCK|TCK frequency|||25|MHz||
|TTCKDC|TCK duty cycle|40||60|%||
|TTDOCQ|TDO clock to Q<br>out|||8.4|ns|CLOAD= 40 pf|
|TRSTBCQ|TRSTB clock to<br>Q out|||23.5|ns|CLOAD= 40 pf|
|TRSTBPW|TRSTB min pulse<br>width|50|||ns||
|TRSTBREM|TRSTB removal<br>time|0.0|||ns||
|TRSTBREC|TRSTB recovery<br>time|12.0|||ns||
|CINTDI|TDI input pin ca-<br>pacitance|||5.3|pf||
|CINTMS|TMS input pin<br>capacitance|||5.3|pf||
|CINTCK|TCK input pin<br>capacitance|||5.3|pf||
|CINTRSTB|TRSTB input pin<br>capacitance|||5.3|pf||



## **7.10.2 SPI Switching Characteristics** 

The following tables describe characteristics of SPI switching. 

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**Table 119 • SPI Master Mode (PolarFire Master)** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|SCK frequency|sp1|||20<br>40|MHz<br>Mhz|DuringProgram-<br>ming<br>During Initializa-<br>tion|
|SCK minimum<br>pulse width high|sp2|SCK_period/2|||ns||
|SCK minimum<br>pulse width low|sp3|SCK_period/2|||ns||
|Rise and fall<br>time|sp4<br>sp5||||ns|Refer to PolarF-<br>ire IBIS models3|
|SDO setup time|sp6m|(SCK_period/2)<br>– 3.0|||ns||
|SDO hold time|sp7m|(SCK_period/2)<br>– 2.0|||ns||
|SDI setup time|sp8m|10.0|||ns||
|SDI hold time|sp9m|–1.0|||ns||



Notes: 

**1.** Parameters are referenced to the active edge of SCK, which depends on the configured SPI protocol (for example, Motorola SPI mode uses rising edge as active edge if SPO= 0). 

**2.** SDI is clocked into SPI on active edge and clocked out on inactive edge. Therefore, SDO delay parameters are dependent on SCK frequency (nominally SCK_period/2). 

**3.** For specific rise/fall times, board design considerations, and detailed output buffer resistances, use the corresponding IBIS models located online at Microsemi SoC Products Group. 

**Table 120 • SPI Slave Mode (PolarFire Slave)** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|SCK frequency|sp1|||80|MHz||
|SCK minimum<br>pulse width high|sp2|SCK_period/2|||ns||
|SCK minimum<br>pulse width low|sp3|SCK_period/2|||ns||
|Rise and fall<br>time|sp4<br>sp5||||ns|Refer to PolarF-<br>ire IBIS models3|
|SDO setup time|sp6s|(SCK_period/2)<br>– 8.0|||ns||
|SDO hold time|sp7s|SCK_period/2|||ns||
|SDI setup time|sp8s|4.0|||ns||



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|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|SDI hold time|sp9s|2.0|||ns||



Notes: 

**1.** Parameters are referenced to the active edge of SCK, which depends on the configured SPI protocol (for example, Motorola SPI mode uses rising edge as active edge if SPO= 0). 

**2.** SDI is clocked into SPI on active edge and clocked out on inactive edge. Therefore, SDO delay parameters are dependent on SCK frequency (nominally SCK_period/2). 

**3.** For specific rise/fall times, board design considerations, and detailed output buffer resistances, use the corresponding IBIS models located online at Microsemi SoC Products Group. 

## **Figure 10 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)** 

## **7.10.3 SmartDebug Probe Switching Characteristics** 

The following table describes characteristics of SmartDebug probe switching. 

## **Table 121 • SmartDebug Probe Performance Characteristics** 

|**Parameter**|**Symbol**|**VDD = 1.0 V STD**|**VDD = 1.0 V – 1**|**VDD = 1.05 V ST-**<br>**D**|**VDD = 1.05 V – 1**|**Unit**|
|---|---|---|---|---|---|---|
|Maximum fre-<br>quency of probe<br>signal|FMAX|100|100|100|100|MHz|
|Minimum delay<br>of probe signal|TMin_delay|||||ns|
|Maximum delay<br>of probe signal|TMax_delay|||||ns|



## **7.10.4 DEVRST_N Switching Characteristics** 

The following table describes characteristics of DEVRST_N switching. 

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**Table 122 • DEVRST_N Electrical Characteristics** 

|**Parameter**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|
|DEVRST_Nramp<br>time|DRRAMP||10||μs|It must be a nor-<br>mal clean digital<br>signal, with typi-<br>cal rise and fall<br>times|
|DEVRST_N as-<br>sert time|DRASSERT|1|||μs|The minimum<br>timeforDEVRST-<br>_N assertion to<br>be recognized|
|DEVRST_N de-<br>assert time|DRDEASSERT|2.75|||ms|The minimum<br>time DEVRST_N<br>needs to be de-<br>asserted before<br>assertion|



## **7.11 User Crypto** 

The following section describes user crypto. 

## **7.11.1 TeraFire 5200B Switching Characteristics** 

The following table describes TeraFire 5200B switching characteristics. 

## **Table 123 • TeraFire F5200B Switching Characteristics** 

|**Parameter**|**Symbol**|**VDD = 1.0 V**<br>**STD**|**VDD = 1.0 V –**<br>**1**|**VDD = 1.05 V**<br>**STD**|**VDD = 1.05 V**<br>**– 1**|**Unit**|**Condition**|
|---|---|---|---|---|---|---|---|
|FMAXwith DLL|FMAX_DLL|189|189|189|189|MHz|–40 °C to 100<br>°C|
|FMINwith DLL|FMIN_DLL|125|125|125|125|MHz|–40 °C to 100<br>°C|
|FMAXwith DLL<br>in bypass<br>mode|FMAX_DLL_BYPA-<br>SS|70|70|70|70|MHz|–40 °C to 100<br>°C|
|FMINwith DLL<br>in bypass<br>mode|FMIN_DLL_BYPAS-<br>S|0|0|0|0|MHz|–40 °C to 100<br>°C|



## **7.11.2 TeraFire 5200B Throughput Characteristics** 

The following tables for each algorithm describe the TeraFire 5200B throughput characteristics. 

Note: Throughput cycle count collected with Athena TeraFire Core and RISCV running at 70 MHz. 

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**Table 124 • AES** 

|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay in CPU Clock-Cycles**|
|---|---|---|---|
|AES-ECB-128 encrypt1|128|511|1011|
||64K|48109|927|
|AES-ECB-128 decrypt1|128|557|1328|
||64K|48385|1282|
|AES-ECB-256 encrypt1|128|527|1333|
||64K|56301|1303|
|AES-ECB-256 decrypt1|128|589|1356|
||64K|56673|1410|
|AES-CBC-256 encrypt1|128|588|1316|
||64K|58691|1286|
|AES-CBC-256 decrypt1|128|617|1676|
||64K|56853|1730|
|AES-GCM-128 encrypt1, 128-<br>bit tag, (full message encrypt-<br>ed/authenticated)|128|1921|1701|
||64K|58022|1640|
|AES-GCM-256 encrypt1, 128-<br>bit tag, (full message encrypt-<br>ed/authenticated)|128|1969|1718|
||64K|58054|1803|



## **1.** With DPA counter measures. 

## **Table 125 • GMAC** 

## **1.** With DPA counter measures. 

## **Table 126 • HMAC** 

|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay In CPU Clock-Cycles**|
|---|---|---|---|
|HMAC-SHA-2561, 256-bit key|512|7461|1616|
||64K|86319|1350|



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|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay In CPU Clock-Cycles**|
|---|---|---|---|
|HMAC-SHA-3841, 384-bit key|1024|13017|1438|
||64K|104055|1438|



## **1.** With DPA counter measures. 

## **Table 127 • CMAC** 

|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay In CPU Clock-Cycles**|
|---|---|---|---|
|AES-CMAC-2561 (message is<br>only authenticated)|128|446|8434|
||64K|45494|110209|



## **1.** With DPA counter measures. 

## **Table 128 • KEY TREE** 

|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay In CPU Clock-Cycles**|
|---|---|---|---|
|SHA-11|512|2370|816|
||64K|75528|709|
|SHA-2561|512|2500|656|
||64K|82704|656|
|SHA-3841|1024|4122|712|
||64K|98174|656|
|SHA-5121|1024|4122|652|
||64K|98174|653|



## **Table 129 • SHA** 

## **1.** With DPA counter measures. 

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**Table 130 • ECC** 

|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay In CPU Clock-Cycles**|
|---|---|---|---|
|ECDSA SigGen, P-384/SHA-38<br>41|1024|12525647|5072|
||8K|12540387|5072|
|ECDSA SigGen, P-384/SHA-384|1024|5502896|5071|
||8K|5513718|5071|
|ECDSA SigVer, P-384/SHA-3841|1024|6243821|4683|
||8K|6321110|4422|
|ECDSA SigVer, P-384/SHA-384|1024|6243821|4422|
||8K|6321110|4422|
|Key Agreement (KAS), P-384||5039125|10318|
|Point Multiply, P-2561||5177474|4434|
|Point Multiply, P-3841||12055519|5086|
|Point Multiply, P-5211||26889271|6470|
|Point Addition, P-384||3018067|5303|
|KeyGen (PKG), P-384||12052230|7909|
|Point Verification, P-384||5091|3354|



## **1.** With DPA counter measures. 

## **Table 131 • IFC (RSA)** 

|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay In CPU Clock-Cycles**|
|---|---|---|---|
|Encrypt, RSA-2048, e=65537|2048|436972|8287|
|Encrypt, RSA-3072, e=65537|3072|962162|12063|
|Decrypt, RSA-20481, CRT|2048|26847616|15261|
|Decrypt, RSA-30721, CRT|3072|75168689|22488|
|Decrypt, RSA-4096, CRT|4096|88789629|23585|
|Decrypt, RSA-3072, CRT|3072|38202717|18838|
|SigGen, RSA-3072/SHA-3841 ,<br>CRT, PKCS #1 V 1 1.5|1024|75156973|19562|
||8K|75222026|18880|



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|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay In CPU Clock-Cycles**|
|---|---|---|---|
|SigGen, RSA-3072/SHA-384, P-<br>KCS #1, V 1.5|1024|148092303|13622|
||8K|148102319|13622|
|SigVer, RSA-3072/SHA-384, e<br>= 65537, PKCS #1 V 1.5|1024|970959|11769|
||8K|981755|11769|
|SigVer, RSA-2048/SHA-256, e<br>= 65537, PKCS #1 V 1.5|1024|443593|8490|
||8K|452751|8443|
|SigGen, RSA-3072/SHA-384, A-<br>NSI X9.31|1024|147143879|13624|
||8K|147153109|13417|
|SigVer, RSA-3072/SHA-384, e<br>= 65537, ANSI X9.31|1024|972788|11268|
||8K|983643|11215|



## **1.** With DPA counter measures. 

## **Table 132 • FFC (DH)** 

|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay In CPU Clock-Cycles**|
|---|---|---|---|
|SigGen, DSA-3072/SHA-3841|1024|27932434|13271|
||8K|27946636|13166|
|SigGen, DSA-3072/SHA-384|1024|12086324|13028|
||8K|12097138|12862|
|SigVer, DSA-3072/SHA-384|1024|24711796|14689|
||8K|24418930|14689|
|SigVer, DSA-2048/SHA-256|1024|9673222|10717|
||8K|9803028|10717|
|Key Agreement (KAS), DH-307<br>2 (p=3072,security=256)||4920705|9519|
|Key Agreement (KAS), DH-307<br>2 (p=3072,security=256)1||78871914|9495|



**1.** With DPA counter measures. 

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## **Table 133 • NRBG** 

|**Modes**|**Message Size (Bits)**|**Athena TeraFire Crypto Core**<br>**Clock-Cycles**|**CAL Delay In CPU Clock-Cycles**|
|---|---|---|---|
|Instantiate: strength, s=256, 3<br>84-bit nonce, 384-bit personal-<br>ization string||18221|3076|
|Reseed: no additional input,<br>s=256||13585|1056|
|Reseed: 384-bit additional in-<br>put, s=256||15922|995|
|Generate: (no additional in-<br>put), prediction resistance en-<br>abled, s=256|128|15262|1672|
||8K|27169|7837|
|Generate: (no additional in-<br>put), prediction resistance dis-<br>abled, s=256|128|2138|781|
||8K|14045|7837|
|Generate: (384-bit additional<br>input), prediction resistance<br>enabled, s=256|128|21299|1620|
||8K|33206|8563|
|Generate: (384-bit additional<br>input), prediction resistance<br>disabled, s=256|128|11657|1507|
||8K|23564|8563|
|Un-instantiate||761|502|



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