MMA1210KEG

N ~~eerrr~~ errr (ele, **Freescale Semiconductor** Document Number: MMA1210 Data Sheet: Technical Data Rev 6, 09/2011 

## **Surface Mount Micromachined Accelerometer** 

## **MMA1210** 

The MMA series of silicon capacitive, micromachined accelerometers feature signal conditioning, a 4-pole low pass filter and temperature compensation. Zero-g offset full scale span and filter cutoff are factory set and require no external devices. A full system self-test capability verifies system functionality. 

## **Features** 

- Integral Signal Conditioning 

- Linear Output 

- Ratiometric Performance 

- 4th Order Bessel Filter Preserves Pulse Shape Integrity 

- Calibrated Self-test 

- Low Voltage Detect, Clock Monitor, and EPROM Parity Check Status 

- Transducer Hermetically Sealed at Wafer Level for Superior Reliability 

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16-LEAD SOIC<br>Pb-FREE<br>CASE 475-01<br>**----- End of picture text -----**<br>


- Robust Design, High Shocks Survivability 

- Qualified AECQ100, Rev. F Grade 2 (-40 ° C/+105 ° C) 

## **Typical Applications** 

- Vibration Monitoring and Recording 

- Impact Monitoring 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|**ORDERING INFORMATION**|
|---|---|---|---|
|**Device Name**|**Temperature Range**|**Case No.**|**Package**|
|MMA1210EG|–40°to 125°C|475-01|SOIC-16|
|MMA1210EGR2|–40°to 125°C|475-01|SOIC-16, Tape & Reel|
|MMA1210KEG|–40°to 125°C|475-01|SOIC-16|
|MMA1210KEGR2|–40°to 125°C|475-01|SOIC-16, Tape & Reel|



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Top View<br>N/C 1 16 N/C<br>N/C 2 15 N/C<br>N/C 3 14 N/C<br>ST 4 13 N/C<br>VOUT 5 12 N/C<br>STATUS 6 11 N/C<br>VSS 7 10 N/C<br>VDD 8 9 N/C<br>Pin Connections<br>**----- End of picture text -----**<br>


”K” suffix indicates device manufactured with an alternate silicon sourcing. 

© Freescale Semiconductor, Inc., 2011. All rights reserved. ~~ee~~ 

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VDD<br>G-Cell Temp<br>Sensor Integrator Gain Filter Comp VOUT<br>ST<br>Self-test Control Logic & Oscillator Clock<br>EPROM Trim Circuits Generator VSS<br>STATUS<br>**----- End of picture text -----**<br>


**Figure 1 Simplified Accelerometer Functional Block Diagram** 

## **Table 1. Maximum Ratings** 

(Maximum ratings are the limits to which the device can be exposed without causing permanent damage.) 

|**Rating**<br>**Symbol**<br>**Value**<br>**Unit**<br>Powered Acceleration (all axes)<br>Gpd<br>1500<br>g<br>Unpowered Acceleration (all axes)<br>Gupd<br>2000<br>g<br>Supply Voltage<br>VDD<br>–0.3 to +7.0<br>V<br>Drop Test(1)<br>Ddrop<br>1.2<br>m<br>Storage Temperature Range<br>Tstg<br>–40 to +125<br>°C<br>~~==~~|**Rating**<br>**Symbol**<br>**Value**<br>**Unit**<br>Powered Acceleration (all axes)<br>Gpd<br>1500<br>g<br>Unpowered Acceleration (all axes)<br>Gupd<br>2000<br>g<br>Supply Voltage<br>VDD<br>–0.3 to +7.0<br>V<br>Drop Test(1)<br>Ddrop<br>1.2<br>m<br>Storage Temperature Range<br>Tstg<br>–40 to +125<br>°C<br>~~==~~|**Rating**<br>**Symbol**<br>**Value**<br>**Unit**<br>Powered Acceleration (all axes)<br>Gpd<br>1500<br>g<br>Unpowered Acceleration (all axes)<br>Gupd<br>2000<br>g<br>Supply Voltage<br>VDD<br>–0.3 to +7.0<br>V<br>Drop Test(1)<br>Ddrop<br>1.2<br>m<br>Storage Temperature Range<br>Tstg<br>–40 to +125<br>°C<br>~~==~~|**Rating**<br>**Symbol**<br>**Value**<br>**Unit**<br>Powered Acceleration (all axes)<br>Gpd<br>1500<br>g<br>Unpowered Acceleration (all axes)<br>Gupd<br>2000<br>g<br>Supply Voltage<br>VDD<br>–0.3 to +7.0<br>V<br>Drop Test(1)<br>Ddrop<br>1.2<br>m<br>Storage Temperature Range<br>Tstg<br>–40 to +125<br>°C<br>~~==~~|
|---|---|---|---|
|1. Dropped onto concrete surface from any axis.||||
|**ELECTRO STATIC DISCHARGE (ESD)**||||
|**WARNING:**<br>**This device is sensitive to electrostatic**||||
|**discharge.**||||



Although the Freescale accelerometers contain internal 2 kV ESD protection circuitry, extra precaution must be taken by the user to protect the chip from ESD. A charge of over 2000 volts can accumulate on the human body or associated test equipment. A charge of this magnitude can alter the 

performance or cause failure of the chip. When handling the accelerometer, proper ESD precautions should be followed to avoid exposing the device to discharges which may be detrimental to its performance. 

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## **Table 2. Operating Characteristics** 

(Unless otherwise noted: –40°C ≤ TA ≤ +105°C, 4.75 ≤ VDD ≤ 5.25, Acceleration = 0g, Loaded output.[(1)] ) 

|(Unless otherwise noted: –40°C≤TAA≤+105°C, 4.75≤VDDDD|VDDDD ≤5.25, Acceleration = 0g, Loaded output.|5.25, Acceleration = 0g, Loaded output.|5.25, Acceleration = 0g, Loaded output.|5.25, Acceleration = 0g, Loaded output.[(1)])||
|---|---|---|---|---|---|
|**Characteristic**<br>~~Od~~|**Symbol**<br>~~Od~~|**Min**<br>~~Od~~|**Typ**<br>~~Od~~|**Max**<br>~~Od~~|**Unit**<br>~~Od~~|
|Operating Range(2)<br>Supply Voltage(3)<br>Supply Current<br>Operating Temperature Range<br>Acceleration Range<br>~~Od~~|VDD<br>IDD<br>TA<br>gFS<br>~~Od~~|4.75<br>3.0<br>–40<br>—<br>~~Od~~|5.00<br>—<br>—<br>112.5<br>~~Od~~|5.25<br>6.0<br>+125<br>—<br>~~Od~~|V<br>mA<br>C<br>g<br>~~Od~~|
|Output Signal<br>Zero g (TA= 25°C, VDD= 5.0 V)(4)<br>Zero g<br>Sensitivity (TA= 25°C, VDD= 5.0 V)(5)<br>Sensitivity<br>Bandwidth Response<br>Nonlinearity|VOFF<br>VOFF,V<br>S<br>SV<br>f–3dB<br>NLOUT|2.35<br>0.46 VDD<br>19<br>3.72<br>360<br>–1.0|2.5<br>0.50 VDD<br>20.0<br>4.0<br>400<br>—|2.65<br>0.54 VDD<br>21<br>4.28<br>440<br>1.0|V<br>V<br>mV/g<br>mV/g/V<br>Hz<br>% FSO|
|Noise<br>RMS (0.1–1 kHz)<br>Power Spectral Density<br>Clock Noise (without RC load on output)(6)<br>~~FEE~~|nRMS<br>nPSD<br>nCLK<br>~~FEE~~|—<br>—<br>—<br>~~FEE~~|—<br>110<br>2.0<br>~~FEE~~|2.8<br>—<br>—<br>~~FEE~~|mVrms<br>μV/(Hz1/2)<br>mVpk<br>~~FEE~~|
|Self-Test<br>Output Response(7)<br>Input Low<br>Input High<br>Input Loading(8)<br>Response Time(9)<br>~~FEE~~|gST<br>VIL<br>VIH<br>IIN<br>tST<br>~~FEE~~|55<br>VSS<br>0.7×VDD<br>–30<br>—<br>~~FEE~~|75<br>—<br>—<br>–100<br>2.0<br>~~FEE~~|93<br>0.3×VDD<br>VDD<br>–260<br>10<br>~~FEE~~|g<br>V<br>V<br>μA<br>ms<br>~~FEE~~|
|Status(10), (11)<br>Output Low (Iload= 100μA)<br>Output High (Iload= 100μA)<br>~~pd~~|VOL<br>VOH<br>~~pd~~|—<br>VDD– 0.8<br>~~pd~~|—<br>—<br>~~pd~~|0.4<br>—<br>~~pd~~|V<br>V<br>~~pd~~|
|Minimum Supply Voltage (LVD Trip)<br>~~pd~~|VLVD<br>~~pd~~|2.7<br>~~pd~~|3.25<br>~~pd~~|4.0<br>~~pd~~|V<br>~~pd~~|
|Clock Monitor Fail Detection Frequency<br>~~Od~~|fmin<br>~~Od~~|50<br>~~Od~~|—<br>~~Od~~|260<br>~~Od~~|kHz<br>~~Od~~|
|Output Stage Performance<br>Electrical Saturation Recovery Time(12)<br>Full Scale Output Range (IOUT= 200μA)<br>Capacitive Load Drive(13)<br>Output Impedance<br>~~Od~~|tDELAY<br>VFSO<br>CL<br>ZO<br>~~Od~~<br>~~ee~~|—<br>0.25<br>—<br>—<br>~~Od~~<br>~~ee~~|0.2<br>—<br>—<br>300<br>~~Od~~<br>~~eee~~|—<br>VDD–0.25<br>100<br>—<br>~~Od~~<br>~~eee~~|ms<br>V<br>pF<br>Ω<br>~~Od~~<br>~~eee~~|
|Mechanical Characteristics<br>Transverse Sensitivity(14)<br>Package Resonance<br>~~e~~|VXZ,YZ<br>fPKG<br>~~e~~~~**e**~~<br>~~ee~~|—<br>—<br>~~**e**~~<br>~~ee~~|—<br>10<br>~~**e**~~<br>~~eee~~|5.0<br>—<br>~~**e**~~<br>~~eee~~|% FSO<br>kHz<br>~~**e**~~<br>~~eee~~|



1. For a loaded output the measurements are observed after an RC filter consisting of a 1 k Ω resistor and a 0.01 μ F capacitor to ground. 

2. These limits define the range of operation for which the part will meet specification. 

3. Within the supply range of 4.75 and 5.25 volts, the device operates as a fully calibrated linear accelerometer. Beyond these supply limits the device may operate as a linear device but is not guaranteed to be in calibration. 

4. The device can measure both + and – acceleration. With no input acceleration the output is at midsupply. For positive acceleration the output will increase above VDD/2 and for negative acceleration the output will decrease below VDD/2. 

5. The device is calibrated at 35g. 

6. At clock frequency ≅ 70 kHz. 

7. Δ VOFF calculated with typical sensitivity. 

8. The digital input pin has an internal pull-down current source to prevent inadvertent self test initiation due to external board level leakages. 

9. Time for the output to reach 90% of its final value after a self-test is initiated. 

10. The Status pin output is not valid following power-up until at least one rising edge has been applied to the self-test pin. The Status pin is high whenever the self-test input is high, as a means to check the connectivity of the self-test and Status pins in the application. 

11. The Status pin output latches high if a Low Voltage Detection or Clock Frequency failure occurs, or the EPROM parity changes to odd. The Status pin can be reset low if the self-test pin is pulsed with a high input for at least 100 μ s, unless a fault condition continues to exist. 

12. Time for amplifiers to recover after an acceleration signal causes them to saturate. 

13. Preserves phase margin (60°) to guarantee output amplifier stability. 

14. A measure of the device's ability to reject an acceleration applied 90° from the true axis of sensitivity. 

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## **PRINCIPLE OF OPERATION** 

The Freescale accelerometer is a surface-micromachined integrated-circuit accelerometer. 

The device consists of a surface micromachined capacitive sensing cell (g-cell) and a CMOS signal conditioning ASIC contained in a single integrated circuit package. The sensing element is sealed hermetically at the wafer level using a bulk micromachined “cap'' wafer. 

The g-cell is a mechanical structure formed from semiconductor materials (polysilicon) using semiconductor processes (masking and etching). It can be modeled as two stationary plates with a moveable plate in-between. The center plate can be deflected from its rest position by subjecting the system to an acceleration (Figure 3). 

When the center plate deflects, the distance from it to one fixed plate will increase by the same amount that the distance to the other plate decreases. The change in distance is a measure of acceleration. 

The g-cell plates form two back-to-back capacitors (Figure 4). As the center plate moves with acceleration, the distance between the plates changes and each capacitor's value will change, (C = A ε /D). Where A is the area of the plate, ε is the dielectric constant, and D is the distance between the plates. 

The CMOS ASIC uses switched capacitor techniques to measure the g-cell capacitors and extract the acceleration data from the difference between the two capacitors. The ASIC also signal conditions and filters (switched capacitor) the signal, providing a high level output voltage that is ratiometric and proportional to acceleration. 

## **SPECIAL FEATURES** 

## **Filtering** 

The Freescale accelerometers contain an onboard 4-pole switched capacitor filter. A Bessel implementation is used because it provides a maximally flat delay response (linear phase) thus preserving pulse shape integrity. Because the filter is realized using switched capacitor techniques, there is no requirement for external passive components (resistors and capacitors) to set the cutoff frequency. 

## **Self-Test** 

The sensor provides a self-test feature that allows the verification of the mechanical and electrical integrity of the accelerometer at any time before or after installation. This feature is critical in applications such as automotive airbag systems where system integrity must be ensured over the life of the vehicle. A fourth “plate'' is used in the g-cell as a selftest plate. When the user applies a logic high input to the selftest pin, a calibrated potential is applied across the self-test plate and the moveable plate. The resulting electrostatic 

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The resultant deflection is measured by the accelerometer's control ASIC and a proportional output voltage results. This procedure assures that both the mechanical (g-cell) and electronic sections of the accelerometer are functioning. 

## **Status** 

~~t==>~~ **Acceleration** ~~=~~ **Figure 3. Transducer Figure 4. Equivalent Physical Model Circuit Model** 

Freescale accelerometers include fault detection circuitry and a fault latch. The Status pin is an output from the fault latch, OR'd with self-test, and is set high whenever the following event occurs: 

- Parity of the EPROM bits becomes odd in number. 

The fault latch can be reset by a rising edge on the self-test input pin, unless one (or more) of the fault conditions continues to exist. 

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**BASIC CONNECTIONS Pinout Description PCB Layout** N/C 1 16 N/C STATUS P1 N/C 2 15 N/C N/C 3 14 N/C ST P0 ST 4 13 N/C VSS VOUT 5 12 N/C VOUT ~~R~~ A/D In C 0.1 μ F STATUSVVDDSS 678 11109 N/CN/CN/C VVDDSS C 0.1 1 k Ωμ F C 0.01 μ F VDD “ ~~A eo~~ VRH C 0.1 μ F **Table 3. Pin Descriptions Pin No. Pin Name Description** Power Supply 1 thru 3 — Leave unconnected. **Figure 6. Recommended PCB Layout for Interfacing** 4 ST Logic input pin used to initiate **Accelerometer to Microcontroller** self-test. 5 VOUT Output voltage of the **NOTES:** accelerometer. 1. Use a 0.1 μ F capacitor on VDD to decouple the power 6 STATUS Logic output pin to indicate fault. source. 7 VSS The power supply ground. 2. Physical coupling distance of the accelerometer to the microcontroller should be minimal. 8 VDD The power supply input. 3. Place a ground plane beneath the accelerometer to 9 thru 13 Trim pins Used for factory trim. Leave reduce noise, the ground plane should be attached to unconnected. all of the open ended terminals shown in Figure 6. 14 thru 16 — No internal connection. Leave 4. Use an RC filter of 1 k Ω and 0.01 μ F on the output of the accelerometer to minimize clock noise (from the unconnected. ~~. RO~~ switched capacitor filter circuit). 5. PCB layout of power and ground should not couple power supply noise. 6. Accelerometer and microcontroller should not be a VDD MMA1210 6 STATUS high current path. Logic 4 ST R1 Input 8 VDD VOUT 5 1 k Ω OutputSignal 7. switching frequency should be selected such that they do not interfere with the internal accelerometer A/D sampling rate and any external power supply do not interfere with the internal accelerometer A/D sampling rate and any external power supply A/D sampling rate and any external power supply C1 0.1 μ F C2 sampling frequency. This will prevent aliasing errors. 7 VSS 0.01 μ F ~~MeLFF~~ **Figure 5. SOIC Accelerometer with Recommended Connection Diagram** 

7. switching frequency should be selected such that they do not interfere with the internal accelerometer A/D sampling rate and any external power supply do not interfere with the internal accelerometer A/D sampling rate and any external power supply A/D sampling rate and any external power supply sampling frequency. This will prevent aliasing errors. 

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Dynamic Acceleration Sensing Direction<br>+ Z<br>Acceleration of the package in the<br>+ Z direction (center plate moves in<br>the  − Z direction) will result in an<br>O increase in the output.<br>Kh<br>Activation of Self test moves the<br>−<br>center plate in the  Z direction,<br>v<br>resulting in an increase in the output.<br>− Z<br>Side View<br>Static Acceleration Sensing Direction<br>Direction of Earth's gravity field [(1)]<br>w<br>Kh<br>Side View<br>1. When positioned as shown, the Earth's gravity will result in a positive 1g output.<br>**----- End of picture text -----**<br>


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## **MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS** 

Surface mount board layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct 

footprint, the packages will self-align when subjected to a solder reflow process. It is always recommended to design boards with a solder mask layer to avoid bridging and shorting between solder pads. 

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0.050 in.<br>0.380 in. 1.27 mm<br>9.65 mm<br>a<br>= =<br>CO -]—<br>= rt<br>C TC<br>0.024 in.<br>0.610 mm<br>= 5<br>Co ae<br>AL Br<br>0.080 in.<br>2.03 mm<br>**----- End of picture text -----**<br>


**Figure 7. Footprint SOIC-16 (Case 475-01)** 

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## **PACKAGE DIMENSIONS** 

PAGE 1 OF 2 

**CASE 475-01 ISSUE C 16 LEAD SOIC** 

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## **PACKAGE DIMENSIONS** 

PAGE 2 OF 2 

**CASE 475-01 ISSUE C 16 LEAD SOIC** 

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MMA1210 Rev. 6 09/2011