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MCP23S18-E/SP
I/O Expander, 16bit, 10 MHz, SPI, 1.8 V, 5.5 V, DIP
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: MICROCHIP
- Product type: I/O Expanders
- No. of Pins: 28Pins
- No. of I/O's: 16I/O's
- Bus Frequency: 10MHz
- IC Interface Type: SPI
- Chip Configuration: 16bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 1.8V
- Interface Case Style: DIP
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 1.6 € |
| Current stock | 200+ |
| Lead time | 7 days |
Datasheet
## **MCP23018/MCP23S18**
## **16-Bit I/O Expander with Open-Drain Outputs**
## **Features**
- 16-bit remote bidirectional I/O port:
- I/O pins default to input
- Open-drain outputs:
- 5.5V tolerant
- 25 mA sink capable (per pin)
- 400 mA total
- High-speed I[2] C™ interface: ( **MCP23018** )
- 100 kHz
- 400 kHz
- Configurable interrupt source:
- Interrupt-on-change from configured defaults or pin change
- Polarity inversion register to configure the polarity of the input port data
- External reset input
- Low standby current:
- 1 µA (-40°C ≤ TA ≤ +85°C)
- 6 µA (+85°C ≤ TA ≤ +125°C)
- Operating voltage:
- 1.8V to 5.5V
- 3.4 MHz
- High-speed SPI interface: ( **MCP23S18** )
- 10 MHz: 2.7V ≤ VDD ≤ 5.5V
- Single hardware address pin: ( **MCP23018** )
- Voltage input to allow up to eight devices on the bus
- Configurable interrupt output pins:
## **Packages**
28-pin PDIP (300 mil)
28-pin SOIC (300 mil)
24-pin SSOP (MCP23018 only)
24-pin QFN (4x4 [mm])
- Configurable as active-high, active-low or open-drain
## **Block Diagram**
**==> picture [371 x 279] intentionally omitted <==**
**----- Start of picture text -----**<br>
MCP23S18<br>CS<br>SCK<br>SI<br>SPI<br>SO<br>MCP23018 Open-drain<br>GPB7<br>SCL Serializer/<br>I [2] C GPB6<br>SDA Deserializer<br>GPB5<br>GPIO GPB4<br>GPB3<br>ADDR Multi-bit GPB2<br>Decode<br>Control GPB1<br>RESET 16 GPB0<br>INTA Interrupt GPA7<br>INTB Logic GPA6<br>8 GPA5<br>GPA4<br>GPIO<br>GPA3<br>Configuration/ GPA2<br>Control GPA1<br>Registers GPA0<br>**----- End of picture text -----**<br>
DS22103A-page 1
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **Package Types:**
|VSS<br>NC<br>GPB0<br>GPB1<br>GPB2<br>GPB3<br>GPB4<br>GPB5<br>GPB6<br>GPB7<br>VDD<br>SCL<br>SDA<br>NC||**PDIP/SOIC**<br><br>|**PDIP/SOIC**<br><br>|**MCP23018**<br>NC<br>GPA7<br><br>VSS<br>GPB0<br>|**MCP23018**<br>NC<br>GPA7<br><br>VSS<br>GPB0<br>|**SSOP**<br><br>|**SSOP**<br><br>|GPA7<br>GPA6<br>GPA5<br>GPA4<br>GPA3<br>GPA2<br>GPA1<br>GPA0<br>INTA<br>INTB|
|---|---|---|---|---|---|---|---|---|
||||||||||
|||28<br>1||||24<br>1|||
||||||||||
|||27<br>2||||23<br>2|||
||||||||||
|||26<br>3||GPA6<br>GPB1||22<br>3|||
|||||GPA5<br>GPA4<br>GPA3<br>GPA2<br>GPA1<br>GPA0<br><br>GPB2<br>GPB3<br>GPB4<br>GPB5<br>GPB6<br>GPB7<br>|||||
|||25<br>4||||21<br>4|||
||||||||||
|||24<br>5||||20<br>5|||
||||||||||
|||23<br>6||||19<br>6|||
||||||||||
|||22<br>7||||18<br>7|||
||||||||||
|||21<br>8||||17<br>8|||
||||||||||
|||20<br>9||||16<br>9|||
||||||||||
|||19<br>10||INTA<br>VDD||15<br>10|||
|||18<br>11||INTB<br>NC<br>R<br>ESET<br>ADDR<br>SCL<br>SDA||14<br>11||R<br>ESET<br>ADDR|
||||||||||
|||17<br>12||||13<br>12|||
|||16<br>13|||||||
||||||||||
|||15<br>14|||||||
|GPB1 <br>GPB2 <br>GPB3 <br>GPB4 <br>GPB5 <br>GPB6||**QFN**<br>GPA6 21<br>GPA7 22<br>VSS<br>23<br>GPA5 20<br>GPA4 19<br>GPA3<br>18<br>GPA2<br>17<br>GPA1<br>16<br>GPA0<br>15<br>INTA<br>14<br>VDD 8<br>SCL 9<br>SDA 10<br>ADDR 11<br>R<br>ESET<br>12<br>GPB0 24<br>GPB7 7<br>INTB<br>13<br>EP<br>25|**QFN**<br>GPA6 21<br>GPA7 22<br>VSS<br>23<br>GPA5 20<br>GPA4 19<br>GPA3<br>18<br>GPA2<br>17<br>GPA1<br>16<br>GPA0<br>15<br>INTA<br>14<br>VDD 8<br>SCL 9<br>SDA 10<br>ADDR 11<br>R<br>ESET<br>12<br>GPB0 24<br>GPB7 7<br>INTB<br>13<br>EP<br>25|
|---|---|---|---|
||1<br> 2<br> 3<br> 4<br> 5<br> 6|24<br> 7|21<br> 22<br>23<br> 20<br> 19<br>18<br>17<br>16<br>15<br>14<br> 8<br> 9<br> 10<br> 11<br>12<br>13<br>EP<br>25|
|||||
DS22103A-page 2
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **Package Types:**
|VSS<br>NC<br>GPB0<br>GPB1<br>GPB2<br>GPB3<br>GPB4<br>GPB5<br>GPB6<br>GPB7<br>VDD<br>CS<br>SCK<br>SI||**PDIP/SOIC**<br><br>|**PDIP/SOIC**<br><br>|**MCP23S18**<br>NC<br>GPA7<br>GPA6<br>GPA5<br>GPA4<br>GPA3<br>GPA2<br>GPA1<br>GPA0<br>INTA<br>INTB<br>NC<br>R<br>ESET<br>SO<br>GPB1 <br>GPB2 <br>GPB3 <br>GPB4 <br>GPB5 <br>GPB6||**QFN ***<br>GPA6 <br>GPA7 <br>VSS<br>GPA5 <br>GPA4 <br>GPB0|**QFN ***<br>GPA6 <br>GPA7 <br>VSS<br>GPA5 <br>GPA4 <br>GPB0|GPA3<br>GPA2<br>GPA1<br>GPA0<br>INTA *<br>RESET|
|---|---|---|---|---|---|---|---|---|
||||||||||
|||28<br>1|||||||
||||||||||
|||27<br>2|||||||
||||||||||
|||26<br>3|||1<br> 2<br> 3<br> 4<br> 5<br> 6|24<br> 7|21<br> 22<br>23<br> 20<br> 19<br>18<br>17<br>16<br>15<br>14<br> 8<br>9<br> 10<br> 11<br> 12<br>13<br>EP<br>25||
||||||||||
|||25<br>4|||||||
|||24<br>5|||||||
||||||||||
|||23<br>6|||||||
||||||||||
|||22<br>7|||||||
|||21<br>8|||||||
||||||||||
|||20<br>9|||||||
||||||||||
|||19<br>10|||||||
|||18<br>11|||||||
|||17<br>12||||GPB7|VDD <br>CS<br>SCK <br>SI <br>SO||
|||16<br>13|||||||
||||||||||
|||15<br>14|||||||
* INTB is not bonded out. Can be controlled in IOCON.MIRROR
DS22103A-page 3
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **1.0 DEVICE OVERVIEW**
The MCP23X18 device provides 16-bit, general purpose parallel I/O expansion for I[2] C bus or SPI applications. The two devices differ only in the serial interface.
- MCP23018 - I[2] C interface
- MCP23S18 - SPI interface
The MCP23X18 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the input port register can be inverted with the polarity inversion register. All registers can be read by the system master.
The 16-bit I/O port functionally consists of two (2) 8-bit ports (PORTA and PORTB). The MCP23X18 can be configured to operate in 8-bit mode or 16-bit mode via IOCON.BANK.
There are two interrupt pins, INTA and INTB which can be associated with their respective ports, or can be logically OR’ed together so both pins will activate if either port causes an interrupt.
The interrupt output can be configured to activate under two conditions (mutually exclusive):
1. When any input state differs from its corresponding input port register state. This is used to indicate to the system master that an input state has changed.
2. When an input state differs from a preconfigured register value (DEFVAL register).
The Interrupt Capture register captures port values at the time of the interrupt, thereby saving the condition that caused the interrupt.
The Power-on Reset (POR) sets the registers to their default values and initializes the device state machine.
The hardware address pin is used to determine the device address.
DS22103A-page 4
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **1.1 Pin Descriptions**
**TABLE 1-1: I[2] C PINOUT DESCRIPTION (MCP23018)**
|**Pin**<br>**Name**|**28L**<br>**PDIP/**<br>**SOIC**|**24L**<br>**QFN**|**24L**<br>**SSOP**|**Pin**<br>**Type**|**Standard Function**|
|---|---|---|---|---|---|
|GPB0|3|24|2|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPB1|4|1|3|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPB2|5|2|4|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPB3|6|3|5|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPB4|7|4|6|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPB5|8|5|7|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPB6|9|6|8|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPB7|10|7|9|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|VDD|11|8|10|P|Power|
|VSS|1|23|1|P|Ground|
|SCL|12|9|11|I|Serial clock input|
|SDA|13|10|12|I/O|Serial data I/O|
|ADDR|15|11|13|I|Hardware addresspin allows upto 8 slave devices on the bus|
|RESET|16|12|14|I|Hardware reset|
|INTB|18|13|15|O|Interrupt output for port B. Can be configured as active high, active low, or<br>open drain.|
|INTA|19|14|16|O|Interrupt output for port A. Can be configured as active high, active low, or<br>open drain.|
|GPA0|20|15|17|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPA1|21|16|18|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPA2|22|17|19|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPA3|23|18|20|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPA4|24|19|21|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPA5|25|20|22|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPA6|26|21|23|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|GPA7|27|22|24|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be<br>enabled for interrupt on change, and/or internalpull-upresistor.|
|NC|2, 14,<br>17, 28|—|—||Not connected|
|EP|—|25|—||Exposed Thermal Pad(EP). Do not electricallyconnect, or connect to VSS.|
DS22103A-page 5
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## **TABLE 1-2: SPI PINOUT DESCRIPTION (MCP23S18)**
|**Pin**<br>**Name**|**28L**<br>**PDIP/**<br>**SOIC**|**24L**<br>**QFN**|**Pin**<br>**Type**|**Standard Function**|
|---|---|---|---|---|
|GPB0|3|24|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPB1|4|1|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPB2|5|2|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPB3|6|3|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPB4|7|4|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPB5|8|5|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPB6|9|6|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPB7|10|7|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|VDD|11|8|P|Power(high current capable)|
|VSS|1|23|P|Ground(high current capable)|
|CS|12|9|I|Chipselect|
|SCK|13|10|I|Serial clock input|
|SI|14|11|I|Serial data input|
|SO|15|12|O|Serial data out|
|RESET|16|13|I|Hardware reset(must be externallybiased)|
|INTB|18|—|O|Interrupt output for port B. Can be configured as active high, active low, or open<br>drain.|
|INTA|19|14|O|Interrupt output for port A. Can be configured as active high, active low, or open<br>drain.|
|GPA0|20|15|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPA1|21|16|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPA2|22|17|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPA3|23|18|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPA4|24|19|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPA5|25|20|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPA6|26|21|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|GPA7|27|22|I/O|Bidirectional I/O Pin (5.5 volt tolerant inputs; open-drain outputs). Can be enabled<br>for interrupt on change, and/or internalpull-upresistor.|
|NC|2, 17,<br>28|—||Not connected|
|EP|—|25|—|Exposed Thermal Pad(EP). Do not electricallyconnect, or connect to VSS.|
DS22103A-page 6
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **1.2 Power-on Reset (POR)**
The on-chip POR circuit holds the device in reset until VDD has reached a high enough voltage to deactivate the POR circuit (i.e., release the device from reset). The maximum VDD rise time is specified in the electrical specification section.
When the device exits the POR condition (releases reset), device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation.
## **1.3 Serial Interface**
This block handles the functionality of the I[2] C (MCP23018) or SPI (MCP23S18) interface protocol. The MCP23X18 contains twenty two (22) individual registers (eleven [11] register pairs) which can be addressed through the Serial Interface block (Table 1- 1).
## **TABLE 1-1: REGISTER ADDRESSES**
|**Address**<br>**IOCON.BANK = 1**|**Address**<br>**IOCON.BANK = 0**|**Access to:**|
|---|---|---|
|00h|00h|IODIRA|
|10h|01h|IODIRB|
|01h|02h|IPOLA|
|11h|03h|IPOLB|
|02h|04h|GPINTENA|
|12h|05h|GPINTENB|
|03h|06h|DEFVALA|
|13h|07h|DEFVALB|
|04h|08h|INTCONA|
|14h|09h|INTCONB|
|05h|0Ah|IOCON|
|15h|0Bh|IOCON|
|06h|0Ch|GPPUA|
|16h|0Dh|GPPUB|
|07h|0Eh|INTFA|
|17h|0Fh|INTFB|
|08h|10h|INTCAPA|
|18h|11h|INTCAPB|
|09h|12h|GPIOA|
|19h|13h|GPIOB|
|0Ah|14h|OLATA|
|1Ah|15h|OLATB|
## 1.3.1 BYTE MODE AND SEQUENTIAL MODE
The MCP23X18 has the ability to operate in “Byte Mode” or “Sequential Mode” (IOCON.SEQOP). Byte mode and sequential mode are not to be confused with I[2] C byte operations and sequential operations. The
modes explained here relate to the device’s internal address pointer and whether or not it is incremented after each byte is clocked on the serial interface.
**Byte Mode** disables automatic address pointer incrementing. When operating in Byte Mode, the MCP23X18 does not increment its internal address counter after each byte during the data transfer. This gives the ability to continually access the same address by providing extra clocks (without additional control bytes). This is useful for polling the GPIO register for data changes or for continually writing to the output latches.
A special mode **(Byte Mode with IOCON.BANK = 0)** causes the address pointer to toggle between associated A/B register pairs. For example, if the BANK bit is cleared and the address pointer is initially set to address 12h (GPIOA) or 13h (GPIOB), the pointer will toggle between GPIOA and GPIOB. Note, the address pointer can initially point to either address in the register pair.
**Sequential Mode** enables automatic address pointer incrementing. When operating in Sequential Mode, the MCP23X18 increments its address counter after each byte during the data transfer. The address pointer automatically rolls over to address 00h after accessing the last register.
These two modes are not to be confused with single writes/reads and continuous writes/reads which are serial protocol sequences. For example, the device may be configured for Byte Mode and the master may perform a continuous read. In this case, the MCP23X18 would not increment the address pointer and would repeatedly drive data from the same location.
## 1.3.2 I[2] C INTERFACE
## 1.3.2.1 I[2] C Write Operation
The I[2] C write operation includes the control byte and register address sequence, as shown in the bottom of Figure 1-1. This sequence is followed by eight bits of data from the master and an Acknowledge (ACK) from the MCP23018. The operation is ended with a stop (P) or restart (SR) condition being generated by the master.
Data is written to the MCP23018 after every byte transfer. If a stop or restart condition is generated during a data transfer, the data will not be written to the MCP23018.
Both “byte mode” and “sequential mode” are supported by the MCP23018. If sequential mode is enabled (default), the MCP23018 increments its address counter after each ACK during the data transfer.
DS22103A-page 7
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## 1.3.2.2 I[2] C Read Operation
I[2] C read operations include the control byte sequence, as shown in the bottom of Figure 1-1. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit equal to a logic one (R/W = `1` ). The MCP23018 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition.
## 1.3.2.3 I[2] C Sequential Write/Read
For sequential operations (Write or Read), instead of transmitting a Stop or Restart condition after the data transfer, the master clocks the next byte pointed to by the address pointer (see **Section 1.3.1 “Byte Mode and Sequential Mode”** for details regarding sequential operation control).
The sequence ends with the master sending a Stop or Restart condition.
The MCP23018 address pointer will roll over to address zero after reaching the last register address.
Refer to Figure 1-1.
## 1.3.3 SPI INTERFACE
## 1.3.3.1 SPI Write Operation
The SPI write operation is started by lowering CS. The write command (slave address with R/W bit cleared) is then clocked into the device. The opcode is followed by an address and at least one data byte.
## 1.3.3.2 SPI Read Operation
The SPI read operation is started by lowering CS. The SPI read command (slave address with R/W bit set) is then clocked into the device. The opcode is followed by an address, with at least one data byte being clocked out of the device.
## 1.3.3.3 SPI Sequential Write/Read
For sequential operations, instead of deselecting the device by raising CS, the master clocks the next byte pointed to by the address pointer. (see **Section 1.3.1 “Byte Mode and Sequential Mode”** for details regarding sequential operation control).
The sequence ends by the raising of CS.
The MCP23S18 address pointer will roll over to address zero after reaching the last register address.
DS22103A-page 8
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **FIGURE 1-1: MCP23018 I[2] C™ DEVICE PROTOCOL**
**==> picture [468 x 477] intentionally omitted <==**
**----- Start of picture text -----**<br>
S - Start<br>SR - Restart<br>S OP W ADDR DIN .... DIN P<br>P - Stop<br>w - Write SR OP R DOUT .... DOUT P<br>R - Read<br>OP - Device opcode SR OP W ADDR .... DIN P<br>ADDR - Device address<br>P<br>DOUT - Data out from MCP23018<br>DIN - Data in to MCP23018<br>S OP R DOUT .... DOUT P<br>SR OP R DOUT .... DOUT P<br>SR OP W ADDR DIN .... DIN P<br>P<br>Byte and Sequential Write<br>Byte S OP W ADDR DIN P<br>Sequential S OP W ADDR DIN .... DIN P<br>Byte and Sequential Read<br>Byte S OP W ADDR SR OP R DOUT P<br>Sequential S OP W ADDR SR OP R DOUT .... DOUT P<br>**----- End of picture text -----**<br>
DS22103A-page 9
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## **1.4 Multi-bit Address Decoder**
The ADDR pin is used to set the slave address of the MCP23018 (I[2] C only) to allow up to eight devices on the bus using only a single pin. Typically, this would require three pins.
The multi-bit Address Decoder employs a basic FLASH ADC architecture (Figure 1-4). The seven comparators generate 8 unique values based on the analog input. This value is converted to a 3-bit code which corresponds to the address bits (A2, A1, A0) in the serial OPCODE.
## **Sequence of Operation (see Figure 1-5 for timings):**
1. Upon power up (after VDD stabilizes) the module becomes active after time tADEN. Note, the analog value on the ADDR pin must be stable before this point to ensure accurate address assignment.
2. The 3-bit address is latched after tADDRLAT.
3. The module powers down after the first rising edge of the serial clock is detected (tADDIS).
Once the address bits are latched, the device will keep the slave address until a POR or reset condition occurs.
## 1.4.1 CALCULATING VOLTAGE ON ADDR
When calculating the required voltage on the ADDR pin (V2), the set point should be the mid-point of the LSb of the ADC.
The examples in Figure 1-2 and Figure 1-3 show how to determine the mid point voltage (V2) and the range of voltages based on a voltage divider circuit. The maximum tolerance is 20%, however, it is recommended to use 5% tolerance worst case (10% total tolerance).
**FIGURE 1-2:**
## **VOLTAGE DIVIDER EXAMPLE**
**==> picture [340 x 260] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD VDD<br>ADDR MCP23018<br>A0<br>R1<br>A1<br>A2<br>V2<br>R2<br>VSS<br>VSS<br>**----- End of picture text -----**<br>
DS22103A-page 10
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **FIGURE 1-3: VOLTAGE AND CODE EXAMPLE**
Assume: n = A2, A1, A0 in opcode ratio = R2/(R1+R2) V2 = voltage on ADDR pin V2(min) = V2 - (VDD/8) x %tolerance V2(max) = V2 + (VDD/8) x %tolerance
|**VDD= 1.8**|**VDD= 1.8**|**VDD= 1.8**|**VDD= 1.8**|**VDD= 1.8**|**10% Tolerance (total)**|**10% Tolerance (total)**|
|---|---|---|---|---|---|---|
|**n**|**R2=2n+1**|**R1=16-R2**|**R2/(R1+R2)**|**V2**|**V2(min)**|**V2(max)**|
|0|1|15|0.0625|**0.113**|0.00|0.14|
|1|3|13|0.1875|**0.338**|0.32|0.36|
|2|5|11|0.3125|**0.563**|0.54|0.59|
|3|7|9|0.4375|**0.788**|0.77|0.81|
|4|9|7|0.5625|**1.013**|0.99|1.04|
|5|11|5|0.6875|**1.238**|1.22|1.26|
|6|13|3|0.8125|**1.463**|1.44|1.49|
|7|15|1|0.9375|**1.688**|1.67|1.80|
|**VDD= 2.7**|||||||
||||||**10% Tolerance (total)**||
|**n**|**R2=2n+1**|**R1=16-R2**|**R2/(R1+R2)**|**V2**|**V2(min)**|**V2(max)**|
|0|1|15|0.0625|**0.169**|0.00|0.19|
|1|3|13|0.1875|**0.506**|0.48|0.53|
|2|5|11|0.3125|**0.844**|0.82|0.87|
|3|7|9|0.4375|**1.181**|1.16|1.20|
|4|9|7|0.5625|**1.519**|1.50|1.54|
|5|11|5|0.6875|**1.856**|1.83|1.88|
|6|13|3|0.8125|**2.194**|2.17|2.22|
|7|15|1|0.9375|**2.531**|2.51|2.70|
|**VDD=3.3**|||||||
||||||**10% Tolerance (total)**||
|**n**|**R2=2n+1**|**R1=16-R2**|**R2/(R1+R2)**|**V2**|**V2(min)**|**V2(max)**|
|0|1|15|0.0625|**0.206**|0.00|0.23|
|1|3|13|0.1875|**0.619**|0.60|0.64|
|2|5|11|0.3125|**1.031**|1.01|1.05|
|3|7|9|0.4375|**1.444**|1.42|1.47|
|4|9|7|0.5625|**1.856**|1.83|1.88|
|5|11|5|0.6875|**2.269**|2.25|2.29|
|6|13|3|0.8125|**2.681**|2.66|2.70|
|7|15|1|0.9375|**3.094**|3.07|3.30|
|**VDD= 5.5**|**VDD= 5.5**|**VDD= 5.5**|**VDD= 5.5**|**VDD= 5.5**|**10% Tolerance (total)**|**10% Tolerance (total)**|
|---|---|---|---|---|---|---|
|**n**|**R2=2n+1**|**R1=16-R2**|**R2/(R1+R2)**|**V2**|**V2(min)**|**V2(max)**|
|0|1|15|0.0625|**0.344**|0.00|0.37|
|1|3|13|0.1875|**1.031**|1.01|1.05|
|2|5|11|0.3125|**1.719**|1.70|1.74|
|3|7|9|0.4375|**2.406**|2.38|2.43|
|4|9|7|0.5625|**3.094**|3.07|3.12|
|5|11|5|0.6875|**3.781**|3.76|3.80|
|6|13|3|0.8125|**4.469**|4.45|4.49|
|7|15|1|0.9375|**5.156**|5.13|5.50|
DS22103A-page 11
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
**FIGURE 1-4: FLASH ADC BLOCK DIAGRAM**
**==> picture [384 x 356] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>analog_in<br>addr_out[6] addr[6:0] i2c_addr[2:0]<br>d q<br>adc_en adc_en en<br>addr_out[5]<br>adc_en reset<br>addr_out[4] '0' d set q adc_en<br>a dc_en<br>i2c_clk<br>addr_out[3]<br>adc_en<br>addr_out[2]<br>adc_en<br>addr_out[1]<br>adc_en<br>addr_out[0]<br>a dc_en<br>adc_en<br>gnd<br>**----- End of picture text -----**<br>
DS22103A-page 12
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **FIGURE 1-5: HARDWARE ADDRESS DECODE TIMING**
**==> picture [442 x 171] intentionally omitted <==**
**----- Start of picture text -----**<br>
tADEN<br>VDD<br>tADDRLAT<br>adc_en<br>i2c_addr[2:0]<br>tADDIS<br>i2c_clk<br>**----- End of picture text -----**<br>
## 1.4.2 ADDRESSING I[2] C DEVICES (MCP23018)
The MCP23018 is a slave I[2] C device that supports 7- bit slave addressing, with the read/write bit filling out the control byte. The slave address contains four fixed bits and three user-defined hardware address bits (pins A2, A1, and A0). Figure 1-6 shows the control byte format.
## 1.4.3 ADDRESSING SPI DEVICES (MCP23S18)
The MCP23S18 is a slave SPI device. The slave address contains seven fixed bits(no address bits) with the read/write bit filling out the control byte. Figure 1-7 shows the control byte format.
## **FIGURE 1-6: I[2] C™ CONTROL BYTE FORMAT**
**==> picture [213 x 98] intentionally omitted <==**
**----- Start of picture text -----**<br>
Control Byte<br>S 0 1 0 0 A2 A1 A0 R/W ACK<br>Slave Address<br>Start R/W bit<br>bit ACK bit<br>R/W = 0 = write<br>R/W = 1 = read<br>**----- End of picture text -----**<br>
## **FIGURE 1-7:**
## **SPI CONTROL BYTE FORMAT**
**==> picture [209 x 111] intentionally omitted <==**
**----- Start of picture text -----**<br>
CS<br>Control Byte<br>0 1 0 0 0 0 0 R/W<br>Slave Address<br>R/W bit<br>R/W = 0 = write<br>R/W = 1 = read<br>**----- End of picture text -----**<br>
DS22103A-page 13
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
**==> picture [468 x 276] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 1-8: I [2] C™ ADDRESSING REGISTERS<br>S 0 1 0 0 A2 A1 A0 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK<br>R/W = 0<br>Device Opcode Register Address<br>The ACKs are provided by the MCP23X18.<br>FIGURE 1-9: SPI ADDRESSING REGISTERS<br>CS<br>0 1 0 0 0 0 0 R/W A7 A6 A5 A4 A3 A2 A1 A0<br>Device Opcode Register Address<br>**----- End of picture text -----**<br>
DS22103A-page 14
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **1.5 GPIO Port**
The GPIO module is a general purpose 16-bit wide bidirectional port which is functionally split into two (2) 8-bit wide ports.
The outputs are open-drain.
The GPIO module contains the data ports (GPIOn), internal pull up resistors and the Output Latches (OLATn).
The pull up resistors are individually configured and can be enabled when the pin is cofigured as an input or output.
Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port.
Writing to the GPIOn register actually causes a write to the latches (OLATn). Writing to the OLATn register forces the associated output drivers to drive to the level in OLATn. Pins configured as inputs turn off the associated output driver and put it in high-impedance.
## **TABLE 1-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 1)**
|**Register**<br>**Name**|**Address**<br>**(hex)**|**bit 7**|**bit 6**|**bit 5**|**bit 4**|**bit 3**|**bit 2**|**bit 1**|**bit 0**|**POR/RST**<br>**value**|
|---|---|---|---|---|---|---|---|---|---|---|
|IODIRA|00|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`|
|IPOLA|01|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`|
|GPINTENA|02|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`|
|GPPUA|06|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`|
|GPIOA|09|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`|
|OLATA|0A|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`|
|IODIRB|10|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`|
|IPOLB|11|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`|
|GPINTENB|12|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`|
|GPPUB|16|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`|
|GPIOB|19|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`|
|OLATB|1A|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`|
## **TABLE 1-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK = 0)**
|**Register**<br>**Name**|**Address**<br>**(hex)**|**bit 7**|**bit 6**|**bit 5**|**bit 4**|**bit 3**|**bit 2**|**bit 1**|**bit 0**|**POR/RST**<br>**value**|
|---|---|---|---|---|---|---|---|---|---|---|
|IODIRA|00|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`|
|IODIRB|01|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`|
|IPOLA|02|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`|
|IPOLB|03|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`|
|GPINTENA|04|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`|
|GPINTENB|05|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`|
|GPPUA|0C|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`|
|GPPUB|0D|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`|
|GPIOA|12|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`|
|GPIOB|13|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`|
|OLATA|14|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`|
|OLATB|15|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`|
DS22103A-page 15
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **1.6 Configuration and Control Registers**
There are twenty two (22) registers associated with the MCP23X18 as shown in Table 1-4 and Table 1-5. The two tables show the register mapping with the two BANK bit values. Ten (10) registers are associated
with Port A and ten (10) are associated with Port B. One register (IOCON) is shared between the two ports. The Port A registers are identical to the Port B registers, therefore, they will be referred to without differentiating between the port designation (i.e., they will not have the “A” or “B” designator assigned) in the register tables.
## **TABLE 1-4: CONTROL REGISTER SUMMARY (IOCON.BANK = 1)**
|**Register**<br>**Name**|**Address**<br>**(hex)**|**bit 7**|**bit 6**|**bit 5**|**bit 4**|**bit 3**|**bit 2**|**bit 1**|**bit 0**|**POR/RST**<br>**value**|
|---|---|---|---|---|---|---|---|---|---|---|
|IODIRA|00|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`|
|IPOLA|01|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`|
|GPINTENA|02|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`|
|DEFVALA|03|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|`0000 0000`|
|INTCONA|04|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|`0000 0000`|
|IOCON|05|BANK|MIRROR|SEQOP|—|—|ODR|INTPOL|INTCC|`0000 0000`|
|GPPUA|06|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`|
|INTFA|07|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INTO|`0000 0000`|
|INTCAPA|08|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|`0000 0000`|
|GPIOA|09|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`|
|OLATA|0A|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`|
|IODIRB|10|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`|
|IPOLB|11|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`|
|GPINTENB|12|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`|
|DEFVALB|13|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|`0000 0000`|
|INTCONB|14|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|`0000 0000`|
|IOCON|15|BANK|MIRROR|SEQOP|—|—|ODR|INTPOL|INTCC|`0000 0000`|
|GPPUB|16|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`|
|INTFB|17|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INTO|`0000 0000`|
|INTCAPB|18|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|`0000 0000`|
|GPIOB|19|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`|
|OLATB|1A|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`|
DS22103A-page 16
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **TABLE 1-5: CONTROL REGISTER SUMMARY (IOCON.BANK = 0)**
|**Register**<br>**Name**|**Address**<br>**(hex)**|**bit 7**|**bit 6**|**bit 5**|**bit 4**|**bit 3**|**bit 2**|**bit 1**|**bit 0**|**POR/RST**<br>**value**|
|---|---|---|---|---|---|---|---|---|---|---|
|IODIRA|00|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`|
|IODIRB|01|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`|
|IPOLA|02|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`|
|IPOLB|03|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`|
|GPINTENA|04|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`|
|GPINTENB|05|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`|
|DEFVALA|06|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|`0000 0000`|
|DEFVALB|07|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|`0000 0000`|
|INTCONA|08|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|`0000 0000`|
|INTCONB|09|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|`0000 0000`|
|IOCON|0A|BANK|MIRROR|SEQOP|—|—|ODR|INTPOL|INTCC|`0000 0000`|
|IOCON|0B|BANK|MIRROR|SEQOP|—|—|ODR|INTPOL|INTCC|`0000 0000`|
|GPPUA|0C|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`|
|GPPUB|0D|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`|
|INTFA|0E|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INTO|`0000 0000`|
|INTFB|0F|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INTO|`0000 0000`|
|INTCAPA|10|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|`0000 0000`|
|INTCAPB|11|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|`0000 0000`|
|GPIOA|12|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`|
|GPIOB|13|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`|
|OLATA|14|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`|
|OLATB|15|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`|
DS22103A-page 17
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## 1.6.1 I/O DIRECTION REGISTER
Controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output.
## **REGISTER 1-3: IODIR – I/O DIRECTION REGISTER**
|**REGISTER 1-3:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-3:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-3:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-3:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-3:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-3:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-3:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-3:**<br>**IODIR – I/O DIRECTION REGISTER**|
|---|---|---|---|---|---|---|---|
|R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1||||||||
|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
bit 7-0 **IO7:IO0:** Controls the direction of data I/O <7:0>
- `1` = Pin is configured as an input.
- `0` = Pin is configured as an output.
DS22103A-page 18
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## 1.6.2 INPUT POLARITY REGISTER
This register allows the user to configure the polarity on the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin.
## **REGISTER 1-4: IPOL – INPUT POLARITY PORT REGISTER**
|**REGISTER 1-4:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-4:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-4:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-4:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-4:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-4:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-4:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-4:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
|||||||||
bit 7-0 **IP7:IP0:** Controls the polarity inversion of the input pins <7:0>
- `1` = GPIO register bit will reflect the opposite logic state of the input pin.
- `0` = GPIO register bit will reflect the same logic state of the input pin.
DS22103A-page 19
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## 1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER
The GPINTEN register controls the interrupt-onchange feature for each pin.
If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change.
## **REGISTER 1-5: GPINTEN – INTERRUPT-ON-CHANGE PINS**
|**REGISTER 1-5:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-5:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-5:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-5:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-5:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-5:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-5:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-5:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
|||||||||
bit 7-0 **GPINT7:GPINT0:** General purpose I/O interrupt-on-change pins <7:0>
`1` = Enable GPIO input pin for interrupt-on-change event
- `0` = Disable GPIO input pin for interrupt-on-change event.
DS22103A-page 20
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## 1.6.4 DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur.
## **REGISTER 1-6: DEFVAL – DEFAULT VALUE REGISTER**
|**REGISTER 1-6:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-6:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-6:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-6:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-6:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-6:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-6:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-6:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|
|bit 7<br>bit 0||||||||
## **Legend:**
|**Legend:**|||
|---|---|---|
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|
|-n = Value at POR|‘1’ = Bit is set|‘0’ = Bit is cleared<br>x = Bit is unknown|
bit 7-0 **DEF7:DEF0:** Sets the compare value for pins configured for interrupt-on-change from defaults <7:0>. Refer to INTCON.
If the associated pin level is the opposite from the register bit, an interrupt occurs.
Refer to INTCON and GPINTEN.
DS22103A-page 21
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## 1.6.5 INTERRUPT CONTROL REGISTER
The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value.
## **REGISTER 1-7: INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**
|**REGISTER 1-7:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-7:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-7:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-7:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-7:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-7:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-7:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-7:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
bit 7-0 **IOC7:IOC0:** Controls how the associated pin value is compared for interrupt-on-change <7:0>. `1` = Pin value is compared against the associated bit is DEFVAL register
`0` = Pin value is compared against the previous pin value.
Refer to INTCON and GPINTEN.
DS22103A-page 22
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## 1.6.6 CONFIGURATION REGISTER
The IOCON register contains several bits for configuring the device:
The **BANK** bit changes how the registers are mapped (see Table 1-4 and Table 1-5 for more details).
- If BANK = 1, the registers associated with each port are segregated. Registers associated with PORTA are are mapped from address 00h - 0Ah and registers associated with PORTB are mapped from Address 10h - 1Ah
- If BANK = 0, the A/B registers are paired. For example, IODIRA is mapped to address 00h and IODIRB is mapped to the next address (address 01h). The mapping for all registers is from 00h - 15h
It is important to take care when changing the BANK bit as the address mapping changes after the byte is clocked into the device. The address pointer may point to an invalid location after the bit is modified.
For example, if the device is configured to automatically increment its internal address pointer the following scenario would occur:
- BANK = 0
- Write 80h to 0Ah (IOCON) to set the BANK bit
- After the write completes the internal address now points to 0Bh which is an invalid address when the BANK bit is set
For this reason, it is advised to only perform byte writes to this register when changing the BANK bit.
**Note:**
The INTB pin is not bonded out on the MCP23S18 (SPI) device in the 24-lead QFN package. The **MIRROR** bit must be configured to a “ `1` ” in order for interrupts to be detected on PORTB.
The **MIRROR** bit controls how the INTA and INTB pins function with respect to each other.
- When MIRROR = 1, the INTn pins are functionally OR’ed so that an interrupt on either port will cause both pins to activate
- When MIRROR = 0, the INT pins are separated. Interrupt conditions on a port will cause its respective INT pin to activate
The Sequential Operation ( **SEQOP** ) controls the incrementing function of the address pointer. If the address pointer is disabled, the address pointer does not automatically increment after each byte is clocked during a serial transfer. This feature is useful when it is desired to continuously poll (read) or modify (write) a register.
The Open-Drain ( **ODR** ) control bit enables/disables the INT pin for open-drain configuration.
The Interrupt Polarity ( **INTPOL** ) sets the polarity of the INT pin. This bit is functional only when the ODR bit is cleared, configuring the INT pin as active push-pull.
The Interrupt Clearing Control ( **INTCC** ) configures how interrupts are cleared. When set (INTCC = 1), the interrupt is cleared when the INTCAP register is read. When cleared (INTCC = 0), the interrupt is cleared when the GPIO register is read.
The interrupt can only be cleared when the interrupt condition is inactive. Refer to **Section 1.7.5 “Clearing Interrupts”** for details.
DS22103A-page 23
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## **REGISTER 1-8:**
## **IOCON – I/O EXPANDER CONFIGURATION REGISTER**
|**REGISTER 1-8:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-8:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-8:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-8:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-8:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-8:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-8:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-8:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|
|---|---|---|---|---|---|---|---|
|||||||||
|R/W-0<br>R/W-0<br>R/W-0<br>U-0<br>U-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|BANK|MIRROR|SEQOP|-|-|ODR|INTPOL|INTCC|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
- bit 7 **BANK:** Controls how the registers are addressed (see Figure 1-4 and Figure 1-5) 1 = The registers associated with each port are separated into different banks
- 0 = The registers are in the same bank (addresses are sequential)
- bit 6 **MIRROR:** INT pins mirror bit 1 = The INT pins are internally connected in a wired OR configuration
- 0 = The INT pins are not connected. INTA is associated with Port A and INTB is associated with Port B
- bit 5 **SEQOP:** Sequential Operation mode bit.
- `1` = Sequential operation disabled, address pointer does not increment.
- `0` = Sequential operation enabled, address pointer increments.
- bit 4 **Unimplemented** : Reads as 0
- bit 3 **Unimplemented:** Reads as 0
- bit 2 **ODR:** Configures the INT pin as an open-drain output.
- `1` = Open-drain output (overrides the INTPOL bit).
- `0` = Active driver output (INTPOL bit sets the polarity).
- bit 1 **INTPOL:** Sets the polarity of the INT output pin.
- `1` = Active-high.
- `0` = Active-low.
- bit 0 **INTCC:** Interrupt Clearing Control
- 1 = Reading INTCAP register clears the interrupt
- 0 = Reading GPIO register clears the interrupt
DS22103A-page 24
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## 1.6.7 PULL-UP RESISTOR CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the port pins. If a bit is set the corresponding port pin is internally pulled up with an internal resistor.
## **REGISTER 1-9: GPPU – GPIO PULL-UP RESISTOR REGISTER**
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|
|---|---|---|---|---|---|---|---|
|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
bit 7-0
**PU7:PU0:** Controls the internal pull-up resistors on each pin (when configured as an input or output) <7:0>.
`1` = Pull-up enabled.
`0` = Pull-up disabled.
## **FIGURE 1-10: TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS**
**==> picture [448 x 307] intentionally omitted <==**
**----- Start of picture text -----**<br>
GPIO Pin Internal Pull-up Current vs VDD<br>400<br>350<br>T = -40°C<br>300<br>T = +25°C<br>250<br>200<br>150<br>°<br>T = +125 C<br>100<br>T = +85°C<br>50<br>0<br>1.5 2 2.5 3 3.5 4 4.5 5 5.5<br>VDD (V)<br> (µA)<br>PU<br>I<br>**----- End of picture text -----**<br>
DS22103A-page 25
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## 1.6.8 INTERRUPT FLAG REGISTER
The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A ‘set’ bit indicates that the associated pin caused the interrupt.
This register is ‘read only’. Writes to this register will be ignored.
## **REGISTER 1-10: INTF – INTERRUPT FLAG REGISTER**
|**REGISTER 1-10:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-10:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-10:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-10:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-10:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-10:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-10:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-10:**<br>**INTF – INTERRUPT FLAG REGISTER**|
|---|---|---|---|---|---|---|---|
|R-0<br>R-0<br>R-0<br>R-0<br>R-0<br>R-0<br>R-0<br>R-0||||||||
|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INT0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
|||||||||
bit 7-0 **INT7:INT0:** Reflects the interrupt condition on the port. Will reflect the change only if interrupts are enabled (GPINTEN) <7:0>.
- `1` = Pin caused interrupt.
- `0` = Interrupt not pending.
DS22103A-page 26
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## 1.6.9 INTERRUPT CAPTURE REGISTER
The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is ‘read only’ and is updated only when an interrupt occurs. The register will remain unchanged until the interrupt is cleared via a read of INTCAP or GPIO.
## **REGISTER 1-11: INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**
|**REGISTER 1-11:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-11:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-11:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-11:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-11:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-11:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-11:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-11:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|
|---|---|---|---|---|---|---|---|
|R-x<br>R-x<br>R-x<br>R-x<br>R-x<br>R-x<br>R-x<br>R-x||||||||
|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
|||||||||
bit 7-0 **ICP7:ICP0:** Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0>. `1` = Logic-high.
`0` = Logic-low.
DS22103A-page 27
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## 1.6.10 PORT REGISTER
The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register.
## **REGISTER 1-12: GPIO – GENERAL PURPOSE I/O PORT REGISTER**
|**REGISTER 1-12:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-12:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-12:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-12:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-12:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-12:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-12:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-12:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
bit 7-0 **GP7:GP0:** Reflects the logic level on the pins <7:0>.
- `1` = Logic-high.
- `0` = Logic-low.
DS22103A-page 28
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## 1.6.11 OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs.
## **REGISTER 1-13: OLAT – OUTPUT LATCH REGISTER 0**
|**REGISTER 1-13:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-13:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-13:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-13:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-13:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-13:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-13:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-13:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
|||||||||
bit 7-0 **OL7:OL0:** Reflects the logic level on the output latch <7:0>.
`1` = Logic-high.
- `0` = Logic-low.
DS22103A-page 29
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## **1.7 Interrupt Logic**
If enabled, the MCP23X18 activates the INTn interrupt output when one of the port pins changes state or when a pin does not match the pre-configured default. Each pin is individually configurable as follows:
- Enable/disable interrupt via GPINTEN
- Can interrupt on either pin change or change from default as configured in DEFVAL
Both conditions are referred to as Interrupt on Change (IOC).
The Interrupt Control (INT) Module uses the following registers/bits:
- IOCON.MIRROR - controls if the two interrupt pins mirror each other.
- GPINTEN - Interrupt enable register
- INTCON - Controls the source for the IOC
- DEFVAL - Contains the register default for IOC operation
## 1.7.1 INTA AND INTB
There are two interrupt pins, INTA and INTB. By default, INTA is associated with GPAn pins (Port A) and INTB is associated with GPBn pins (Port B). Each port has an independent signal which is cleared if its associated GPIO or INTCAP register is read.
## 1.7.1.1 Mirroring the INT pins
Additionally, the INTn pins can be configured to mirror each other so that any interrupt will cause both pins to go active. This is controlled via IOCON.MIRROR.
If IOCON.MIRROR = 0, the internal signals are routed independently to the INTA and INTB pads.
If IOCON.MIRROR = 1, the internal signals are OR’ed together and routed to the INTn pads. In this case, the interrupt will only be cleared if the associated GPIO or INTCAP is read (see Table 1-6).
**TABLE 1-6: INTERRUPT OPERATION (IOCON.MIRROR = 1)**
|**Interrupt**<br>**Condition**|**Read Port N***|**Interupt**<br>**Result**|
|---|---|---|
|GPIOA|Port A|Clear|
||Port B|Unchanged|
|GPIOB|Port A|Unchanged|
||Port B|Clear|
|GPIOA and<br>GPIOB|Port A|Unchanged|
||Port B|Unchanged|
||Both Port A<br>and Port B|Clear|
## 1.7.2 IOC FROM PIN CHANGE
If enabled, the MCP23X18 will generate an interrupt if a mismatch condition exists between the current port value and the previous port value. Only IOC enabled pins will be compared. See GPINTEN and INTCON registers.
## 1.7.3 IOC FROM REGISTER DEFAULT
If enabled, the MCP23X18 will generate an interrupt if a mismatch occurs between the DEFVAL register and the port. Only IOC enabled pins will be compared. See GPINTEN, INTCON, and DEFVAL registers.
## 1.7.4 INTERRUPT OPERATION
The INTn interrupt output can be configured as “active low”, “active high”, or “open drain” via the IOCON register.
Only those pins that are configured as an input (IODIR register) with interrupt-on-change (IOC) enabled (GPINTEN register) can cause an interrupt. Pins defined as an output have no effect on the interrupt output pin.
Input change activity on a port input pin that is enabled for IOC will generate an internal device interrupt and the device will capture the value of the port and copy it into INTCAP.
The first interrupt event will cause the port contents to be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of INTCAP or GPIO.
## 1.7.5 CLEARING INTERRUPTS
The interrupt will remain active until the INTCAP or GPIO register is read (depending on IOCON.INTCC). Writing to these registers will not affect the interrupt. The interrupt condition will be cleared after the LSb of the data is clocked out during a Read command of GPIO or INTCAP (depending on IOCON.INTCC).
**Note:** Assuming IOCON.INTCC = 0 (INT cleared on GPIO read): The value in INTCAP can be lost if GPIO is read before INTCAP while another IOC is pending. After reading GPIO, the interrupt will clear and then set due to the pending IOC, causing the INTCAP register to update.
* Port n = GPIOn or INTCAPn
DS22103A-page 30
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## 1.7.6 INTERRUPT CONDITIONS
There are two possible configurations to cause interrupts (configured via INTCON):
1. Pins configured for **interrupt-on-pin-change** will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs. For example, an interrupt occurs by an input changing from `1` to `0` . The new initial state for the pin is a logic `0` .
2. Pins configured for **interrupt-on-change from register value** will cause an interrupt to occur if the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the INTAP or GPIO is read.
See Figure 1-11 and Figure 1-12 for more information on interrupt operations.
## **FIGURE 1-11: INTERRUPT-ON-PINCHANGE**
**==> picture [184 x 97] intentionally omitted <==**
**----- Start of picture text -----**<br>
GPx<br>INT ACTIVE ACTIVE<br>Port value Read GPIO Port value<br>is captured or INTCAP is captured<br>into INTCAP into INTCAP<br>**----- End of picture text -----**<br>
**FIGURE 1-12: INTERRUPT-ON-CHANGE FROM REGISTER DEFAULT**
**==> picture [196 x 205] intentionally omitted <==**
**----- Start of picture text -----**<br>
DEFVAL<br>GP: 7 6 5 4 3 2 1 0<br>X X X X X 1 X X<br>GP2<br>INT ACTIVE AC T IVE<br>Port value<br>is captured Read GPIO<br>into INTCAP or INTCAP<br>(INT clears only if interrupt<br>condition does not exist.)<br>**----- End of picture text -----**<br>
DS22103A-page 31
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **NOTES:**
DS22103A-page 32
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **2.0 ELECTRICAL CHARACTERISTICS**
## **Absolute Maximum Ratings[(†)]**
|Ambient temperature under bias.............................................................................................................-40°C to +125°C|
|---|
|Storage temperature .............................................................................................................................. -65°C to +150°C|
|Voltage on VDDwith respect to VSS......................................................................................................... -0.3V to +7.0V|
|Voltage on RESET<br>with respect to VSS..................................................................................................... -0.3V to +14V|
|Voltage on all other pins with respect to VSS(except VDDand GPIOA/B) ...................................... -0.6V to (VDD+ 0.6V)|
|Voltage on GPIO Pins: ................................................................................................................................. -0.6V to 5.5V|
|Total power dissipation (Note 1)...........................................................................................................................700 mW|
|Maximum current out of VSSpin ...........................................................................................................................400 mA|
|Maximum current into VDDpin ..............................................................................................................................125 mA|
|Input clamp current, IIK(VI< 0 or VI> VDD)......................................................................................................................±20 mA|
|Output clamp current, IOK(VO< 0 or VO> VDD)..............................................................................................................±20 mA|
|Maximum output current sunk by any Output pin....................................................................................................25 mA|
|Maximum output current sunk by any Output pin (VDD= 1.8V) ..............................................................................10 mA|
|Maximum output current sourced by any Output pin ..............................................................................................25 mA|
|Maximum output current sourced by any Output pin (VDD= 1.8V).........................................................................10 mA|
|**Note:**<br>Power dissipation is calculated as follows:|
|Pdis = VDDx {IDD-∑IOH} +∑{(VDD-VOH) x IOH} +∑(VOLx IOL)|
|† **NOTICE:**Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the|
|device. This is a stress rating only and functional operation of the device at those or any other conditions above those|
|indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for|
|extendedperiods mayaffect device reliability.|
DS22103A-page 33
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## **2.1 DC CHARACTERISTICS**
|**DC Characteristics**|**DC Characteristics**|**Operating Conditions (unless otherwise indicated):**<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C|**Operating Conditions (unless otherwise indicated):**<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C|**Operating Conditions (unless otherwise indicated):**<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C|**Operating Conditions (unless otherwise indicated):**<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C|**Operating Conditions (unless otherwise indicated):**<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C|**Operating Conditions (unless otherwise indicated):**<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C|
|---|---|---|---|---|---|---|---|
|**Param**<br>**No.**|**Characteristic**|**Sym**|**Min**|**Typ( 2)**|**Max**|**Units**|**Conditions**|
|D001|SupplyVoltage|VDD|1.8|—|5.5|V||
|D002|VDDStart Voltage to<br>Ensure Power-on<br>Reset|VPOR|—|VSS|—|V||
|D003|VDDRise Rate to<br>Ensure Power-on<br>Reset|SVDD|0.05|—|—|V/ms|Design guidance only.<br>Not tested.|
|D004|SupplyCurrent|IDD|—|—|1|mA|SCL/SCK = 1 MHz|
|D005|Standby (Idle) current|IDDS|—|—|1|µA|–40°C≤TA ≤+85°C|
||||—|—|6|µA|+85°C≤TA ≤+125°C|
||**Input Low-Voltage**|||||||
|D031|CS<br>, GPIO,SCL/SCK,<br>SDA, SI, RESET|VIL|VSS|—|0.2 VDD|V||
||**Input High-Voltage**|||||||
|D041|CS<br>,SCL/SCK, SDA,<br>SI, RESET|VIH|0.8 VDD|—|VDD|V||
||GPIO|VIH|0.8 VDD|—|5.5|V||
||**Input Leakage Current**|||||||
|D060|I/Oportpins|IIL|—|—|±1|µA|VSS ≤VPIN ≤VDD,|
||**Output Leakage Current**|||||||
|D065|I/Oportpins|ILO|—|—|±1|µA|VSS ≤VPIN ≤VDD,|
|D070|GPIO internal pull-up<br>current|IPU|—|220|—|µA|VDD= 5V, GP Pins = VSS<br>Note 1|
||**Output Low-Voltage**|||||||
|D080|GPIO<br>INT<br>SO, SDA<br>SDA|VOL|—<br>—<br>—<br>—|—<br>—<br>—<br>—|0.6<br>0.6<br>0.6<br>0.8|V<br>V<br>V<br>V|IOL= 8.5 mA, VDD= 4.5V<br>(open-drain)<br>IOL= 1.6 mA, VDD= 4.5V<br>IOL= 3.0 mA, VDD= 1.8V<br>IOL= 3.0 mA, VDD= 4.5V|
||**Output High-Voltage**|||||||
|D090|INT, SO|VOH|VDD– 0.7<br>VDD– 0.7|—<br>—|—<br>—|V|IOH= -3.0 mA, VDD= 4.5V|
||||||||IOH= -400µA, VDD= 1.8V|
||**Capacitive Loading Specs on Output Pins**|||||||
|D101<br>D102|GPIO, SO, INT<br>SDA|CIO<br>CB|—<br>—|—<br>—|50<br>400|pF<br>pF||
**Note 1:** This parameter is characterized, not 100% tested.
- **2:** Data in the Typical (“Typ”) column is at 5V, +25°C unless otherwise stated.
DS22103A-page 34
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **2.2 AC CHARACTERISTICS**
## **FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS**
**==> picture [286 x 102] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>Pin<br>1 kΩ<br>SCL and<br>50 pF<br>SDA pin<br>MCP23018<br>135 pF<br>**----- End of picture text -----**<br>
## **FIGURE 2-2: RESET AND DEVICE RESET TIMER TIMING**
**==> picture [444 x 172] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>RESET<br>30 32<br>31<br>Internal<br>RESET<br>34<br>Output pin<br>**----- End of picture text -----**<br>
## **TABLE 2-1: RESET AND DEVICE RESET TIMER REQUIREMENTS**
|**AC Characteristics**|**AC Characteristics**|Standard Operating Conditions (unless otherwise specified)<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Standard Operating Conditions (unless otherwise specified)<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Standard Operating Conditions (unless otherwise specified)<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Standard Operating Conditions (unless otherwise specified)<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Standard Operating Conditions (unless otherwise specified)<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Standard Operating Conditions (unless otherwise specified)<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|
|---|---|---|---|---|---|---|---|
|**Parameter**<br>**No.**|**Sym**|**Characteristic**|**Min**|**Typ( 2)**|**Max**|**Units**|**Conditions**|
|30|TRSTL|RESET<br>Pulse Width (low)|1|—|—|µs|VDD= 5.0V|
|32|THLD|Device active after reset high|—|0|—|µs|VDD= 5.0V|
|31|TPOR|POR at device power up|—|20|—|µs|VDD= 5.0V|
|34|TioZ|Output Hi-impedance from<br>RESET<br>Low|—|—|1|µs||
**Note 1:** This parameter is characterized, not 100% tested.
- **2:** Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated.
DS22103A-page 35
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## **TABLE 2-2: GP AND INT PINS**
|**TABLE 2-2:**<br>**GP AND INT PINS**|**TABLE 2-2:**<br>**GP AND INT PINS**|**TABLE 2-2:**<br>**GP AND INT PINS**|**TABLE 2-2:**<br>**GP AND INT PINS**|**TABLE 2-2:**<br>**GP AND INT PINS**|**TABLE 2-2:**<br>**GP AND INT PINS**|**TABLE 2-2:**<br>**GP AND INT PINS**|**TABLE 2-2:**<br>**GP AND INT PINS**|
|---|---|---|---|---|---|---|---|
|||||||||
|**AC Characteristics** Standard Operating Conditions (unless otherwise specified)<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.||||||||
|**Parameter**<br>**No.**|**Sym**|**Characteristic**|**Min**|**Typ( 2)**|**Max**|**Units**|**Conditions**|
|50|tGPOV|Serial data to output valid|—|—|500|ns||
|51|tINTD|Interrupt pin disable time|—|—|600|ns||
|52|tGPIV|GP input change to register valid|—|450|—|ns|**Note 1**|
|53|tGPINT|IOC event to INT active|—|—|600|ns||
|54|tGLITCH|Glitch filter on GP pins|—|—|50|ns|**Note 1**|
**Note 1:** This parameter is characterized, not 100% tested. **2:** Data in the Typical (“Typ”) column is at 5V, 25°C, unless otherwise stated.
## **FIGURE 2-3: GPIO AND INT TIMING**
**==> picture [417 x 262] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCL<br>SDA<br>In D1 D0<br>LSb of data byt e zero<br>during a write o r read<br>command, depe n ding<br>on parameter 50<br>GPn<br>Output<br>Pin<br>51<br>INT<br>Pin<br>INT pin active INT pin<br>inactive<br>53<br>GPn<br>Input<br>Pin<br>52<br>Register<br>Loaded<br>**----- End of picture text -----**<br>
DS22103A-page 36
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **TABLE 2-3: HARDWARE ADDRESS LATCH TIMING**
|**TABLE 2-3:**<br>**HARDWARE ADDRESS LATCH TIMING**|**TABLE 2-3:**<br>**HARDWARE ADDRESS LATCH TIMING**|**TABLE 2-3:**<br>**HARDWARE ADDRESS LATCH TIMING**|**TABLE 2-3:**<br>**HARDWARE ADDRESS LATCH TIMING**|**TABLE 2-3:**<br>**HARDWARE ADDRESS LATCH TIMING**|**TABLE 2-3:**<br>**HARDWARE ADDRESS LATCH TIMING**|**TABLE 2-3:**<br>**HARDWARE ADDRESS LATCH TIMING**|**TABLE 2-3:**<br>**HARDWARE ADDRESS LATCH TIMING**|
|---|---|---|---|---|---|---|---|
|||||||||
|**AC Characteristics**<br>Standard Operating Conditions (unless otherwise specified)<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.||||||||
|**Parameter**<br>**No.**|**Sym**|**Characteristic**|**Min**<br>|**Typ( 2)**|**Max**|**Units**|**Conditions**|
|40|tADEN|Time from VDDstable after<br>POR to ADC enable|—|0|—|µs|Note 1|
|41|tADDRLAT|Time from ADC enable to<br>address decode and latch|—|50|—|ns|Note 1|
|42|tADDIS|Time from raising edge of serial<br>clock to ADC disable|—|10|—|ns|Note 1|
**Note 1:** This parameter is characterized, not 100% tested.
**2:** Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated..
## **FIGURE 2-4: HARDWARE ADDRESS LATCH TIMING**
**==> picture [442 x 170] intentionally omitted <==**
**----- Start of picture text -----**<br>
40<br>VDD<br>41<br>adc_en<br>i2c_addr[2:0]<br>42<br>SCL<br>**----- End of picture text -----**<br>
DS22103A-page 37
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## **FIGURE 2-5: I[2] C BUS START/STOP BITS TIMING**
**==> picture [455 x 123] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCL<br>91 93<br>90 92<br>SDA<br>START STOP<br>Condition Condition<br>Note 1: Refer to Figure 2-1 for load conditions.<br>**----- End of picture text -----**<br>
## **FIGURE 2-6: I[2] C BUS DATA TIMING**
**==> picture [399 x 121] intentionally omitted <==**
**----- Start of picture text -----**<br>
10 3 100 102<br>10 1<br>SCL<br>90 106<br>91 107 92<br>SDA<br>In<br>109 109 110<br>SDA<br>Out<br>Note 1: Refer to Figure 2-1 for load conditions.<br>**----- End of picture text -----**<br>
DS22103A-page 38
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **TABLE 2-4: I[2] C BUS DATA REQUIREMENTS (SLAVE MODE)**
|**I2C™ AC Characteristics**|**I2C™ AC Characteristics**|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|
|---|---|---|---|---|---|---|---|
|**Param**<br>**No.**|<br>**Characteristic**|**Sym**|**Min**|**Typ**|**Max**|**Units**|**Conditions**|
|100|Clock High Time:<br>100 kHz mode|THIGH||||||
||||4.0|—|—|µs|1.8V – 5.5V|
||400 kHz mode||0.6|—|—|µs|1.8V – 5.5V|
||3.4 MHz mode||0.06|—|—|µs|2.7V – 5.5V|
|101|Clock Low Time:|TLOW||||||
||100 kHz mode||4.7|—|—|µs|1.8V – 5.5V|
||400 kHz mode||1.3|—|—|µs|1.8V – 5.5V|
||3.4 MHz mode||0.16|—|—|µs|2.7V – 5.5V|
|102|SDA and SCL Rise Time:|TR<br>**(Note 1)**||||||
||100 kHz mode||—|—|1000|ns|1.8V – 5.5V|
||400 kHz mode||20 + 0.1 CB**(2)**|—|300|ns|1.8V – 5.5V|
||3.4 MHz mode||10|—|80|ns|2.7V – 5.5V|
|103|SDA and SCL Fall Time:|TF<br>**(Note 1)**||||||
||100 kHz mode||—|—|300|ns|1.8V – 5.5V|
||400 kHz mode||20 + 0.1 CB**(2)**|—|300|ns|1.8V – 5.5V|
||3.4 MHz mode||10|—|80|ns|2.7V – 5.5V|
|90|START Condition SetupTime:|TSU:STA||||||
||100 kHz mode||4.7|—|—|µs|1.8V – 5.5V|
||400 kHz mode||0.6|—|—|µs|1.8V – 5.5V|
||3.4 MHz mode||0.16|—|—|µs|2.7V – 5.5V|
|91|START Condition Hold Time:|THD:STA||||||
||100 kHz mode||4.0|—|—|µs|1.8V – 5.5V|
||400 kHz mode||0.6|—|—|µs|1.8V – 5.5V|
||3.4 MHz mode||0.16|—|—|µs|2.7V – 5.5V|
|106|Data Input Hold Time:|THD:DAT||||||
||100 kHz mode||0|—|3.45|µs|1.8V – 5.5V|
||400 kHz mode||0|—|0.9|µs|1.8V – 5.5V|
||3.4 MHz mode||0|—|0.07|µs|2.7V – 5.5V|
|107|Data Input SetupTime:|TSU:DAT||||||
||100 kHz mode||250|—|—|ns|1.8V – 5.5V|
||400 kHz mode||100|—|—|ns|1.8V – 5.5V|
||3.4 MHz mode||0.01|—|—|µs|2.7V – 5.5V|
|92|STOP Condition SetupTime:|TSU:STO||||||
||100 kHz mode||4.0|—|—|µs|1.8V – 5.5V|
||400 kHz mode||0.6|—|—|µs|2.7V – 5.5V|
||3.4 MHz mode||0.16|—|—|µs|4.5V – 5.5V|
**Note 1:** This parameter is characterized, not 100% tested.
- **2:** CB is specified from 10 to 400 (pF).
- **3:** This parameter is not applicable in high-speed mode (3.4 MHz).
DS22103A-page 39
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## **TABLE 2-4: I[2] C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)**
|**I2C™ AC Characteristics**|**I2C™ AC Characteristics**|**I2C™ AC Characteristics**|**I2C™ AC Characteristics**|**I2C™ AC Characteristics**|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C<br>RPU (SCL, SDA)= 1 kΩ, CL (SCL, SDA)= 135pF.|||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Param**<br>**No.**|<br>**Characteristic**||||**Sym**|**Min**|||**Typ**|**Max**|**Units**|||||**Conditions**||
|109|Output Valid From Clock:||||TAA|||||||||||||
||100 kHz mode|||||—|||—|3.45|µs|||1.8V –||5.5V||
||400 kHz mode|||||—|||—|0.9|µs|||1.8V –||5.5V||
||3.4 MHz mode|||||—|||—|0.18|µs|||2.7V –||5.5V||
|110|Bus Free Time:||||TBUF<br>**(NOTE 3)**|||||||||||||
||100 kHz mode|||||4.7|||—|—|µs|||1.8V –||5.5V||
||400 kHz mode|||||1.3|||—|—|µs|||1.8V –||5.5V||
||3.4 MHz mode|||||N/A|||—|N/A|µs|||2.7V –||5.5V||
||Bus Capacitive Loading:||||CB<br>**(NOTE 2)**|||||||||||||
||100 kHz and 400 kHz|||||—|||—|400|pF|||**(Note**||**1)**||
||3.4 MHz|||||—|||—|100|pF|||**(Note**||**1)**||
||Input Filter Spike<br>Suppression:(SDA and SCL)||||TSP|||||||||||||
||100 kHz and 400 kHz|||||—|||—|50|ns|||**(Note**||**1)**||
||3.4 MHz|||||—|||—|10|ns|||**(Note**||**1)**||
|**FIGURE 2-7:**<br>**SPI INPUT TIMING**<br>**Note 1:**<br>This parameter is characterized, not 100% tested.<br>**2:**<br>CBis specified from 10 to 400 (pF).<br>**3:**<br>This parameter is not applicable in high-speed mode (3.4 MHz).||||||||||||||||||
|CS<br>SCK<br>SI<br>SO||1<br>5<br>4<br>6<br>MSB in<br>high impedance<br>Mode 1,1<br>Mode 0,0||||||7|||||||3||11|
|||||||||||||||||||
||||||||||||||||10|||
||||||||||2<br>LSB in|||||||||
|||||||||||||||||||
|||||||||||||||||||
|||||||||||||||||||
DS22103A-page 40
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **FIGURE 2-8: SPI OUTPUT TIMING**
**==> picture [443 x 147] intentionally omitted <==**
**----- Start of picture text -----**<br>
CS<br>2<br>8 9<br>SCK Mode 1,1<br>Mode 0,0<br>12<br>14<br>13<br>SO<br>MSB out LSB out<br>don’t care<br>SI<br>**----- End of picture text -----**<br>
DS22103A-page 41
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
## **TABLE 2-5: SPI INTERFACE AC CHARACTERISTICS**
|**SPI Interface AC Characteristics**|**SPI Interface AC Characteristics**|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|Operating Conditions (unless otherwise indicated):<br>1.8V≤VDD ≤5.5V at -40°C≤TA ≤+125°C.|
|---|---|---|---|---|---|---|---|
|**Param**<br>**No.**|**Characteristic**|**Sym**|**Min**|**Typ**|**Max**|**Units**|**Conditions**|
||Clock Frequency|FCLK|—|—|10|MHz|1.8V – 5.5V|
|1|CS<br>Setup Time|TCSS|50|—|—|ns||
|2|CS<br>Hold Time|TCSH|50|—|—|ns|1.8V – 5.5V|
|3|CS<br>Disable Time|TCSD|50|—|—|ns|1.8V – 5.5V|
|4|Data Setup Time|TSU|10|—|—|ns|1.8V – 5.5V|
|5|Data Hold Time|THD|10|—|—|ns|1.8V – 5.5V|
|6|CLK Rise Time|TR|—|—|2|µs|**Note 1**|
|7|CLK Fall Time|TF|—|—|2|µs|**Note 1**|
|8|Clock High Time|THI|45|—|—|ns|1.8V – 5.5V|
|9|Clock Low Time|TLO|45|—|—|ns|1.8V – 5.5V|
|10|Clock Delay Time|TCLD|50|—|—|ns||
|11|Clock Enable Time|TCLE|50|—|—|ns||
|12|Output Valid from Clock<br>Low|TV|—|—|45|ns|1.8V – 5.5V|
|13|Output Hold Time|THO|0|—|—|ns||
|14|Output Disable Time|TDIS|—|—|100|ns||
|**Note 1:**<br>This parameter is characterized, not 100% tested.||||||||
**Note 1:** This parameter is characterized, not 100% tested.
**FIGURE 2-9: TYPICAL PERFORMANCE CURVE FOR SPI TV SPECIFICATION (PARAM #12)**
**==> picture [424 x 261] intentionally omitted <==**
**----- Start of picture text -----**<br>
TV vs VDD<br>40<br>35<br>°<br>T = +125 C<br>30<br>25<br>T = -40°C T = +85°C<br>20<br>15<br>10<br>T = +25°C<br>5<br>0<br>1.5 2 2.5 3 3.5 4 4.5 5 5.5<br>VDD (V)<br> (ns)<br>V<br>T<br>**----- End of picture text -----**<br>
DS22103A-page 42
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **3.0 PACKAGING INFORMATION**
## **3.1 Package Marking Information**
24-Lead QFN
## Example
**==> picture [34 x 36] intentionally omitted <==**
**----- Start of picture text -----**<br>
XXXXX<br>XXXXXX<br>XXXXXX<br>YWWNNN<br>**----- End of picture text -----**<br>
**==> picture [33 x 37] intentionally omitted <==**
**----- Start of picture text -----**<br>
23018<br>E/MJ^^ e3<br>0838<br>256<br>**----- End of picture text -----**<br>
## 24-Lead SSOP **(MCP23018 only)**
## Example:
**==> picture [65 x 31] intentionally omitted <==**
**----- Start of picture text -----**<br>
XXXXXXXXXXXX<br>XXXXXXXXXXXX<br>YYWWNNN<br>**----- End of picture text -----**<br>
**==> picture [45 x 32] intentionally omitted <==**
**----- Start of picture text -----**<br>
MCP23018<br>E/SS^^ e3<br>0838256<br>**----- End of picture text -----**<br>
**Legend:** XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) ***** This package is Pb-free. The Pb-free JEDEC designator ( ) e3 can be found on the outer packaging for this package. **Note** : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
DS22103A-page 43
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **Package Marking Information (Continued)**
28-Lead SPDIP (300 mil)
```
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
```
## 28-Lead SOIC (300 mil)
```
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
```
Example:
Example:
**`MCP23018`** `E/SP^^` e3 `0838256`
**`MCP23018`** `E/SO^^` e3 `YYWW NNN`
DS22103A-page 44
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **24-Lead Plastic Quad Flat, No Lead Package (MJ) – 4x4x0.9 mm Body [QFN]**
**==> picture [462 x 27] intentionally omitted <==**
**----- Start of picture text -----**<br>
Note: For the most current package drawings, please see the Microchip Packaging Specification located at<br>http://www.microchip.com/packaging<br>**----- End of picture text -----**<br>
**==> picture [449 x 541] intentionally omitted <==**
DS22103A-page 45
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
DS22103A-page 46
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
**==> picture [367 x 270] intentionally omitted <==**
**----- Start of picture text -----**<br>
D<br>N<br>E<br>— . |<br>SS \ ‘SS ‘. E1 St , as<br>S\ S \ | SO , ees SV<br>OTTO a5 is<br>1 2<br>b<br>NOTE 1<br>e<br>c<br>φ<br>A A2<br>STL<br>| Lon, r<br>A1 J 4 L1 AL L<br>**----- End of picture text -----**<br>
DS22103A-page 47
© 2008 Microchip Technology Inc.
## **MCP23018/MCP23S18**
**==> picture [415 x 229] intentionally omitted <==**
**----- Start of picture text -----**<br>
N<br>Pe<br>NOTE 1<br>[ 4<br>E1<br>j<br>| at<br>1 2 3<br>s e aay ||<br>na ate | |<br>D Rey |<br>[rv fh | |<br>E<br>A A2<br>L<br>c<br>A1 C b1 TT | 1<br>b e eB<br>p alo JE ’ bo<br>**----- End of picture text -----**<br>
DS22103A-page 48
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
**==> picture [369 x 226] intentionally omitted <==**
**----- Start of picture text -----**<br>
D<br>N<br>TE) TE Py) PH ft<br>E<br>E1<br>NOTE 1<br>1 2 3<br>e<br>b<br>h<br>α h<br>A icn A | A2 φ c<br>{i tera (atalatatalate(utnln late a<br>L<br>A1 | | L1 seI β<br>**----- End of picture text -----**<br>
DS22103A-page 49
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **NOTES:**
DS22103A-page 50
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **APPENDIX A: REVISION HISTORY**
## **Revision A (September 2008)**
- Original Release of this Document.
DS22103A-page 51
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **NOTES:**
DS22103A-page 52
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **PRODUCT IDENTIFICATION SYSTEM**
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
|Device<br>MCP23018:<br>16-Bit I/O Expander w/ I2C™ Inter-<br>face<br>MCP23018T:<br>16-Bit I/O Expander w/ I2C Interface<br>(Tape and Reel)<br>MCP23S18:<br>16-Bit I/O Expander w/ SPI Interface<br>MCP23S18T:<br>16-Bit I/O Expander w/ SPI Interface<br>(Tape and Reel)<br>Temperature<br>Range<br>E<br>= -40°C to +125°C (Extended) *<br>Package<br>MJ<br>= Plastic Quad Flat, No Lead Package<br>(4x4x0.9 mm Body), 24-Lead<br>SP<br>= Skinny Plastic DIP (300 mil Body), 28-Lead<br>SO<br>= Plastic SOIC (300 mil Body), 28-Lead<br>SS<br>= SSOP, (209 mil Body, 5.30 mm), 24-Lead<br>**PART NO.**<br>**X**<br>**/XX**<br>**Package**<br>**Temperature**<br>**Range**<br>**Device**<br>–|**Examples:**<br>a)<br>MCP23018-E/SP:<br>Extended Temp.,<br>28LD SPDIP package.<br>b)<br>MCP23018-E/SO:<br>Extended Temp.,<br>28LD SOIC package.<br>c)<br>MCP23018T-E/SO: Tape and Reel,<br>Extended Temp.,<br>28LD SOIC package.<br>d)<br>MCP23018-E/SS:<br>Extended Temp.,<br>24LD SSOP package.<br>e)<br>MCP23018T-E/SS: Tape and Reel,<br>Extended Temp.,<br>24LD SSOP package.<br>f)<br>MCP23018-E/MJ:<br>Extended Temp.,<br>24LD QFN package.<br>a)<br>MCP23S18-E/SP:<br>Extended Temp.,<br>28LD SPDIP package.<br>b)<br>MCP23S18-E/SO:<br>Extended Temp.,<br>28LD SOIC package.<br>c)<br>MCP23S18T-E/SO: Tape and Reel,<br>Extended Temp.,<br>28LD SOIC package.<br>d)<br>MCP23S18T-E/MJ: Tape and Reel,<br>Extended Temp.,<br>24LD QFN package.|
|---|---|
DS22103A-page 53
© 2008 Microchip Technology Inc.
**MCP23018/MCP23S18**
## **NOTES:**
DS22103A-page 54
© 2008 Microchip Technology Inc.
**Note the following details of the code protection feature on Microchip devices:**
- Microchip products meet the specification contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
- Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE **.** Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
## **Trademarks**
The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC[32] logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.
© 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
0 Printed on recycled paper.
_Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC[®] MCUs and dsPIC[®] DSCs, KEELOQ[®] code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified._
DS22103A-page 55
© 2008 Microchip Technology Inc.
## **WORLDWIDE SALES AND SERVICE**
## **AMERICAS**
**Corporate Office** 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com
**Atlanta** Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455
**Boston** Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088
**Chicago** Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075
**Dallas** Addison, TX Tel: 972-818-7423 Fax: 972-818-2924
**Detroit** Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260
**Kokomo** Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387
**Los Angeles** Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608
**Santa Clara** Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445
**Toronto** Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
## **ASIA/PACIFIC**
**Asia Pacific Office** Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
**Australia - Sydney** Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
**China - Beijing** Tel: 86-10-8528-2100 Fax: 86-10-8528-2104
**China - Chengdu** Tel: 86-28-8665-5511 Fax: 86-28-8665-7889
**China - Hong Kong SAR** Tel: 852-2401-1200 Fax: 852-2401-3431
**China - Nanjing** Tel: 86-25-8473-2460 Fax: 86-25-8473-2470
**China - Qingdao** Tel: 86-532-8502-7355 Fax: 86-532-8502-7205
**China - Shanghai** Tel: 86-21-5407-5533 Fax: 86-21-5407-5066
**China - Shenyang** Tel: 86-24-2334-2829 Fax: 86-24-2334-2393
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**China - Wuhan** Tel: 86-27-5980-5300 Fax: 86-27-5980-5118
**China - Xiamen** Tel: 86-592-2388138 Fax: 86-592-2388130
**China - Xian** Tel: 86-29-8833-7252 Fax: 86-29-8833-7256
**China - Zhuhai** Tel: 86-756-3210040 Fax: 86-756-3210049
## **ASIA/PACIFIC**
**India - Bangalore** Tel: 91-80-4182-8400 Fax: 91-80-4182-8422
**India - New Delhi** Tel: 91-11-4160-8631 Fax: 91-11-4160-8632
**India - Pune** Tel: 91-20-2566-1512 Fax: 91-20-2566-1513
**Japan - Yokohama** Tel: 81-45-471- 6166 Fax: 81-45-471-6122
**Korea - Daegu** Tel: 82-53-744-4301 Fax: 82-53-744-4302
**Korea - Seoul** Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934
**Malaysia - Kuala Lumpur** Tel: 60-3-6201-9857 Fax: 60-3-6201-9859
**Malaysia - Penang** Tel: 60-4-227-8870 Fax: 60-4-227-4068
**Philippines - Manila** Tel: 63-2-634-9065 Fax: 63-2-634-9069
**Singapore** Tel: 65-6334-8870 Fax: 65-6334-8850
**Taiwan - Hsin Chu** Tel: 886-3-572-9526 Fax: 886-3-572-6459
**Taiwan - Kaohsiung** Tel: 886-7-536-4818 Fax: 886-7-536-4803
**Taiwan - Taipei** Tel: 886-2-2500-6610 Fax: 886-2-2508-0102
**Thailand - Bangkok** Tel: 66-2-694-1351 Fax: 66-2-694-1350
## **EUROPE**
**Austria - Wels** Tel: 43-7242-2244-39 Fax: 43-7242-2244-393
**Denmark - Copenhagen** Tel: 45-4450-2828 Fax: 45-4485-2829
**France - Paris** Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
**Germany - Munich** Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
**Italy - Milan** Tel: 39-0331-742611 Fax: 39-0331-466781
**Netherlands - Drunen** Tel: 31-416-690399 Fax: 31-416-690340
**Spain - Madrid** Tel: 34-91-708-08-90 Fax: 34-91-708-08-91
**UK - Wokingham** Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/02/08
DS22103A-page 56
© 2008 Microchip Technology Inc.
Updated at February 9, 2023
Microchip Technology Inc. is a leading global provider of smart, connected, and secure embedded control solutions. Known for enabling engineers to design with confidence, the company delivers a comprehensive product portfolio that reduces total system costs and accelerates time to market across the industrial, automotive, communications, and computing sectors. Our extensive selection of Microchip components highlights the manufacturer's strength in both discrete semiconductors and advanced wireless connectivity. We carry a robust lineup of highly efficient single MOSFETs and Schottky diodes tailored for demanding power management and switching applications. Alongside these essential discretes, engineers can source a wide array of ready-to-use networking modules, prominently featuring Bluetooth and WLAN adapters that streamline the development of modern IoT and connected devices. Rounding out the offering is a diverse range of Microchip integrated circuits and specialized components. This includes versatile I/O expanders for simplified system integration, precision timing solutions such as MEMS oscillators and pulse generators, as well as AC/DC LED driver ICs and sub-2.4GHz RF transceivers. Backed by Microchip's renowned commitment to exceptional quality and reliable performance, these components provide scalable, dependable building blocks for complex electronic designs.
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