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MCP23S17T-E/ML
I/O Expander, 16bit, 10 MHz, SPI, 1.8 V, 5.5 V, QFN
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: MICROCHIP
- Product type: I/O Expanders
- No. of Pins: 28Pins
- No. of I/O's: 16I/O's
- Bus Frequency: 10MHz
- IC Interface Type: SPI
- Chip Configuration: 16bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 1.8V
- Interface Case Style: QFN
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 1.69 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **MCP23017/MCP23S17** ## **16-Bit I/O Expander with Serial Interface** ## **Features** - 16-Bit Remote Bidirectional I/O Port: - I/O pins default to input - High-Speed I[2] C Interface ( **MCP23017** ): - 100 kHz - 400 kHz - 1.7 MHz - High-Speed SPI Interface ( **MCP23S17** ): - 10 MHz (maximum) - Three Hardware Address Pins to Allow Up to Eight Devices On the Bus - Configurable Interrupt Output Pins: - Configurable as active-high, active-low or open-drain - INTA and INTB Can Be Configured to Operate Independently or Together - Configurable Interrupt Source: - Interrupt-on-change from configured register defaults or pin changes - Polarity Inversion Register to Configure the Polarity of the Input Port Data - External Reset Input - Low Standby Current: 1 µA (max.) - Operating Voltage: - 1.8V to 5.5V @ -40°C to +85°C - 2.7V to 5.5V @ -40°C to +85°C - 4.5V to 5.5V @ -40°C to +125°C ## **Packages** - 28-pin QFN, 6 x 6 mm Body - 28-pin SOIC, Wide, 7.50 mm Body - 28-pin SPDIP, 300 mil Body - 28-pin SSOP, 5.30 mm Body ## **Package Types** ## **MCP23017** ## **MCP23S17** |GPB0<br>GPB1<br>GPB2|||• 1<br>2<br>3|28<br>27<br>26||||GPA7<br>GPA6<br>GPA5|| |---|---|---|---|---|---|---|---|---|---| |GPB3<br>GPB4|||4<br>5|25<br>24||||GPA4<br>GPA3|| |NC<br>NC<br>GPB5<br>GPB6<br>GPB7<br>SCK<br>VDD<br>VSS<br>SDA|||6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|23<br>22<br>21<br>20<br>19<br>18<br>17<br>16<br>15||||INTA<br>GPA2<br>GPA1<br>GPA0<br>A2<br>A1<br>A0<br>INTB<br>RESET|**SPDIP**<br>**SSOP**<br>**SOIC**| |GPB0|||||• 1||28||GPA7|||||||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |GPB0<br>GPB1<br>GPB2<br>GPB3<br>GPB4|||||• 1<br>2<br>3<br>4<br>5||28<br>27<br>26<br>25<br>24||GPA7<br>GPA6<br>GPA5<br>GPA4<br>GPA3||GPB0<br>GPB1<br>GPB2<br>GPB3<br>GPB4|||• 1<br>2<br>3<br>4<br>5|28<br>27<br>26<br>25<br>24|||GPA7<br>GPA6<br>GPA5<br>GPA4<br>GPA3| |NC<br>NC<br>GPB5<br>GPB6<br>GPB7<br>SCK<br>VDD<br>VSS<br>SDA|||||6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14||23<br>22<br>21<br>20<br>19<br>18<br>17<br>16<br>15||INTA<br>GPA2<br>GPA1<br>GPA0<br>A2<br>A1<br>A0<br>INTB<br>RESET|**SPDIP**<br>**SSOP**<br>**SOIC**|SO<br>CS<br>GPB5<br>GPB6<br>GPB7<br>SCK<br>VDD<br>VSS<br>SI|||6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|23<br>22<br>21<br>20<br>19<br>18<br>17<br>16<br>15|||INTA<br>GPA2<br>GPA1<br>GPA0<br>A2<br>A1<br>A0<br>INTB<br>RESET| ||||||GPB3<br>GPB2<br>GPB1<br>GPB0<br>GPA7<br>GPA6<br>GPA5|||||||||GPB3<br>GPB2<br>GPB1<br>GPB0<br>GPA7<br>GPA6<br>GPA5||||| ||||||peeadae|||||||||phen||||| |VSS<br>NC<br>VDD<br>GPB5<br>GPB6<br>GPB7<br>GPB4|||2<br>3<br>4<br>5<br>6<br>1<br>7||15<br>16<br>17<br>18<br>19<br>20<br>21<br>23<br>24<br>25<br>26<br>27<br>28<br>22<br>EP<br>29 *||||GPA4<br>GPA3<br>GPA2<br>GPA1<br>GPA0<br>INTB<br>INTA|**QFN**|VSS<br>CS<br>VDD<br>GPB5<br>GPB6<br>GPB7<br>GPB4||2<br>3<br>4<br>5<br>6<br>1<br>7|15<br>16<br>17<br>18<br>19<br>20<br>21<br>23<br>24<br>25<br>26<br>27<br>28<br>22<br>EP<br>29 *||||GPA4<br>GPA3<br>GPA2<br>GPA1<br>GPA0<br>INTB<br>INTA| ||||||1011<br>8 9<br>121314|||||||||1011<br>8 9<br>121314||||| ||||||SCK<br>SDA<br>NC<br>A0<br>A1<br>A2<br>RESET<br>~~a~~||||* Includes Exposed Thermal Pad; seeTable 2-1.|||||SI<br>SO<br>A0<br>A1<br>A2<br>RESET<br>SCK<br>payee||||| DS20001952C-page 1 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** ## **Functional Block Diagram** **==> picture [390 x 298] intentionally omitted <==** **----- Start of picture text -----**<br> MCP23S17<br>CS<br>SCK<br>SI<br>SPI<br>SO<br>MCP23017<br>GPB7<br>SCL Serializer/<br>GPB6<br>SDA I [2] C Deserializer<br>GPB5<br>GPB4<br>3 GPIO<br>GPB3<br>A2:A0 Decode<br>GPB2<br>RESET Control GPB1<br>INTA Interrupt 16 GPB0<br>INTB Logic GPA7<br>GPA6<br>8 GPA5<br>GPA4<br>GPIO GPA3<br>Configuration/ GPA2<br>Control GPA1<br>Registers GPA0<br>**----- End of picture text -----**<br> DS20001952C-page 2 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **1.0 ELECTRICAL CHARACTERISTICS** ## **Absolute Maximum Ratings †** Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature ...............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +5.5V Voltage on all other pins with respect to VSS (except VDD)............................................................. -0.6V to (VDD + 0.6V) Total power dissipation.........................................................................................................................................700 mW Maximum current out of VSS pin ...........................................................................................................................150 mA Maximum current into VDD pin ..............................................................................................................................125 mA Input clamp current, IIK (VI < 0 or VI > VDD)..........................................................................................................±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA Maximum output current sunk by any output pin ....................................................................................................25 mA Maximum output current sourced by any output pin ...............................................................................................25 mA ESD protection on all pins (HBM:MM) ..............................................................................................................4 kV:400V **† Notice** : Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DS20001952C-page 3 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** ## **1.1 DC Characteristics** ## **TABLE 1-1: DC CHARACTERISTICS** |**Electrical Specifications:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|**Electrical Specifications:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|**Electrical Specifications:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|**Electrical Specifications:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|**Electrical Specifications:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|**Electrical Specifications:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|**Electrical Specifications:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|**Electrical Specifications:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C| |---|---|---|---|---|---|---|---| |**Param.**<br>**No.**|**Characteristic**|**Sym.**|**Min.**|**Typ.(1)**|**Max.**|**Units**|**Conditions**| |D001|SupplyVoltage|VDD|1.8|—|5.5|V|| |D002|VDDStart Voltage to<br>ensure Power-on Reset|VPOR|—|VSS|—|V|| |D003|VDDRise Rate to ensure<br>Power-on Reset|SVDD|0.05|—|—|V/ms|Design guidance only.<br>Not tested.| |D004|SupplyCurrent|IDD|—|—|1|mA|SCL/SCK = 1 MHz| |D005|Standby current|IDDS8|—|—|1|µA|-40°CTA +85°C| ||||—|—|3|µA|4.5VVDD 5.5V<br>+85°CTA +125C<br>**(Note 1)**| |**Input Low Voltage**|||||||| |D030|A0, A1, A2(TTL buffer)|VIL|VSS|—|0.15 VDD|V|| |D031|CS<br>, GPIO,SCL/SCK,<br>SDA, RESET<br>(Schmitt Trigger)|VIL|VSS|—|0.2 VDD|V|| |**Input High Voltage**|||||||| |D040|A0, A1, A2(TTL buffer)|VIH|0.25 VDD+ 0.8|—|VDD|V|| |D041|CS<br>, GPIO,SCL/SCK,<br>SDA, RESET<br>(Schmitt Trigger)|VIH|0.8 VDD|—|VDD|V|For entire VDDrange| |**Input Leakage Current**|||||||| |D060|I/Oportpins|IIL|—|—|±1|µA|VSS VPIN VDD| |**Output Leakage Current**|||||||| |D065|I/Oportpins|ILO|—|—|±1|µA|VSS VPIN VDD| |D070|GPIO weak pull-up<br>current|IPU|40|75|115|µA|VDD= 5V<br>GPpins = VSS| |**Output Low-Voltage**|||||||| |D080|GPIO|VOL|—|—|0.6|V|IOL= 8.0 mA<br>VDD= 4.5V| ||INT|VOL|—|—|0.6|V|IOL= 1.6 mA<br>VDD= 4.5V| ||SO, SDA|VOL|—|—|0.6|V|IOL= 3.0 mA<br>VDD= 1.8V| ||SDA|VOL|—|—|0.8|V|IOL= 3.0 mA<br>VDD= 4.5V| |**Output High-Voltage**|||||||| |D090|GPIO, INT, SO|VOH|VDD– 0.7<br>VDD– 0.7|—<br>—|—<br>—|V|IOH= -3.0 mA<br>VDD= 4.5V| ||||||||IOH= -400 µA<br>VDD= 1.8V| |**Capacitive Loading Specs on Output Pins**|||||||| |D101|GPIO, SO, INT|CIO|—|—|50|pF|| |D102|SDA|CB|—|—|400|pF|| **Note 1:** This parameter is characterized, not 100% tested. DS20001952C-page 4 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **1.2 AC Characteristics** ## **FIGURE 1-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS** **==> picture [286 x 102] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>Pin<br>1 k<br>SCL and 50 pF<br>SDA pin<br>MCP23017<br>135 pF<br>**----- End of picture text -----**<br> ## **FIGURE 1-2: RESET AND DEVICE RESET TIMER TIMING** **==> picture [43 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>RESET<br>Internal<br>RESET<br>Output pin<br>**----- End of picture text -----**<br> **==> picture [255 x 107] intentionally omitted <==** **----- Start of picture text -----**<br> 30 32<br>34<br>**----- End of picture text -----**<br> ## **TABLE 1-2: DEVICE RESET SPECIFICATIONS** **AC Characteristics:** Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C |**TABLE 1-2:**<br>**DEVICE RESET SPECIFICATIONS**|**TABLE 1-2:**<br>**DEVICE RESET SPECIFICATIONS**|**TABLE 1-2:**<br>**DEVICE RESET SPECIFICATIONS**|**TABLE 1-2:**<br>**DEVICE RESET SPECIFICATIONS**|**TABLE 1-2:**<br>**DEVICE RESET SPECIFICATIONS**|**TABLE 1-2:**<br>**DEVICE RESET SPECIFICATIONS**|**TABLE 1-2:**<br>**DEVICE RESET SPECIFICATIONS**|**TABLE 1-2:**<br>**DEVICE RESET SPECIFICATIONS**| |---|---|---|---|---|---|---|---| |**AC Characteristics:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|||||||| |**Param.**<br>**No.**|**Characteristic**|**Sym.**|**Min.**|**Typ.(1)**|**Max.**|**Units**|**Conditions**| |30|RESET<br>Pulse Width<br>(Low)|TRSTL|1|—|—|µs|| |32|Device Active After Reset<br>high|THLD|—|0|—|ns|VDD= 5.0V| |34|Output High-Impedance<br>From RESET<br>Low|TIOZ|—|—|1|µs|| **Note 1:** This parameter is characterized, not 100% tested. DS20001952C-page 5 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** **FIGURE 1-3: I[2] C BUS START/STOP BITS TIMING** **==> picture [454 x 108] intentionally omitted <==** **----- Start of picture text -----**<br> SCL<br>91 93<br>90 92<br>SDA<br>Start Stop<br>Condition Condition<br>**----- End of picture text -----**<br> ## **FIGURE 1-4: I[2] C BUS DATA TIMING** **==> picture [396 x 109] intentionally omitted <==** **----- Start of picture text -----**<br> 103 100 102<br>101<br>SCL<br>90 106<br>91 107 92<br>SDA<br>In<br>109 109 110<br>SDA<br>Out<br>**----- End of picture text -----**<br> ## **TABLE 1-3: I[2] C BUS DATA REQUIREMENTS** **I[2] C Interface AC Characteristics:** Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C **,** RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF |**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS**| |---|---|---|---|---|---|---|---| |**I2C Interface AC Characteristics:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C**,**RPU(SCL,<br>SDA) = 1 k, CL(SCL, SDA) = 135 pF|||||||| |**Param.**<br>**No.**|**Characteristic**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**| |100|Clock High Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|THIGH|||||| ||||4.0|—|—|µs<br>|1.8V – 5.5V| ||||0.6|—|—|µs<br>|2.7V – 5.5V| ||||0.12|—|—|µs<br>|4.5V – 5.5V| |101|Clock Low Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|TLOW|||||| ||||4.7|—|—|µs<br>|1.8V – 5.5V| ||||1.3|—|—|µs<br>|2.7V – 5.5V| ||||0.32|—|—|µs<br>|4.5V – 5.5V| |102|SDA and SCL Rise Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|TR<br>**(1)**|||||| ||||—|—|1000|ns<br>|1.8V – 5.5V| ||||20 + 0.1 CB **(2)**|—|300|ns<br>|2.7V – 5.5V| ||||20|—|160|ns<br>|4.5V – 5.5V| |103|SDA and SCL Fall Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|TF<br>**(1)**|||||| ||||—|—|300|ns<br>|1.8V – 5.5V| ||||20 + 0.1 CB<br>**(2)**|—|300|ns<br>|2.7V – 5.5V| ||||20|—|80|ns<br>|4.5V – 5.5V| **Note 1:** This parameter is characterized, not 100% tested. **2:** CB is specified to be from 10 to 400 pF. DS20001952C-page 6 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **TABLE 1-3: I[2] C BUS DATA REQUIREMENTS (CONTINUED)** |**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS(CONTINUED)**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS(CONTINUED)**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS(CONTINUED)**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS(CONTINUED)**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS(CONTINUED)**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS(CONTINUED)**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS(CONTINUED)**|**TABLE 1-3:**<br>**I2C BUS DATA REQUIREMENTS(CONTINUED)**| |---|---|---|---|---|---|---|---| |**I2C Interface AC Characteristics:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C**,**RPU(SCL,<br>SDA) = 1 k, CL(SCL, SDA) = 135 pF|||||||| |**Param.**<br>**No.**|**Characteristic**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**| |90|START Condition Setup Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|TSU:STA|||||| ||||4.7|—|—|µs|1.8V – 5.5V| ||||0.6|—|—|µs|2.7V – 5.5V| ||||0.16|—|—|µs|4.5V – 5.5V| |91|START Condition Hold Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|THD:STA|||||| ||||4.0|—|—|µs|1.8V – 5.5V| ||||0.6|—|—|µs|2.7V – 5.5V| ||||0.16|—|—|µs|4.5V – 5.5V| |106|Data Input Hold Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|THD:DAT|||||| ||||0|—|3.45|µs|1.8V – 5.5V| ||||0|—|0.9|µs|2.7V – 5.5V| ||||0|—|0.15|µs|4.5V – 5.5V| |107|Data Input Setup Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|TSU:DAT|||||| ||||250|—|—|ns|1.8V – 5.5V| ||||100|—|—|ns|2.7V – 5.5V| ||||0.01|—|—|µs|4.5V – 5.5V| |92|Stop Condition Setup Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|TSU:STO|||||| ||||4.0|—|—|µs|1.8V – 5.5V| ||||0.6|—|—|µs|2.7V – 5.5V| ||||0.16|—|—|µs|4.5V–5.5V| |109|Output Valid From Clock:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|TAA|||||| ||||—|—|3.45|µs|1.8V – 5.5V| ||||—|—|0.9|µs|2.7V – 5.5V| ||||—|—|0.18|µs|4.5V – 5.5V| |110|Bus Free Time:<br>100 kHz mode<br>400 kHz mode<br>1.7 MHz mode|TBUF|||||| ||||4.7|—|—|µs|1.8V – 5.5V| ||||1.3|—|—|µs|2.7V – 5.5V| ||||N/A|—|N/A|µs|4.5V – 5.5V| |111|Bus Capacitive Loading:<br>100 kHz and 400 kHz<br>1.7 MHz|CB|||||| ||||—|—|400|pF|**Note 1**| ||||—|—|100|pF|**Note 1**| |112|Input Filter Spike Suppression<br>(SDA and SCL):<br>100 kHz and 400 kHz<br>1.7 MHz|TSP|||||| ||||—|—|50|ns|| ||||—|—|10|ns|Spike suppression off| **Note 1:** This parameter is characterized, not 100% tested. **2:** CB is specified to be from 10 to 400 pF. DS20001952C-page 7 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** ## **FIGURE 1-5: SPI INPUT TIMING** **==> picture [426 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> CS [(][1][)] 3<br>11<br>1 6 10<br>Mode 1,1 7 2<br>SCK Mode 0,0<br>4 5<br>SI<br>MSB in LSB in<br>SO High-Impedance<br>Note 1: When using SPI Mode 1,1 the CS pin needs to be toggled once before the first communication after<br>power-up.<br>**----- End of picture text -----**<br> ## **FIGURE 1-6: SPI OUTPUT TIMING** **==> picture [444 x 148] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>2<br>8 9<br>SCK Mode 1,1<br>Mode 0,0<br>12<br>14<br>13<br>SO<br>MSB out LSB out<br>Don’t Care<br>SI<br>**----- End of picture text -----**<br> ## **TABLE 1-4: SPI INTERFACE REQUIREMENTS** |**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS**| |---|---|---|---|---|---|---|---| ||||||||| |**SPI Interface AC Characteristics:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|||||||| |**Param.**<br>**No.**|**Characteristic**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**| |—|Clock Frequency|FCLK|—|—|5|MHz|1.8V – 5.5V| ||||—|—|10|MHz|2.7V – 5.5V| ||||—|—|10|MHz|4.5V – 5.5V| |1|CS<br>SetupTime|TCSS|50|—|—|ns|| |2|CS<br>Hold Time|TCSH|100|—|—|ns|1.8V – 5.5V| ||||50|—|—|ns|2.7V – 5.5V| |3|CS<br>Disable Time|TCSD|100|—|—|ns|1.8V – 5.5V| ||||50|—|—|ns|2.7V – 5.5V| |4|Data Setup Time|TSU|20|—|—|ns|1.8V – 5.5V| ||||10|—|—|ns|2.7V – 5.5V| **Note 1:** This parameter is characterized, not 100% tested. DS20001952C-page 8 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **TABLE 1-4: SPI INTERFACE REQUIREMENTS (CONTINUED)** |**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS(CONTINUED)**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS(CONTINUED)**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS(CONTINUED)**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS(CONTINUED)**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS(CONTINUED)**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS(CONTINUED)**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS(CONTINUED)**|**TABLE 1-4:**<br>**SPI INTERFACE REQUIREMENTS(CONTINUED)**| |---|---|---|---|---|---|---|---| ||||||||| |**SPI Interface AC Characteristics:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|||||||| |**Param.**<br>**No.**|**Characteristic**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**| |5|Data Hold Time|THD|20|—|—|ns|1.8V – 5.5V| ||||10|—|—|ns|2.7V – 5.5V| |6|CLK Rise Time|TR|—|—|2|µs|**Note 1**| |7|CLK Fall Time|TF|—|—|2|µs|**Note 1**| |8|Clock High Time|THI|90|—|—|ns|1.8V – 5.5V| ||||45|—|—|ns|2.7V – 5.5V| |9|Clock Low Time|TLO|90|—|—|ns|1.8V – 5.5V| ||||45|—|—|ns|2.7V – 5.5V| |10|Clock DelayTime|TCLD|50|—|—|ns|| |11|Clock Enable Time|TCLE|50|—|—|ns|| |12|Output Valid from Clock Low|TV|—|—|90|ns|1.8V – 5.5V| ||||—|—|45|ns|2.7V – 5.5V| |13|Output Hold Time|THO|0|—|—|ns|| |14|Output Disable Time|TDIS|—|—|100|ns|| **Note 1:** This parameter is characterized, not 100% tested. **FIGURE 1-7: GPIO AND INT TIMING** **==> picture [420 x 262] intentionally omitted <==** **----- Start of picture text -----**<br> SCL/SCK<br>SDA/SI<br>In D1 D0<br>LSb of data byte zero<br>during a write or read<br>command, depending<br>on parameter 50<br>GPn<br>Output<br>Pin<br>51<br>INT<br>Pin<br>INT Pin Active Inactive<br>53<br>GPn<br>Input<br>Pin<br>52<br>Register<br>Loaded<br>**----- End of picture text -----**<br> DS20001952C-page 9 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** ## **TABLE 1-5: GP AND INT PINS REQUIREMENTS** |**TABLE 1-5:**<br>**GP AND INT PINS REQUIREMENTS**|**TABLE 1-5:**<br>**GP AND INT PINS REQUIREMENTS**|**TABLE 1-5:**<br>**GP AND INT PINS REQUIREMENTS**|**TABLE 1-5:**<br>**GP AND INT PINS REQUIREMENTS**|**TABLE 1-5:**<br>**GP AND INT PINS REQUIREMENTS**|**TABLE 1-5:**<br>**GP AND INT PINS REQUIREMENTS**|**TABLE 1-5:**<br>**GP AND INT PINS REQUIREMENTS**|**TABLE 1-5:**<br>**GP AND INT PINS REQUIREMENTS**| |---|---|---|---|---|---|---|---| ||||||||| |**GP and INT Pins AC Characteristics:**Unless otherwise noted, 1.8VVDD 5.5V at -40CTA +125C|||||||| |**Param.**<br>**No.**|**Characteristic**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**| |50|Serial Data to Output Valid|TGPOV|—|—|500|ns|| |51|Interrupt Pin Disable Time|TINTD|—|—|600|ns|| |52|GP Input Change to<br>Register Valid|TGPIV|—|—|450|ns|| |53|IOC Event to INT Active|TGPINT|—|—|600|ns|| ||Glitch Filter on GP Pins|TGLITCH|—|—|150|ns|**Note 1**| **Note 1:** This parameter is characterized, not 100% tested. DS20001952C-page 10 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **2.0 PIN DESCRIPTIONS** The descriptions of the pins are listed in Table 2-1. ## **TABLE 2-1: PINOUT DESCRIPTION** |**Pin**<br>**Name**|**QFN**|**SOIC**<br>**SPDIP**<br>**SSOP**|**Pin**<br>**Type**|**Function**| |---|---|---|---|---| |GPB0|25|1|I/O|Bidirectional I/Opin. Can be enabled for interrupt-on-change and/or internal weakpull-upresistor.| |GPB1|26|2|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |GPB2|27|3|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |GPB3|28|4|I/O|Bidirectional I/Opin. Can be enabled for interrupt-on-change and/or internal weakpull-upresistor.| |GPB4|1|5|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |GPB5|2|6|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |GPB6|3|7|I/O|Bidirectional I/Opin. Can be enabled for interrupt-on-change and/or internal weakpull-upresistor.| |GPB7|4|8|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |VDD|5|9|P|Power| |VSS|6|10|P|Ground| |NC/CS|7|11|I|NC (**MCP23017**)/Chip Select (**MCP23S17**)| |SCK|8|12|I|Serial clock input| |SDA/SI|9|13|I/O|Serial data I/O(**MCP23017**)/Serial data input(**MCP23S17**)| |NC/SO|10|14|O|NC (**MCP23017**)/Serial data out (**MCP23S17**)| |A0|11|15|I|Hardware address pin. Must be externally biased.| |A1|12|16|I|Hardware addresspin. Must be externallybiased.| |A2|13|17|I|Hardware address pin. Must be externally biased.| |RESET|14|18|I|Hardware reset. Must be externally biased.| |INTB|15|19|O|Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.| |INTA|16|20|O|Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.| |GPA0|17|21|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |GPA1|18|22|I/O|Bidirectional I/Opin. Can be enabled for interrupt-on-change and/or internal weakpull-upresistor.| |GPA2|19|23|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |GPA3|20|24|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |GPA4|21|25|I/O|Bidirectional I/Opin. Can be enabled for interrupt-on-change and/or internal weakpull-upresistor.| |GPA5|22|26|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |GPA6|23|27|I/O|Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.| |GPA7|24|28|I/O|Bidirectional I/Opin. Can be enabled for interrupt-on-change and/or internal weakpull-upresistor.| |EP|29|—|—|Exposed Thermal Pad. Either connect to VSS, or leave unconnected.| DS20001952C-page 11 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **3.0 DEVICE OVERVIEW** The MCP23017/MCP23S17 (MCP23X17) device family provides 16-bit, general purpose parallel I/O expansion for I[2] C bus or SPI applications. The two devices differ only in the serial interface: - MCP23017 – I[2] C interface - MCP23S17 – SPI interface The MCP23X17 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits (IODIRA/B). The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The 16-bit I/O port functionally consists of two 8-bit ports (PORTA and PORTB). The MCP23X17 can be configured to operate in the 8-bit or 16-bit modes via IOCON.BANK. There are two interrupt pins, INTA and INTB, that can be associated with their respective ports, or can be logically OR’ed together so that both pins will activate if either port causes an interrupt. The interrupt output can be configured to activate under two conditions (mutually exclusive): 1. When any input state differs from its corresponding Input Port register state. This is used to indicate to the system master that an input state has changed. 2. When an input state differs from a preconfigured register value (DEFVAL register). The Interrupt Capture register captures port values at the time of the interrupt, thereby saving the condition that caused the interrupt. ## **3.2 Serial Interface** This block handles the functionality of the I[2] C ( **MCP23017** ) or SPI ( **MCP23S17** ) interface protocol. The MCP23X17 contains 22 individual registers (11 register pairs) that can be addressed through the Serial Interface block, as shown in Table 3-1. **TABLE 3-1: REGISTER ADDRESSES** |**Address**<br>**IOCON.BANK =****`1`**|**Address**<br>**IOCON.BANK =****`0`**|**Access to:**| |---|---|---| |00h|00h|IODIRA| |10h|01h|IODIRB| |01h|02h|IPOLA| |11h|03h|IPOLB| |02h|04h|GPINTENA| |12h|05h|GPINTENB| |03h|06h|DEFVALA| |13h|07h|DEFVALB| |04h|08h|INTCONA| |14h|09h|INTCONB| |05h|0Ah|IOCON| |15h|0Bh|IOCON| |06h|0Ch|GPPUA| |16h|0Dh|GPPUB| |07h|0Eh|INTFA| |17h|0Fh|INTFB| |08h|10h|INTCAPA| |18h|11h|INTCAPB| |09h|12h|GPIOA| |19h|13h|GPIOB| |0Ah|14h|OLATA| |1Ah|15h|OLATB| The Power-on Reset (POR) sets the registers to their default values and initializes the device state machine. The hardware address pins are used to determine the device address. ## **3.1 Power-on Reset (POR)** The on-chip POR circuit holds the device in reset until VDD has reached a high enough voltage to deactivate the POR circuit (i.e., release the device from reset). The maximum VDD rise time is specified in **Section 1.0 “Electrical Characteristics”** . When the device exits the POR condition (releases reset), device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation. DS20001952C-page 12 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## 3.2.1 BYTE MODE AND SEQUENTIAL MODE The MCP23X17 family has the ability to operate in Byte mode or Sequential mode (IOCON.SEQOP). **Byte mode** disables automatic Address Pointer incrementing. When operating in Byte mode, the MCP23X17 family does not increment its internal address counter after each byte during the data transfer. This gives the ability to continually access the same address by providing extra clocks (without additional control bytes). This is useful for polling the GPIO register for data changes or for continually writing to the output latches. A special mode **(Byte mode with IOCON.BANK =** **`0` )** causes the address pointer to toggle between associated A/B register pairs. For example, if the BANK bit is cleared and the Address Pointer is initially set to address 12h (GPIOA) or 13h (GPIOB), the pointer will toggle between GPIOA and GPIOB. Note that the Address Pointer can initially point to either address in the register pair. **Sequential mode** enables automatic address pointer incrementing. When operating in Sequential mode, the MCP23X17 family increments its address counter after each byte during the data transfer. The Address Pointer automatically rolls over to address 00h after accessing the last register. These two modes are not to be confused with single writes/reads and continuous writes/reads that are serial protocol sequences. For example, the device may be configured for Byte mode and the master may perform a continuous read. In this case, the MCP23X17 would not increment the Address Pointer and would repeatedly drive data from the same location. ## 3.2.2 I[2] C INTERFACE ## 3.2.2.1 I[2] C Write Operation The I[2] C write operation includes the control byte and register address sequence, as shown in Figure 3-1. This sequence is followed by eight bits of data from the master and an Acknowledge (ACK) from the MCP23017. The operation is ended with a Stop (P) or Restart (SR) condition being generated by the master. Data is written to the MCP23017 after every byte transfer. If a Stop or Restart condition is generated during a data transfer, the data will not be written to the MCP23017. Both “byte writes” and “sequential writes” are supported by the MCP23017. If Sequential mode is enabled (IOCON, SEQOP = `0` ) (default), the MCP23017 increments its address counter after each ACK during the data transfer. ## **FIGURE 3-1: BYTE AND SEQUENTIAL WRITE** |**S**|**OP**|**W**|**ADDR**||**DIN**||**P**<br>**DIN**<br>**P**| |---|---|---|---|---|---|---|---| ||||||||| |**S**|**OP**|**W**|**ADDR**||||| ||||||||| DS20001952C-page 13 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** ## 3.2.2.2 I[2] C Read Operation I[2] C Read operations include the control byte sequence, as shown in Figure 3-2. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit set (R/W = `1` ). The MCP23017 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition. ## **FIGURE 3-2: BYTE AND SEQUENTIAL READ** |Byte<br>Sequential|**S**|**OP**|**W**||**SR**|**OP**|**R**|**DOUT**|||**P**|**P**|**P**| |---|---|---|---|---|---|---|---|---|---|---|---|---|---| ||||||||||||||| ||**S**|**OP**|**W**||**SR**|**OP**|**R**|**DOUT**|....|**DOUT**|||**P**| ## 3.2.2.3 I[2] C Sequential Write/Read For sequential operations (Write or Read), instead of transmitting a Stop or Restart condition after the data transfer, the master clocks the next byte pointed to by the address pointer (see **Section 3.2.1 “Byte Mode and Sequential Mode”** for details regarding sequential operation control). The sequence ends with the master sending a Stop or Restart condition. The MCP23017 Address Pointer will roll over to address zero after reaching the last register address. Refer to Figure 3-3. ## **FIGURE 3-3: MCP23017 I[2] C DEVICE PROTOCOL** **==> picture [353 x 239] intentionally omitted <==** **----- Start of picture text -----**<br> S OP W ADDR DIN .... DIN P<br>SR OP R DOUT .... D OUT P<br>SR OP W DIN .... DIN P<br>P<br>S OP R DOUT .... DOUT P<br>SR OP R DOUT .... DOUT P<br>SR OP W ADDR DIN .... DIN P<br>P<br>**----- End of picture text -----**<br> DS20001952C-page 14 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## 3.2.3 SPI INTERFACE ## 3.2.3.1 SPI Write Operation The SPI write operation is started by lowering CS. The Write command (slave address with R/W bit cleared) is then clocked into the device. The opcode is followed by an address and at least one data byte. ## 3.2.3.2 SPI Read Operation The SPI read operation is started by lowering CS. The SPI read command (slave address with R/W bit set) is then clocked into the device. The opcode is followed by an address, with at least one data byte being clocked out of the device. ## 3.2.3.3 SPI Sequential Write/Read For sequential operations, instead of deselecting the device by raising CS, the master clocks the next byte pointed to by the Address Pointer. (see **Section 3.2.1 “Byte Mode and Sequential Mode”** for details regarding sequential operation control). The sequence ends by the raising of CS. The MCP23S17 Address Pointer will roll over to address zero after reaching the last register address. four fixed bits and three user-defined hardware address bits (pins A2, A1 and A0). Figure 3-4 shows the control byte format. ## 3.3.2 ADDRESSING SPI DEVICES ( **MCP23S17** ) The MCP23S17 is a slave SPI device. The slave address contains four fixed bits and three user-defined hardware address bits (if enabled via IOCON.HAEN) (pins A2, A1 and A0) with the read/write bit filling out the control byte. Figure 3-5 shows the control byte format. The address pins should be externally biased even if disabled (IOCON.HAEN = `0` ). ## **FIGURE 3-4: I[2] C CONTROL BYTE FORMAT** **==> picture [212 x 98] intentionally omitted <==** **----- Start of picture text -----**<br> Control Byte<br>S 0 1 0 0 A2 A1 A0 R/W ACK<br>Slave Address<br>Start R/W bit<br>bit ACK bit<br>R/W = 0 = write<br>R/W = 1 = read<br>**----- End of picture text -----**<br> ## **3.3 Hardware Address Decoder** The hardware address pins are used to determine the device address. To address a device, the corresponding address bits in the control byte must match the pin state. The pins must be biased externally. ## 3.3.1 ADDRESSING I[2] C DEVICES ( **MCP23017** ) The MCP23017 is a slave I[2] C interface device that supports 7-bit slave addressing, with the read/write bit filling out the control byte. The slave address contains ## **FIGURE 3-5: SPI CONTROL BYTE FORMAT** **==> picture [205 x 111] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>Control Byte<br>0 1 0 0 A2 A1 A0 R/W<br>Slave Address<br>R/W bit<br>R/W = 0 = write<br>R/W = 1 = read<br>**----- End of picture text -----**<br> ## **FIGURE 3-6: I[2] C ADDRESSING REGISTERS** **==> picture [453 x 96] intentionally omitted <==** **----- Start of picture text -----**<br> S 0 1 0 0 A2 A1 A0 0 ACK * A7 A6 A5 A4 A3 A2 A1 A0 ACK *<br>R/W = 0<br>Device Opcode Register Address<br>*The ACKs are provided by the MCP23017.<br>**----- End of picture text -----**<br> DS20001952C-page 15 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** ## **FIGURE 3-7:** ## **SPI ADDRESSING REGISTERS** **==> picture [413 x 70] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>0 1 0 0 A2 * A1 * A0 * R/W A7 A6 A5 A4 A3 A2 A1 A0<br>Device Opcode Register Address<br>**----- End of picture text -----**<br> ***** Address pins are enabled/disabled via IOCON.HAEN. ## **3.4 GPIO Port** The GPIO module is a general purpose, 16-bit wide, bidirectional port that is functionally split into two 8-bit wide ports. The GPIO module contains the data ports (GPIOn), internal pull-up resistors and the output latches (OLATn). Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port. Writing to the GPIOn register actually causes a write to the latches (OLATn). Writing to the OLATn register forces the associated output drivers to drive to the level in OLATn. Pins configured as inputs turn off the associated output driver and put it in high-impedance. **TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK =** **`1` )** |**Register**<br>**Name**|**Address**<br>**(hex)**|**bit 7**|**bit 6**|**bit 5**|**bit 4**|**bit 3**|**bit 2**|**bit 1**|**bit 0**|**POR/RST**<br>**value**| |---|---|---|---|---|---|---|---|---|---|---| |IODIRA|00|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`| |IPOLA|01|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`| |GPINTENA|02|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`| |GPPUA|06|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`| |GPIOA|09|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`| |OLATA|0A|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`| |IODIRB|10|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`| |IPOLB|11|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`| |GPINTENB|12|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`| |GPPUB|16|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`| |GPIOB|19|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`| |OLATB|1A|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`| ## **TABLE 3-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE GPIO PORTS (BANK =** **`0` )** |**Register**<br>**Name**|**Address**<br>**(hex)**|**bit 7**|**bit 6**|**bit 5**|**bit 4**|**bit 3**|**bit 2**|**bit 1**|**bit 0**|**POR/RST**<br>**value**| |---|---|---|---|---|---|---|---|---|---|---| |IODIRA|00|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`| |IODIRB|01|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`| |IPOLA|02|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`| |IPOLB|03|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`| |GPINTENA|04|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`| |GPINTENB|05|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`| |GPPUA|0C|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`| |GPPUB|0D|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`| |GPIOA|12|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`| |GPIOB|13|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`| |OLATA|14|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`| |OLATB|15|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`| DS20001952C-page 16 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **3.5 Configuration and Control Registers** There are 21 registers associated with the MCP23X17, as shown in Tables 3-4 and3-5. The two tables show the register mapping with the two BANK bit values. Ten registers are associated with PORTA and ten are associated with PORTB. One register (IOCON) is shared between the two ports. The PORTA registers are identical to the PORTB registers, therefore, they will be referred to without differentiating between the port designation (i.e., they will not have the “A” or “B” designator assigned) in the register tables. **TABLE 3-4: CONTROL REGISTER SUMMARY (IOCON.BANK =** **`1` )** |**Register**<br>**Name**|**Address**<br>**(hex)**|**bit 7**|**bit 6**|**bit 5**|**bit 4**|**bit 3**|**bit 2**|**bit 1**|**bit 0**|**POR/RST**<br>**value**| |---|---|---|---|---|---|---|---|---|---|---| |IODIRA|00|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`| |IPOLA|01|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`| |GPINTENA|02|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`| |DEFVALA|03|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|`0000 0000`| |INTCONA|04|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|`0000 0000`| |IOCON|05|BANK|MIRROR|SEQOP|DISSLW|HAEN|ODR|INTPOL|—|`0000 0000`| |GPPUA|06|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`| |INTFA|07|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INTO|`0000 0000`| |INTCAPA|08|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|`0000 0000`| |GPIOA|09|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`| |OLATA|0A|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`| |IODIRB|10|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`| |IPOLB|11|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`| |GPINTENB|12|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`| |DEFVALB|13|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|`0000 0000`| |INTCONB|14|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|`0000 0000`| |IOCON|15|BANK|MIRROR|SEQOP|DISSLW|HAEN|ODR|INTPOL|—|`0000 0000`| |GPPUB|16|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`| |INTFB|17|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INTO|`0000 0000`| |INTCAPB|18|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|`0000 0000`| |GPIOB|19|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`| |OLATB|1A|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`| ## **TABLE 3-5: CONTROL REGISTER SUMMARY (IOCON.BANK =** **`0` )** |**Register**<br>**Name**|**Address**<br>**(hex)**|**bit 7**|**bit 6**|**bit 5**|**bit 4**|**bit 3**|**bit 2**|**bit 1**|**bit 0**|**POR/RST**<br>**value**| |---|---|---|---|---|---|---|---|---|---|---| |IODIRA|00|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`| |IODIRB|01|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`| |IPOLA|02|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`| |IPOLB|03|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`| |GPINTENA|04|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`| |GPINTENB|05|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`| |DEFVALA|06|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|`0000 0000`| |DEFVALB|07|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|`0000 0000`| |INTCONA|08|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|`0000 0000`| |INTCONB|09|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|`0000 0000`| |IOCON|0A|BANK|MIRROR|SEQOP|DISSLW|HAEN|ODR|INTPOL|—|`0000 0000`| |IOCON|0B|BANK|MIRROR|SEQOP|DISSLW|HAEN|ODR|INTPOL|—|`0000 0000`| |GPPUA|0C|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`| |GPPUB|0D|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`| DS20001952C-page 17 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** ## **TABLE 3-5: CONTROL REGISTER SUMMARY (IOCON.BANK =** **`0` ) (CONTINUED)** |**Register**<br>**Name**|**Address**<br>**(hex)**|**bit 7**|**bit 6**|**bit 5**|**bit 4**|**bit 3**|**bit 2**|**bit 1**|**bit 0**|**POR/RST**<br>**value**| |---|---|---|---|---|---|---|---|---|---|---| |INTFA|0E|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INTO|`0000 0000`| |INTFB|0F|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INTO|`0000 0000`| |INTCAPA|10|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|`0000 0000`| |INTCAPB|11|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|`0000 0000`| |GPIOA|12|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`| |GPIOB|13|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`| |OLATA|14|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`| |OLATB|15|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`| ## 3.5.1 I/O DIRECTION REGISTER Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output. ## **REGISTER 3-1: IODIR: I/O DIRECTION REGISTER (ADDR 0x00)** |**REGISTER 3-1:**<br>**IODIR: I/O DIRECTION REGISTER (ADDR 0x00)**|**REGISTER 3-1:**<br>**IODIR: I/O DIRECTION REGISTER (ADDR 0x00)**|**REGISTER 3-1:**<br>**IODIR: I/O DIRECTION REGISTER (ADDR 0x00)**|**REGISTER 3-1:**<br>**IODIR: I/O DIRECTION REGISTER (ADDR 0x00)**|**REGISTER 3-1:**<br>**IODIR: I/O DIRECTION REGISTER (ADDR 0x00)**|**REGISTER 3-1:**<br>**IODIR: I/O DIRECTION REGISTER (ADDR 0x00)**|**REGISTER 3-1:**<br>**IODIR: I/O DIRECTION REGISTER (ADDR 0x00)**|**REGISTER 3-1:**<br>**IODIR: I/O DIRECTION REGISTER (ADDR 0x00)**| |---|---|---|---|---|---|---|---| |R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1|||||||| |IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| bit 7-0 **IO<7:0>:** Controls the direction of data I/O <7:0> - `1` = Pin is configured as an input. - `0` = Pin is configured as an output. ## 3.5.2 INPUT POLARITY REGISTER This register allows the user to configure the polarity on the corresponding GPIO port bits. If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin. ## **REGISTER 3-2: IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)** |**REGISTER 3-2:**<br>**IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)**|**REGISTER 3-2:**<br>**IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)**|**REGISTER 3-2:**<br>**IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)**|**REGISTER 3-2:**<br>**IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)**|**REGISTER 3-2:**<br>**IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)**|**REGISTER 3-2:**<br>**IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)**|**REGISTER 3-2:**<br>**IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)**|**REGISTER 3-2:**<br>**IPOL: INPUT POLARITY PORT REGISTER (ADDR 0x01)**| |---|---|---|---|---|---|---|---| |R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|||||||| |IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| bit 7-0 **IP<7:0>:** Controls the polarity inversion of the input pins <7:0> - `1` = GPIO register bit reflects the opposite logic state of the input pin. - `0` = GPIO register bit reflects the same logic state of the input pin. DS20001952C-page 18 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## 3.5.3 INTERRUPT-ON-CHANGE CONTROL REGISTER The GPINTEN register controls the interrupt-on-change feature for each pin. If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change. ## **REGISTER 3-3: GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)** |**REGISTER 3-3:**<br>**GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)**|**REGISTER 3-3:**<br>**GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)**|**REGISTER 3-3:**<br>**GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)**|**REGISTER 3-3:**<br>**GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)**|**REGISTER 3-3:**<br>**GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)**|**REGISTER 3-3:**<br>**GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)**|**REGISTER 3-3:**<br>**GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)**|**REGISTER 3-3:**<br>**GPINTEN: INTERRUPT-ON-CHANGE PINS (ADDR 0x02) (Note 1)**| |---|---|---|---|---|---|---|---| |R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|||||||| |GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| bit 7-0 **GPINT<7:0>:** General purpose I/O interrupt-on-change bits <7:0> - `1` = Enables GPIO input pin for interrupt-on-change event. - `0` = Disables GPIO input pin for interrupt-on-change event. **Note 1:** Refer to INTCON. ## 3.5.4 DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an interrupt to occur. ## **REGISTER 3-4: DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)** |**REGISTER 3-4:**<br>**DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)**|**REGISTER 3-4:**<br>**DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)**|**REGISTER 3-4:**<br>**DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)**|**REGISTER 3-4:**<br>**DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)**|**REGISTER 3-4:**<br>**DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)**|**REGISTER 3-4:**<br>**DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)**|**REGISTER 3-4:**<br>**DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)**|**REGISTER 3-4:**<br>**DEFVAL: DEFAULT VALUE REGISTER (ADDR 0x03)**| |---|---|---|---|---|---|---|---| ||||||||| |R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|||||||| |DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| ||||||||| bit 7-0 **DEF<7:0>:** Sets the compare value for pins configured for interrupt-on-change from defaults <7:0> ## **(Note 1)** If the associated pin level is the opposite from the register bit, an interrupt occurs. **(Note 2)** **Note 1:** Refer to INTCON. - **2:** Refer to INTCON and GPINTEN. DS20001952C-page 19 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## 3.5.5 INTERRUPT CONTROL REGISTER The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value. ## **REGISTER 3-5: INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)** |**REGISTER 3-5:**<br>**INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)**|**REGISTER 3-5:**<br>**INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)**|**REGISTER 3-5:**<br>**INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)**|**REGISTER 3-5:**<br>**INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)**|**REGISTER 3-5:**<br>**INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)**|**REGISTER 3-5:**<br>**INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)**|**REGISTER 3-5:**<br>**INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)**|**REGISTER 3-5:**<br>**INTCON: INTERRUPT-ON-CHANGE CONTROL REGISTER (ADDR 0x04) (Note 1)**| |---|---|---|---|---|---|---|---| |R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|||||||| |IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| ||||||||| bit 7-0 **IOC<7:0>:** Controls how the associated pin value is compared for interrupt-on-change <7:0> `1` = Pin value is compared against the associated bit in the DEFVAL register. - `0` = Pin value is compared against the previous pin value. **Note 1:** Refer to INTCON and GPINTEN. ## 3.5.6 CONFIGURATION REGISTER The IOCON register contains several bits for configuring the device: The BANK bit changes how the registers are mapped (see Tables 3-4 and3-5 for more details). - If BANK = `1` , the registers associated with each port are segregated. Registers associated with PORTA are mapped from address 00h - 0Ah and registers associated with PORTB are mapped from 10h - 1Ah. - If BANK = `0` , the A/B registers are paired. For example, IODIRA is mapped to address 00h and IODIRB is mapped to the next address (address 01h). The mapping for all registers is from 00h -15h. It is important to take care when changing the BANK bit as the address mapping changes after the byte is clocked into the device. The address pointer may point to an invalid location after the bit is modified. For example, if the device is configured to automatically increment its internal Address Pointer, the following scenario would occur: - BANK = `0` - Write 80h to address 0Ah (IOCON) to set the BANK bit - Once the write completes, the internal address now points to 0Bh which is an invalid address when the BANK bit is set. For this reason, when changing the BANK bit, it is advised to only perform byte writes to this register. The **MIRROR** bit controls how the INTA and INTB pins function with respect to each other. - When MIRROR = `1` , the INTn pins are functionally OR’ed so that an interrupt on either port will cause both pins to activate. - When MIRROR = `0` , the INT pins are separated. Interrupt conditions on a port will cause its respective INT pin to activate. The Sequential Operation ( **SEQOP** ) controls the incrementing function of the Address Pointer. If the address pointer is disabled, the Address Pointer does not automatically increment after each byte is clocked during a serial transfer. This feature is useful when it is desired to continuously poll (read) or modify (write) a register. The Slew Rate ( **DISSLW** ) bit controls the slew rate function on the SDA pin. If enabled, the SDA slew rate will be controlled when driving from a high to low. The Hardware Address Enable ( **HAEN** ) bit enables/disables hardware addressing on the MCP23S17 only. The address pins (A2, A1 and A0) must be externally biased, regardless of the HAEN bit value. If enabled (HAEN = `1` ), the device’s hardware address matches the address pins. If disabled (HAEN = `0` ), the device’s hardware address is A2 = A1 = A0 = `0` . DS20001952C-page 20 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** The Open-Drain ( **ODR** ) control bit enables/disables the INT pin for open-drain configuration. Setting this bit overrides the INTPOL bit. The Interrupt Polarity ( **INTPOL** ) sets the polarity of the INT pin. This bit is functional only when the ODR bit is cleared, configuring the INT pin as active push-pull. ## **REGISTER 3-6: IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)** |**REGISTER 3-6:**<br>**IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)**|**REGISTER 3-6:**<br>**IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)**|**REGISTER 3-6:**<br>**IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)**|**REGISTER 3-6:**<br>**IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)**|**REGISTER 3-6:**<br>**IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)**|**REGISTER 3-6:**<br>**IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)**|**REGISTER 3-6:**<br>**IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)**|**REGISTER 3-6:**<br>**IOCON: I/O EXPANDER CONFIGURATION REGISTER (ADDR 0x05)**| |---|---|---|---|---|---|---|---| |R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>U-0|||||||| |BANK|MIRROR|SEQOP|DISSLW|HAEN|ODR|INTPOL|—| |bit 7<br>bit 0|||||||| |**Legend:**|||| |---|---|---|---| |R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’|| |-n = Value at POR|‘1’ = Bit is set|‘0’ = Bit is cleared|x = Bit is unknown| - bit 7 **BANK:** Controls how the registers are addressed `1` = The registers associated with each port are separated into different banks. `0` = The registers are in the same bank (addresses are sequential). - bit 6 **MIRROR:** INT Pins Mirror bit `1` = The INT pins are internally connected `0` = The INT pins are not connected. INTA is associated with PORTA and INTB is associated with PORTB - bit 5 **SEQOP:** Sequential Operation mode bit `1` = Sequential operation disabled, address pointer does not increment. `0` = Sequential operation enabled, address pointer increments. - bit 4 **DISSLW:** Slew Rate control bit for SDA output `1` = Slew rate disabled `0` = Slew rate enabled - bit 3 **HAEN:** Hardware Address Enable bit ( **MCP23S17** only) **(Note 1)** `1` = Enables the MCP23S17 address pins. `0` = Disables the MCP23S17 address pins. - bit 2 **ODR:** Configures the INT pin as an open-drain output `1` = Open-drain output (overrides the INTPOL bit.) `0` = Active driver output (INTPOL bit sets the polarity.) - bit 1 **INTPOL:** This bit sets the polarity of the INT output pin `1` = Active-high `0` = Active-low - bit 0 **Unimplemented:** Read as ‘ `0` ’ **Note 1:** Address pins are always enabled on the MCP23017. DS20001952C-page 21 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## 3.5.7 PULL-UP RESISTOR CONFIGURATION REGISTER The GPPU register controls the pull-up resistors for the port pins. If a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100 k resistor. ## **REGISTER 3-7: GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)** |**REGISTER 3-7:**<br>**GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)**|**REGISTER 3-7:**<br>**GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)**|**REGISTER 3-7:**<br>**GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)**|**REGISTER 3-7:**<br>**GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)**|**REGISTER 3-7:**<br>**GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)**|**REGISTER 3-7:**<br>**GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)**|**REGISTER 3-7:**<br>**GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)**|**REGISTER 3-7:**<br>**GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)**| |---|---|---|---|---|---|---|---| |R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|||||||| |PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| ||||||||| bit 7-0 **PU<7:0>** Controls the weak pull-up resistors on each pin (when configured as an input) - `1` = Pull-up enabled - `0` = Pull-up disabled ## 3.5.8 INTERRUPT FLAG REGISTER The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A set bit indicates that the associated pin caused the interrupt. This register is read-only. Writes to this register will be ignored. ## **REGISTER 3-8: INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)** |**REGISTER 3-8:**<br>**INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)**|**REGISTER 3-8:**<br>**INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)**|**REGISTER 3-8:**<br>**INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)**|**REGISTER 3-8:**<br>**INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)**|**REGISTER 3-8:**<br>**INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)**|**REGISTER 3-8:**<br>**INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)**|**REGISTER 3-8:**<br>**INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)**|**REGISTER 3-8:**<br>**INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)**| |---|---|---|---|---|---|---|---| ||||||||| |R-0<br>R-0<br>R-0<br>R-0<br>R-0<br>R-0<br>R-0<br>R-0|||||||| |INT7|INT6|INT5|INT4|INT3|INT2|INT1|INT0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| ||||||||| bit 7-0 **INT<7:0>:** Reflects the interrupt condition on the port. It reflects the change only if interrupts are enabled per GPINTEN<7:0>. - `1` = Pin caused interrupt. - `0` = Interrupt not pending DS20001952C-page 22 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## 3.5.9 INTERRUPT CAPTURED REGISTER The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is read-only and is updated only when an interrupt occurs. The register remains unchanged until the interrupt is cleared via a read of INTCAP or GPIO. ## **REGISTER 3-9: INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)** |**REGISTER 3-9:**<br>**INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)**|**REGISTER 3-9:**<br>**INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)**|**REGISTER 3-9:**<br>**INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)**|**REGISTER 3-9:**<br>**INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)**|**REGISTER 3-9:**<br>**INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)**|**REGISTER 3-9:**<br>**INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)**|**REGISTER 3-9:**<br>**INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)**|**REGISTER 3-9:**<br>**INTCAP: INTERRUPT CAPTURED VALUE FOR PORT REGISTER (ADDR 0x08)**| |---|---|---|---|---|---|---|---| |R-x<br>R-x<br>R-x<br>R-x<br>R-x<br>R-x<br>R-x<br>R-x|||||||| |ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| bit 7-0 **ICP<7:0>:** Reflects the logic level on the port pins at the time of interrupt due to pin change <7:0> `1` = Logic-high - `0` = Logic-low ## 3.5.10 PORT REGISTER The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register. ## **REGISTER 3-10: GPIO: GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09)** |R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0| |---|---|---|---|---|---|---|---| |GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| bit 7-0 **GP<7:0>:** Reflects the logic level on the pins <7:0> - `1` = Logic-high - `0` = Logic-low DS20001952C-page 23 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** ## 3.5.11 OUTPUT LATCH REGISTER (OLAT) The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs. ## **REGISTER 3-11: OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)** |**REGISTER 3-11:**<br>**OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)**|**REGISTER 3-11:**<br>**OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)**|**REGISTER 3-11:**<br>**OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)**|**REGISTER 3-11:**<br>**OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)**|**REGISTER 3-11:**<br>**OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)**|**REGISTER 3-11:**<br>**OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)**|**REGISTER 3-11:**<br>**OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)**|**REGISTER 3-11:**<br>**OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)**| |---|---|---|---|---|---|---|---| |R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0|||||||| |OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0| |bit 7<br>bit 0|||||||| ||||||||| |**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown|||||||| bit 7-0 **OL<7:0>:** Reflects the logic level on the output latch <7:0> - `1` = Logic-high - `0` = Logic-low ## **3.6 Interrupt Logic** If enabled, the MCP23X17 activates the INTn interrupt output when one of the port pins changes state or when a pin does not match the preconfigured default. Each pin is individually configurable as follows: - Enable/disable interrupt via GPINTEN - Can interrupt on either pin change or change from default as configured in DEFVAL Both conditions are referred to as Interrupt-on-Change (IOC). The interrupt control module uses the following registers/bits: - IOCON.MIRROR – controls if the two interrupt pins mirror each other - GPINTEN – Interrupt enable register - INTCON – controls the source for the IOC - DEFVAL – contains the register default for IOC operation ## 3.6.1 INTA AND INTB There are two interrupt pins: INTA and INTB. By default, INTA is associated with GPAn pins (PORTA) and INTB is associated with GPBn pins (PORTB). Each port has an independent signal which is cleared if its associated GPIO or INTCAP register is read. If IOCON.MIRROR = `1` , the internal signals are OR’ed together and routed to the INTn pads. In this case, the interrupt will only be cleared if the associated GPIO or INTCAP is read (see Table 3-6). **TABLE 3-6: INTERRUPT OPERATION (IOCON.MIRROR =** **`1` )** |**Interrupt**<br>**Condition**|**Read PORTn(1)**|**Interrupt**<br>**Result**| |---|---|---| |GPIOA|PORTA|Clear| ||PORTB|Unchanged| |GPIOB|PORTA|Unchanged| ||PORTB|Clear| |GPIOA and<br>GPIOB|PORTA|Unchanged| ||PORTB|Unchanged| ||Both PORTA and<br>PORTB|Clear| **Note 1:** PORTn = GPIOn or INTCAPn ## 3.6.2 IOC FROM PIN CHANGE If enabled, the MCP23X17 generates an interrupt if a mismatch condition exists between the current port value and the previous port value. Only IOC-enabled pins will be compared. Refer to Registers 3-3 and 3-5. ## 3.6.3 IOC FROM REGISTER DEFAULT ## 3.6.1.1 Mirroring the INT pins Additionally, the INTn pins can be configured to mirror each other so that any interrupt will cause both pins to go active. This is controlled via IOCON.MIRROR. If enabled, the MCP23X17 generates an interrupt if a mismatch occurs between the DEFVAL register and the port. Only IOC enabled pins are compared. Refer to Registers 3-3, 3-4 and 3-5. If IOCON.MIRROR = `0` , the internal signals are routed independently to the INTA and INTB pads. DS20001952C-page 24 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## 3.6.4 INTERRUPT OPERATION The INTn interrupt output can be configured as active-low, active-high or open-drain via the IOCON register. Only those pins that are configured as an input (IODIR register) with Interrupt-On-Change (IOC) enabled (IOINTEN register) can cause an interrupt. Pins defined as an output have no effect on the interrupt output pin. Input change activity on a port input pin that is enabled for IOC generates an internal device interrupt and the device captures the value of the port and copies it into INTCAP. The interrupt remains active until the INTCAP or GPIO register is read. Writing to these registers does not affect the interrupt. The interrupt condition is cleared after the LSb of the data is clocked out during a read command of GPIO or INTCAP. The first interrupt event causes the port contents to be copied into the INTCAP register. Subsequent interrupt conditions on the port will not cause an interrupt to occur as long as the interrupt is not cleared by a read of INTCAP or GPIO. **Note:** The value in INTCAP can be lost if GPIO is read before INTCAP while another IOC is pending. After reading GPIO, the interrupt will clear and then set due to the pending IOC, causing the INTCAP register to update. ## 3.6.5 INTERRUPT CONDITIONS There are two possible configurations that cause interrupts (configured via INTCON): 1. Pins configured for **interrupt-on-pin change** will cause an interrupt to occur if a pin changes to the opposite state. The default state is reset after an interrupt occurs and after clearing the interrupt condition (i.e., after reading GPIO or INTCAP). For example, an interrupt occurs by an input changing from ‘ `1` ’ to ‘ `0` ’. The new initial state for the pin is a logic ‘ `0` ’ after the interrupt is cleared. ## **FIGURE 3-8: INTERRUPT-ON-PIN CHANGE** **==> picture [184 x 97] intentionally omitted <==** **----- Start of picture text -----**<br> GPx<br>INT ACTIVE ACTIVE<br>Port value Read GPIO Port value<br>is captured or INTCAP is captured<br>into INTCAP into INTCAP<br>**----- End of picture text -----**<br> **FIGURE 3-9: INTERRUPT-ON-CHANGE FROM REGISTER DEFAULT** **==> picture [211 x 206] intentionally omitted <==** **----- Start of picture text -----**<br> DEFVAL REGISTER<br>GPx<7:0> 7 6 5 4 3 2 1 0<br>X X X X X 0 X X<br>GP2<br>Pin<br>INT ACTIVE ACTIVE<br>Pin<br>Port value<br>is captured Read GPIO<br>into INTCAP or INTCAP<br>(INT clears only if interrupt<br>condition does not exist.)<br>**----- End of picture text -----**<br> 2. Pins configured for **interrupt-on-change from register value** will cause an interrupt to occur if the corresponding input pin differs from the register bit. The interrupt condition will remain as long as the condition exists, regardless if the INTCAP or GPIO is read. See Figures 3-8 and 3-9 for more information on interrupt operations. DS20001952C-page 25 2005-2016 Microchip Technology Inc. ## **MCP23017/MCP23S17** ## **4.0 PACKAGING INFORMATION** ## **4.1 Package Marking Information** 28-Lead QFN **==> picture [39 x 82] intentionally omitted <==** **----- Start of picture text -----**<br> Example:<br>4%<br>23017<br>E/ML e3<br>1628256<br>**----- End of picture text -----**<br> 28-Lead SOIC **==> picture [129 x 53] intentionally omitted <==** **----- Start of picture text -----**<br> 28-Lead SPDIP<br>XXXXXXXXXXXXXXXXX<br>XXXXXXXXXXXXXXXXX<br>YYWWNN<br>**----- End of picture text -----**<br> **==> picture [135 x 166] intentionally omitted <==** **----- Start of picture text -----**<br> Example:<br>Mion nnnonnnnnn<br>MCP23017-E/SO e3<br>1628256<br>O &<br>TUMTIOOIOOO oD<br>Example:<br>MCP23017-E/SP e3<br>1628256<br>**----- End of picture text -----**<br> 28-Lead SSOP Example: ~~LINO MNO AOD LIMON~~ **XXXXXXXXXXXX** MCP23017 **XXXXXXXXXXXX** E/SS e3 **YYWWNNN** 1628256 ~~aeNMUUUOTOOUTI| aeMUNUUUOUUUUOLNON OAD|~~ **Legend:** XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) ***** This package is Pb-free. The Pb-free JEDEC designator ( ) e3 can be found on the outer packaging for this package. **Note** : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20001952C-page 26 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** **==> picture [469 x 638] intentionally omitted <==** DS20001952C-page 27 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** **==> picture [469 x 602] intentionally omitted <==** DS20001952C-page 28 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** DS20001952C-page 29 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging **==> picture [175 x 42] intentionally omitted <==** **==> picture [341 x 152] intentionally omitted <==** **==> picture [52 x 57] intentionally omitted <==** DS20001952C-page 30 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** **==> picture [466 x 597] intentionally omitted <==** **----- Start of picture text -----**<br> Note: For the most current package drawings, please see the Microchip Packaging Specification located at<br>http://www.microchip.com/packaging<br>**----- End of picture text -----**<br> DS20001952C-page 31 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging **==> picture [179 x 121] intentionally omitted <==** DS20001952C-page 32 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** **==> picture [409 x 215] intentionally omitted <==** **----- Start of picture text -----**<br> N<br>Pe i ee<br>NOTE 1<br>g E1<br>!<br>e e arity<br>1 2 3 ee e e qi |<br>nas ant | |<br>qi<br>D<br>E<br>A A2<br>L<br>c<br>A1 b1<br>b e eB<br>**----- End of picture text -----**<br> DS20001952C-page 33 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** **==> picture [384 x 262] intentionally omitted <==** **----- Start of picture text -----**<br> D<br>N<br>E<br>NA ST A N A E1 J AL<br>SN \ x ‘NI < As .<br>|SX SS | S \ Es a<br>FOUUUUUUBUU UL ASVy<br>1 2<br>b<br>NOTE 1<br>_ . | — | 7 e<br>A Se A2 c<br>φ<br>A1 STE r<br>L1 L<br>**----- End of picture text -----**<br> DS20001952C-page 34 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging **==> picture [181 x 174] intentionally omitted <==** DS20001952C-page 35 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **NOTES:** DS20001952C-page 36 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **APPENDIX A: REVISION HISTORY** ## **Revision C (July 2016)** The following is the list of modifications: 1. Added ESD data to **Section 1.0, Electrical Characteristics** . 2. Updated Table 2-1. 3. Updated package outline drawings. 4. Minor typographical errors ## **Revision B (February 2007)** 1. Changed Byte and Sequential Read in Figure 1-1 from “R” to “W”. 2. Table 2-4, Param No. 51 and 53: Changed from 450 to 600 and 500 to 600, respecively. 3. Added disclaimers to package outline drawings. 4. Updated package outline drawings. ## **Revision A (June 2005)** - Original release of this document. DS20001952C-page 37 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **NOTES:** DS20001952C-page 38 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **PRODUCT IDENTIFICATION SYSTEM** To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. |**Device:**<br>MCP23017:<br>16-Bit I/O Expander with I2C Interface<br>MCP23S17:<br>16-Bit I/O Expander with SPI Interface<br>**Temperature**<br>**Range:**<br>E<br>=<br>-40C to +125C (Extended)<br>**Package:**<br>ML<br>=<br>Plastic Quad Flat, No Lead Package, 6x6 mm<br>Body, QFN, 28-lead<br>SO<br>=<br>Plastic Small Outline, Wide, 7.50 mm Body, SOIC,<br>28-Lead<br>SP<br>=<br>Skinny Plastic Dual In-Line, 300 mil Body, SPDIP,<br>28-Lead<br>SS<br>=<br>Plastic Shrink Small Outline, 5.30 mm Body,<br>SSOP, 28-Lead<br>**Tape and Reel**<br>**Option:**<br>T<br>= Tape and Reel**(1)**<br>Blank = Tube<br>**PART NO.**<br>**X**<br>**/XX**<br>**Package**<br>**Temperature**<br>**Range**<br>**Device**<br>–<br>**X**<br>**(1)**<br>**Tape and Reel**<br>**Option**|**Examples:**<br>a)<br>MCP23017-E/ML:<br>Extended temperature,<br>28LD QFN package<br>b)<br>MCP23017T-E/ML: Extended temperature,<br>28LD QFN package,<br>Tape and Reel<br>c)<br>MCP23017-E/SP: Extended temperature ,<br>28LD SPDIP package<br>d)<br>MCP23017-E/SO:<br>Extended temperature,<br>28LD SOIC package<br>e)<br>MCP23017T-E/SO:<br>Extended temperature,<br>28LD SOIC package,<br>Tape and Reel<br>f)<br>MCP23017-E/SS:<br>Extended temperature,<br>28LD SSOP package<br>g)<br>MCP23017T-E/SS:<br>Extended temperature,<br>28LD SSOP package,<br>Tape and Reel<br>a)<br>MCP23S17-E/ML: Extended temperature,<br>28LD QFN package<br>b)<br>MCP23S17T-E/ML:<br>Extended temperature,<br>28LD QFN package,<br>Tape and Reel<br>c)<br>MCP23S17-E/SP: Extended temperature,<br>28LD SPDIP package<br>d)<br>MCP23S17-E/SO:<br>Extended temperature,<br>28LD SOIC package<br>e)<br>MCP23S17T-E/SO:<br>Extended temperature,<br>28LD SOIC package,<br>Tape and Reel<br>f)<br>MCP23S17-E/SS:<br>Extended temperature,<br>28LD SSOP package<br>g)<br>MCP23S17T-E/SS:<br>Extended temperature,<br>28LD SSOP package<br>Tape and Reel<br>**Note 1:**<br>Tape and Reel identifier only appears in the<br>catalog part number description. This identifier<br>is used for ordering purposes and is not<br>printed on the device package. Check with<br>your Microchip Sales Office for package<br>availability with the Tape and Reel option.| |---|---| DS20001952C-page 39 2005-2016 Microchip Technology Inc. **MCP23017/MCP23S17** ## **NOTES:** DS20001952C-page 40 2005-2016 Microchip Technology Inc. **Note the following details of the code protection feature on Microchip devices:** - Microchip products meet the specification contained in their particular Microchip Data Sheet. - Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. - There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. - Microchip is willing to work with the customer who is concerned about the integrity of their code. - Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE **.** Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. ## **Trademarks** The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. - SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. _Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC[®] MCUs and dsPIC[®] DSCs, KEELOQ[®] code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified._ ## **QUALITY MANAGEMENT SYSTEM** ## **CERTIFIED BY DNV** Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2005-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0755-3 ## **== == ISO/TS 16949** DS20001952C-page 41 2005-2016 Microchip Technology Inc. ## **Worldwide Sales and Service** ## **AMERICAS** **Corporate Office** 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com **Atlanta** Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 **Austin, TX** Tel: 512-257-3370 **Boston** Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 **Chicago** Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 **Cleveland** Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 **Dallas** Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 **Detroit** Novi, MI Tel: 248-848-4000 **Houston, TX** Tel: 281-894-5983 **Indianapolis** Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 **Los Angeles** Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 **New York, NY** Tel: 631-435-6000 **San Jose, CA** Tel: 408-735-9110 **Canada - Toronto** Tel: 905-695-1980 Fax: 905-695-2078 ## **ASIA/PACIFIC** ## **ASIA/PACIFIC** **Asia Pacific Office** **China - Xiamen** Tel: 86-592-2388138 Fax: 86-592-2388130 Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon **China - Zhuhai** Tel: 86-756-3210040 Fax: 86-756-3210049 **Hong Kong** Tel: 852-2943-5100 Fax: 852-2401-3431 **India - Bangalore** Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 **Australia - Sydney** Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 **India - New Delhi** Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 **China - Beijing** Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 **India - Pune** Tel: 91-20-3019-1500 **China - Chengdu** Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 **Japan - Osaka** Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 **China - Chongqing** Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 **Japan - Tokyo** Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 **China - Dongguan** Tel: 86-769-8702-9880 **Korea - Daegu** Tel: 82-53-744-4301 Fax: 82-53-744-4302 **China - Guangzhou** Tel: 86-20-8755-8029 **Korea - Seoul** Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 **China - Hangzhou** Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 **China - Hong Kong SAR** Tel: 852-2943-5100 Fax: 852-2401-3431 **Malaysia - Kuala Lumpur** Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 **China - Nanjing** Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 **Malaysia - Penang** Tel: 60-4-227-8870 Fax: 60-4-227-4068 **China - Qingdao** Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 **Philippines - Manila** Tel: 63-2-634-9065 Fax: 63-2-634-9069 **China - Shanghai** Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 **Singapore** Tel: 65-6334-8870 Fax: 65-6334-8850 **China - Shenyang** Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 **Taiwan - Hsin Chu** Tel: 886-3-5778-366 Fax: 886-3-5770-955 **China - Shenzhen** Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 **Taiwan - Kaohsiung** Tel: 886-7-213-7828 **China - Wuhan** Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 **Taiwan - Taipei** Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 **China - Xian Thailand - Bangkok** Tel: 86-29-8833-7252 Tel: 66-2-694-1351 Fax: 86-29-8833-7256 Fax: 66-2-694-1350 **Thailand - Bangkok** Tel: 66-2-694-1351 ## **EUROPE** **Austria - Wels** Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 **Denmark - Copenhagen** Tel: 45-4450-2828 Fax: 45-4485-2829 **France - Paris** Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 **Germany - Dusseldorf** Tel: 49-2129-3766400 **Germany - Karlsruhe** Tel: 49-721-625370 **Germany - Munich** Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 **Italy - Milan** Tel: 39-0331-742611 Fax: 39-0331-466781 **Italy - Venice** Tel: 39-049-7625286 **Netherlands - Drunen** Tel: 31-416-690399 Fax: 31-416-690340 **Poland - Warsaw** Tel: 48-22-3325737 **Spain - Madrid** Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 **Sweden - Stockholm** Tel: 46-8-5090-4654 **UK - Wokingham** Tel: 44-118-921-5800 Fax: 44-118-921-5820 06/23/16 DS20001952C-page 42 2005-2016 Microchip Technology Inc.
Updated at February 9, 2023
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