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MCP23009-E/SO
I/O Expander, 8bit, 3.4 MHz, I2C, 1.8 V, 5.5 V, SOIC
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: MICROCHIP
- Product type: I/O Expanders
- No. of Pins: 18Pins
- No. of I/O's: 8I/O's
- Bus Frequency: 3.4MHz
- IC Interface Type: I2C
- Chip Configuration: 8bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 1.8V
- Interface Case Style: SOIC
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 0.673 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **MCP23009/MCP23S09**
## ~~——~~ **8-Bit I/O Expander with Open-Drain Outputs**
## **Features:**
- 8-Bit Remote Bidirectional I/O Port:
- I/O Pins Default to Input
- Open-Drain Outputs:
- 5.5V Tolerant
- 25 mA Sink Capable (per Pin)
- 200 mA Total
- High-Speed I[2] C™ Interface ( **MCP23009** ):
- 100 kHz
- 400 kHz
- 3.4 MHz
- High-Speed SPI Interface ( **MCP23S09** ):
- 10 MHz
- Single Hardware Address Pin ( **MCP23009** ):
- Voltage input to allow up to eight devices on the bus
- Configurable Interrupt Source:
- Interrupt-on-Change from configured defaults or pin change
- Polarity inversion register to configure the polarity of the input port data
- External Reset Input
- Low Standby Current:
- 1 µA (-40°C TA +85°C)
- 6 µA (+85°C TA +125°C)
- Operating Voltage:
- 1.8V to 5.5V
- Available Packages:
- 16-Lead QFN (3x3x0.9 mm)
- 18-Lead PDIP (300 mil)
- 18-Lead SOIC (7.50 mm)
- 20-Lead SSOP (5.30 mm)
- Configurable Interrupt Output Pins:
- Configurable as active-high, active-low or open-drain
## **Block Diagram**
**==> picture [355 x 263] intentionally omitted <==**
**----- Start of picture text -----**<br>
MCP23S09<br>CS<br>SCK<br>SI<br>SPI<br>SO<br>MCP23009<br>SCL Serializer/<br>SDA I [2] C™ Deserializer GP0<br>GP1<br>GP2<br>RESET 8<br>GPIO GP3<br>INT GP4<br>Control<br>GP5<br>Multi-Bit<br>ADDR GP6<br>Decode<br>GP7<br>oe 8 [<br>Configuration/<br>Control<br>Registers<br>us<br>**----- End of picture text -----**<br>
DS20002121C-page 1
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **Package Types**
|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|**Package Types**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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||VDD<br>NC<br>SCL<br>SDA<br>ADDR<br>RESET||VSS<br>18<br>NC<br>17<br>NC<br>16<br>GP7<br>15<br>GP6<br>14<br>GP5<br>13<br>GP4<br>12<br>GP2<br>10<br>1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>GP3<br>11<br>9<br>VSS<br>18<br>NC<br>17<br>GP7<br>16<br>GP6<br>15<br>GP5<br>14<br>GP4<br>13<br>GP3<br>12<br>GP1<br>10<br>VDD<br>1<br>NC<br>2<br>C<br>S<br>3<br>SCK<br>4<br>SI<br>5<br>SO<br>6<br>RESET<br>7<br>INT<br>8<br>GP2<br>11<br>GP0<br>9<br>**MCP23009**<br>PDIP, SOIC<br>**MCP23S09**<br>PDIP/SOIC<br>2<br>VDD<br>SCL<br>VSS<br>NC<br>1<br>3<br>4||||||**MCP23009**<br>3 x 3 QFN*<br>GP3<br>GP2<br>SDA<br>GP1<br>ADDR<br>RESET<br>INT<br>GP0<br>GP7<br>GP6<br>GP5<br>GP4<br>EP<br>~~16~~<br>~~15~~<br>~~14~~<br>~~13~~<br>~~1~~2<br>11<br>10<br>9<br>5<br>6<br>7<br>8<br>17|VDD<br>NC<br>SCL<br>SDA<br>ADDR||||
||||1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9|||18<br>17<br>16<br>15<br>14<br>13<br>12<br>10<br>11||||||20<br>19<br>18<br>17<br>16<br>15<br>14<br>13<br>12<br>11<br>1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10||
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|||||||||2<br>1<br>3<br>4|EP<br>~~1~~2<br>11<br>10<br>9<br>5<br>6<br>7<br>8<br>17|||||
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|||||||||||RESET<br>INT<br>GP0<br>GP1<br>NC<br>VDD<br>CS<br>VSS<br>SCK||||
||<br>INT<br>GP0<br>GP1<br>|||||||||||||
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|||||VDD<br>NC<br>C<br>S<br>SCK<br>SI<br>SO<br>RESET<br>INT<br>GP0||||||||||
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||||||||||||2<br>1<br>3<br>4||~~16~~|
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|* Includes Exposed Thermal Pad (EP); seeTables 1-1and1-2.||||||||||||||
* Includes Exposed Thermal Pad (EP); see Tables 1-1 and 1-2.
DS20002121C-page 2
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **1.0 DEVICE OVERVIEW**
The MCP23X09 device provides 8-bit, general purpose parallel I/O expansion for I[2] C bus or SPI applications. The two devices differ only in the serial interface.
- MCP23009 – I[2] C interface
- MCP23S09 – SPI interface
The MCP23X09 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the input port register can be inverted with the polarity inversion register. All registers can be read by the system master.
The interrupt output can be configured to activate under two conditions (mutually exclusive):
1. When any input state differs from its corresponding input port register state. This is used to indicate to the system master that an input state has changed.
2. When an input state differs from a pre-configured register value (DEFVAL register).
The Interrupt Capture register captures port values at the time of the Interrupt, thereby saving the condition that caused the Interrupt.
The Power-On Reset (POR) sets the registers to their default values and initializes the device state machine.
The hardware address pin is used to determine the device address.
DS20002121C-page 3
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **1.1 Pin Descriptions**
## **TABLE 1-1: I[2] C™ PINOUT DESCRIPTION (MCP23009)**
||**Pin**<br>**Name**|**Pin Number**|**Pin Number**|**Pin Number**|**Pin**<br>**Type**|**Standard Function**|
|---|---|---|---|---|---|---|
|||**16-lead**<br>**QFN**|**18-lead**<br>**PDIP/SOIC**|**20-lead**<br>**SSOP**|||
||VDD|3|1|1|P|Power|
||NC|2|2, 16-17|2, 10-11,<br>18-19|—|Not connected|
||SCL|4|3|3|I|Serial clock input|
||SDA|5|4|4|I/O|Serial data I/O|
||ADDR|6|5|5|I|Hardware address pin allows up to eight slave devices on the<br>bus|
||RESET|7|6|6|I|Hardware reset|
||INT|8|7|7|O|Interrupt output for port. Can be configured as active-high,<br>active-low or open-drain.|
||GP0|9|8|8|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).<br>Can be enabled for interrupt on change and/or internal pull-up<br>resistor.|
||GP1|10|9|9|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).<br>Can be enabled for interrupt on change and/or internal pull-up<br>resistor.|
||GP2|11|10|12|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).<br>Can be enabled for interrupt on change and/or internal pull-up<br>resistor.|
||GP3|12|11|13|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).<br>Can be enabled for interrupt on change and/or internal pull-up<br>resistor.|
||GP4|13|12|14|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).<br>Can be enabled for interrupt on change and/or internal pull-up<br>resistor.|
||GP5|14|13|15|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).<br>Can be enabled for interrupt on change and/or internal pull-up<br>resistor.|
||GP6|15|14|16|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).<br>Can be enabled for interrupt on change and/or internal pull-up<br>resistor.|
||GP7|16|15|17|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).<br>Can be enabled for interrupt on change and/or internal pull-up<br>resistor.|
||VSS|1|18|20|P|Ground|
||EP|17|—|—|—|Exposed Thermal Pad (EP). Can be left floating or connected<br>to VSS.|
DS20002121C-page 4
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**TABLE 1-2: SPI PINOUT DESCRIPTION (MCP23S09)**
||**Pin**<br>**Name**|**Pin Number**|**Pin Number**|**Pin**<br>**Type**|**Standard Function**|
|---|---|---|---|---|---|
|||**16-lead**<br>**QFN**|**18-lead**<br>**PDIP/SOIC**|||
||VDD|3|1|P|Power(high-current capable)|
||NC|—|2, 17|—|Not connected|
||CS|4|3|I|Chipselect|
||SCK|2|4|I|Serial clock input|
||SI|5|5|I|Serial data input|
||SO|6|6|O|Serial data out|
||RESET|7|7|I|Hardware reset(must be externallybiased)|
||INT|8|8|O|Interrupt output for port. Can be configured as active-high, active-low or<br>open-drain.|
||GP0|9|9|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be<br>enabled for Interrupt-on-Change and/or internalpull-upresistor.|
||GP1|10|10|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be<br>enabled for Interrupt-on-Change and/or internalpull-upresistor.|
||GP2|11|11|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be<br>enabled for Interrupt-on-Change and/or internalpull-upresistor.|
||GP3|12|12|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be<br>enabled for Interrupt-on-Change and/or internalpull-upresistor.|
||GP4|13|13|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be<br>enabled for Interrupt-on-Change and/or internalpull-upresistor.|
||GP5|14|14|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be<br>enabled for Interrupt-on-Change and/or internalpull-upresistor.|
||GP6|15|15|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be<br>enabled for Interrupt-on-Change and/or internalpull-upresistor.|
||GP7|16|16|I/O|Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be<br>enabled for Interrupt-on-Change and/or internalpull-upresistor.|
||VSS|1|18|P|Ground(high-current capable)|
||EP|17|—|—|Exposed Thermal Pad(EP). Can be left floatingor connected to VSS.|
DS20002121C-page 5
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **1.2 Power-On Reset (POR)**
The on-chip POR circuit holds the device in reset until VDD has reached a high enough voltage to deactivate the POR circuit (i.e., release the device from reset). The maximum VDD rise time is specified in the electrical specification section.
When the device exits the POR condition (releases reset), the device operating parameters (i.e., voltage, temperature, serial bus frequency, etc.) must be met to ensure proper operation.
## **1.3 Serial Interface**
This block handles the functionality of the I[2] C (MCP23009) or SPI (MCP23S09) interface protocol. The MCP23X09 contains eleven (11) individual registers which can be addressed through the Serial Interface block (Table 1-3).
**TABLE 1-3: REGISTER ADDRESSES**
|**Address**|**Access to**|
|---|---|
|00h|IODIR|
|01h|IPOL|
|02h|GPINTEN|
|03h|DEFVAL|
|04h|INTCON|
|05h|IOCON|
|06h|GPPU|
|07h|INTF|
|08h|INTCAP(read-only)|
|09h|GPIO|
|0Ah|OLAT|
- **Sequential mode** enables automatic address pointer incrementing. When operating in Sequential mode, the MCP23X09 increments its address counter after each byte during the data transfer. The address pointer automatically rolls over to address 00h after accessing the last register.
These two modes are not to be confused with single writes/reads and continuous writes/reads, which are serial protocol sequences. For example, the device may be configured for Byte mode and the master may perform a continuous read. In this case, the MCP23X09 would not increment the address pointer and would repeatedly drive data from the same location.
## 1.3.2 I[2] C INTERFACE
## 1.3.2.1 I[2] C Write Operation
The I[2] C write operation includes the control byte and the register address sequence, as shown in the bottom of Figure 1-1. This sequence is followed by eight bits of data from the master and an Acknowledge (ACK) from the MCP23009. The operation is ended with a Stop (P) or Restart (SR) condition being generated by the master.
Data is written to the MCP23009 after every byte transfer. If a Stop or Restart condition is generated during a data transfer, the data will not be written to the MCP23009.
Both Byte mode and Sequential mode are supported by the MCP23009. If Sequential mode is enabled (default), the MCP23009 increments its address counter after each ACK during the data transfer.
## 1.3.2.2 I[2] C Read Operation
## 1.3.1 BYTE MODE AND SEQUENTIAL MODE
The MCP23X09 has the ability to operate in Byte mode or Sequential mode (IOCON.SEQOP). Byte mode and Sequential mode are not to be confused with I[2] C byte operations and sequential operations. The modes explained here relate to the device’s internal address pointer and whether or not it is incremented after each byte is clocked on the serial interface.
- **Byte mode** disables automatic address pointer incrementing. When operating in Byte mode, the MCP23X09 does not increment its internal address counter after each byte during the data transfer. This gives the ability to continually access the same address by providing extra clocks (without additional control bytes). This is useful for polling the GPIO register for data changes or for continually writing to the output latches.
I[2] C read operations include the control byte sequence, as shown in the bottom of Figure 1-1. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit equal to a logic one (R/W = `1` ). The MCP23009 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition.
## 1.3.2.3 I[2] C Sequential Write/Read
For sequential operations (Write or Read), instead of transmitting a Stop or Restart condition after the data transfer, the master clocks the next byte pointed to by the address pointer (see **Section 1.3.1 “Byte Mode and Sequential Mode”** for details regarding sequential operation control).
The sequence ends with the master sending a Stop or Restart condition.
The MCP23009 address pointer will roll over to address zero after reaching the last register address. Refer to Figure 1-1.
DS20002121C-page 6
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## 1.3.3 SPI INTERFACE
The MCP23S09 operates in Mode 0,0 and Mode 1,1. The difference between the two modes is the idle state of the clock.
- Mode 0,0: The idle state of the clock is low. Input data is latched on the rising edge of the clock; output data is driven on the falling edge of the clock.
- Mode 1,1: The idle state of the clock is high. Input data is latched on the rising edge of the clock; output data is driven on the falling edge of the clock.
## 1.3.3.1 SPI Write Operation
The SPI write operation is started by lowering CS. The write command (slave address with R/W bit cleared) is then clocked into the device. The opcode is followed by an address and at least one data byte.
## 1.3.3.2 SPI Read Operation
The SPI read operation is started by lowering CS. The SPI read command (slave address with R/W bit set) is then clocked into the device. The opcode is followed by an address, with at least one data byte being clocked out of the device.
## 1.3.3.3 SPI Sequential Write/Read
For sequential operations, instead of deselecting the device by raising CS, the master clocks the next byte pointed to by the address pointer (see **Section 1.3.1 “Byte Mode and Sequential Mode”** for details regarding sequential operation control).
The sequence ends by the raising of CS.
The MCP23S09 address pointer will roll over to address zero after reaching the last register address.
DS20002121C-page 7
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **FIGURE 1-1: MCP23009 I[2] C™ DEVICE PROTOCOL**
||||||||||||||||**DIN**<br>....|**DIN**<br>....|**DIN**<br>....|**DIN**<br>....||**DIN**|**DIN**|....|**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**<br>**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**|**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**<br>**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**|**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**<br>**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**|**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**<br>**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**|**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**<br>**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**|**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**<br>**P**<br>**DOUT**<br>**P**<br>**DIN**<br>**P**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**S**|**OP**|||**W**|||**ADDR**||||||||||||**DIN**|||||||||
||||||||||||||||||||||||||||||
||||||||||||||||||||||||||||||
||||||||||||||||**SR**|**OP**|||**R**|**DOUT**<br>|||||||||
||||||||||||||||||||||||||||||
||||||||||||||||||||||||||||||
|||||||||||||||||||||||....<br>....|||||||
||||||||||||||||**SR**|**OP**|||**W**|**ADDR**<br>|||||||||
||||||||||||||||||||||||||||||
||||||||||||||||**P**<br>**DOUT**<br>....|||||**DOUT**<br>**DOUT**<br>|||||||||
||||||||||||||||||||||||||||||
||**S**|**OP**||||**R**||||||||||||||**DOUT**|||||||||
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||||||||||||||||**SR**|**OP**|||**R**||||||||||
||||||||||||||||||||||||||||||
||||||||||||||||||||||||||||||
||||||||||||**SR**|||**OP**||**W**||**ADDR**||**DIN**||....|**DIN**||||**P**||
|||||||||||||||**P**|||||||||||||||
||||||||||||||||||||||||||||||
|**S**<br>**S**<br>**OP**<br>**S**<br>**S**<br>**OP**<br>Byte<br>Sequential<br>Byte<br>Sequential|||||||||||||||||||||||**P**<br>**DIN**<br>**DOUT**<br>....<br>**P**<br>**P**<br>**P**||||||
|||||||**S**||**OP**||||**W**||**ADDR**|||||**DIN**||||||||||
||||||||||||||||||||||||||||||
|||||||**S**||**OP**||||**W**||**ADDR**|||||||||**DIN**||||||
||||||||||||||||||||||||||||||
||||**S**|**OP**|||||**W**|||||||**SR**||**OP**||**R**|**DOUT**||||||||
||||||||||||||||||||||||||||||
||||||||||||||||||||||||||||||
||||**S**|**OP**|||||**W**|**ADDR**||||||**SR**||**OP**||**R**|**DOUT**||....|**DOUT**||||**P**|
||||||||||||||||||||||||||||||
|||||**S**<br>**P**<br>**SR**<br>**W**<br>**R**<br>- Start<br>- Restart<br>- Stop<br>- Write<br>- Read<br>**Legend:**||||||||||||||**OP**<br>**ADDR**<br>**DOUT**<br>**DIN**<br>- Device opcode<br>- Device address<br>- Data out from**MCP23009**<br>- Data in to**MCP23009**|||||||||||
DS20002121C-page 8
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **1.4 Multi-Bit Address Decoder**
The ADDR pin is used to set the slave address of the MCP23009 (I[2] C only) to allow up to eight devices on the bus using only a single pin. Typically, this would require three pins.
The multi-bit Address Decoder employs a basic FLASH ADC architecture (Figure 1-4). The seven comparators generate eight unique values based on the analog input. This value is converted to a 3-bit code which corresponds to the address bits (A2, A1, A0) in the serial OPCODE.
## 1.4.1 CALCULATING VOLTAGE ON ADDR
When calculating the required voltage on the ADDR pin (V2), the set point should be the mid point of the LSb of the ADC.
The examples in Figures 1-2 and 1-3 show how to determine the mid-point voltage (V2) and the range of voltages based on a voltage divider circuit. The maximum tolerance is 20%, however, it is recommended to use 5% tolerance worst-case (10% total tolerance).
**Sequence of operation (see Figure 1-5 for timings):**
1. Upon power-up (after VDD stabilizes), the module becomes active after time tADEN. Note that the analog value on the ADDR pin must be stable before this point to ensure accurate address assignment.
2. The 3-bit address is latched after tADDRLAT.
3. The module powers down after the first rising edge of the serial clock is detected (tADDIS).
Once the address bits are latched, the device will keep the slave address until a POR or Reset condition occurs.
**FIGURE 1-2: VOLTAGE DIVIDER EXAMPLE**
**==> picture [340 x 260] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD VDD<br>ADDR MCP23009 Only<br>A0<br>R1<br>A1<br>A2<br>V2<br>R2<br>VSS<br>VSS<br>**----- End of picture text -----**<br>
DS20002121C-page 9
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **FIGURE 1-3: VOLTAGE AND CODE EXAMPLE**
Assume: n = A2, A1, A0 in opcode ratio = R2/(R1+R2) V2 = voltage on ADDR pin V2(min) = V2 – (VDD/8) x %tolerance V2(max) = V2 + (VDD/8) x %tolerance
|**VDD = 1.8**|**VDD = 1.8**|**VDD = 1.8**|**VDD = 1.8**|**VDD = 1.8**|**10% Tolerance(total)**|**10% Tolerance(total)**|
|---|---|---|---|---|---|---|
|**n**|**R2 = 2n + 1 **|**R1 = 16 – R2 **|**R2/(R1 + R2)**|**V2**|**V2(min)**|**V2(max)**|
|0|1|15|0.0625|**0.113**|0.00|0.14|
|1|3|13|0.1875|**0.338**|0.32|0.36|
|2|5|11|0.3125|**0.563**|0.54|0.59|
|3|7|9|0.4375|**0.788**|0.77|0.81|
|4|9|7|0.5625|**1.013**|0.99|1.04|
|5|11|5|0.6875|**1.238**|1.22|1.26|
|6|13|3|0.8125|**1.463**|1.44|1.49|
|7|15|1|0.9375|**1.688**|1.67|1.80|
|**VDD = 2.7**|**VDD = 2.7**|**VDD = 2.7**|**VDD = 2.7**|**VDD = 2.7**|**10% Tolerance(total)**|**10% Tolerance(total)**|
|---|---|---|---|---|---|---|
|**n**|**R2 = 2n + 1 **|**R1 = 16 – R2 **|**R2/(R1 + R2)**|**V2**|**V2(min)**|**V2(max)**|
|0|1|15|0.0625|**0.169**|0.00|0.19|
|1|3|13|0.1875|**0.506**|0.48|0.53|
|2|5|11|0.3125|**0.844**|0.82|0.87|
|3|7|9|0.4375|**1.181**|1.16|1.20|
|4|9|7|0.5625|**1.519**|1.50|1.54|
|5|11|5|0.6875|**1.856**|1.83|1.88|
|6|13|3|0.8125|**2.194**|2.17|2.22|
|7|15|1|0.9375|**2.531**|2.51|2.70|
|**VDD = 3.3**|**VDD = 3.3**|**VDD = 3.3**|**VDD = 3.3**|**VDD = 3.3**|**10% Tolerance(total)**|**10% Tolerance(total)**|
|---|---|---|---|---|---|---|
|**n**|**R2 = 2n + 1 **|**R1 = 16 – R2 **|**R2/(R1 + R2)**|**V2**|**V2(min)**|**V2(max)**|
|0|1|15|0.0625|**0.206**|0.00|0.23|
|1|3|13|0.1875|**0.619**|0.60|0.64|
|2|5|11|0.3125|**1.031**|1.01|1.05|
|3|7|9|0.4375|**1.444**|1.42|1.47|
|4|9|7|0.5625|**1.856**|1.83|1.88|
|5|11|5|0.6875|**2.269**|2.25|2.29|
|6|13|3|0.8125|**2.681**|2.66|2.70|
|7|15|1|0.9375|**3.094**|3.07|3.30|
|**VDD = 5.5**|**VDD = 5.5**|**VDD = 5.5**|**VDD = 5.5**|**VDD = 5.5**|**10% Tolerance(total)**|**10% Tolerance(total)**|
|---|---|---|---|---|---|---|
|**n**|**R2 = 2n + 1 **|**R1 = 16 – R2 **|**R2/(R1 + R2)**|**V2**|**V2(min)**|**V2(max)**|
|0|1|15|0.0625|**0.344**|0.00|0.37|
|1|3|13|0.1875|**1.031**|1.01|1.05|
|2|5|11|0.3125|**1.719**|1.70|1.74|
|3|7|9|0.4375|**2.406**|2.38|2.43|
|4|9|7|0.5625|**3.094**|3.07|3.12|
|5|11|5|0.6875|**3.781**|3.76|3.80|
|6|13|3|0.8125|**4.469**|4.45|4.49|
|7|15|1|0.9375|**5.156**|5.13|5.50|
DS20002121C-page 10
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **FIGURE 1-4: FLASH ADC BLOCK DIAGRAM**
**==> picture [379 x 354] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>ADDR<br>+- addr_out 6 d q addr<6:0> i2c_addr<2:0><br>a dc_en adc_en<br>en<br>+ addr_out 5<br>-<br>a dc_en reset<br>+- addr_out 4 '0' d set q adc_en<br>adc_en<br>i2c_clk<br>+ addr_out 3<br>-<br>adc_en<br>+ addr_out 2<br>-<br>adc_en<br>+ addr_out 1<br>-<br>a dc_en<br>+ addr_out 0<br>-<br>a dc_en<br>adc_en<br>VSS<br>**----- End of picture text -----**<br>
DS20002121C-page 11
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **FIGURE 1-5: HARDWARE ADDRESS DECODE TIMING**
**==> picture [443 x 171] intentionally omitted <==**
**----- Start of picture text -----**<br>
tADEN<br>VDD<br>tADDRLAT<br>adc_en<br>i2c_addr[2:0]<br>tADDIS<br>i2c_clk<br>**----- End of picture text -----**<br>
## 1.4.2 ADDRESSING I[2] C DEVICES (MCP23009)
The MCP23009 is a slave I[2] C device that supports 7-bit slave addressing, with the read/write bit filling out the control byte. The slave address contains four fixed bits and three user-defined hardware address bits (configured via the ADDR pin). Figure 1-6 shows the control byte format.
## 1.4.3 ADDRESSING SPI DEVICES (MCP23S09)
The MCP23S09 is a slave SPI device. The slave address contains seven fixed bits (no address bits), with the read/write bit filling out the control byte. Figure 1-7 shows the control byte format.
## **FIGURE 1-6: I[2] C™ CONTROL BYTE FORMAT**
**==> picture [212 x 98] intentionally omitted <==**
**----- Start of picture text -----**<br>
Control Byte<br>S 0 1 0 0 A2 A1 A0 R/W ACK<br>Slave Address<br>Start R/W bit<br>bit ACK bit<br>R/W = 0 = write<br>R/W = 1 = read<br>**----- End of picture text -----**<br>
## **FIGURE 1-7: SPI CONTROL BYTE FORMAT**
**==> picture [209 x 111] intentionally omitted <==**
**----- Start of picture text -----**<br>
CS<br>Control Byte<br>0 1 0 0 0 0 0 R/W<br>Slave Address<br>R/W bit<br>R/W = 0 = write<br>R/W = 1 = read<br>**----- End of picture text -----**<br>
DS20002121C-page 12
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **FIGURE 1-8:**
## **I[2] C™ ADDRESSING REGISTERS**
S 0 1 0 0 A2 A1 A0 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK R/W = `0` Device Opcode Register Address The ACKs are provided by the MCP23009.
## **FIGURE 1-9: SPI ADDRESSING REGISTERS**
|||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|CS||||||||||||||||||
||||||||||A7<br>A6<br>A5<br>A4<br>A3<br>A2<br>A1<br>A0<br>Register Address|||||||||
|||||||||||||||||||
||0|1|0|0|0|0|0|R/W|A7|A6|A5|A4|A3|A2|A1|A0||
||Device Opcode||||||||Register Address|||||||||
DS20002121C-page 13
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **1.5 GPIO Port**
The GPIO module is a general purpose 8-bit wide bidirectional port.
The outputs are open-drain.
The GPIO module contains the data ports (GPIOn), internal pull-up resistors and the output latches (OLATn).
The pull-up resistors are individually configured and can be enabled when the pin is configured as an input or output.
Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port.
Writing to the GPIOn register actually causes a write to the latches (OLATn). Writing to the OLATn register forces the associated output drivers to drive to the level in OLATn. Pins configured as inputs turn off the associated output driver and put it in high impedance.
DS20002121C-page 14
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **1.6 Configuration and Control Registers**
There are eleven (11) registers associated with the MCP23X09, as shown in Table 1-4.
## **TABLE 1-4: CONFIGURATION AND CONTROL REGISTERS**
|**Register**<br>**Name**|**Address**<br>**(hex)**|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|**POR/RST**<br>**Value**|
|---|---|---|---|---|---|---|---|---|---|---|
|IODIR|00|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|`1111 1111`|
|IPOL|01|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|`0000 0000`|
|GPINTEN|02|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|`0000 0000`|
|DEFVAL|03|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|`0000 0000`|
|INTCON|04|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|`0000 0000`|
|IOCON|05|—|—|SEQOP|—|—|ODR|INTPOL|INTCC|`0000 0000`|
|GPPU|06|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|`0000 0000`|
|INTF|07|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INTO|`0000 0000`|
|INTCAP|08|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|`0000 0000`|
|GPIO|09|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|`0000 0000`|
|OLAT|0A|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|`0000 0000`|
DS20002121C-page 15
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## 1.6.1 I/O DIRECTION REGISTER
This register controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output.
## **REGISTER 1-1:**
## **IODIR – I/O DIRECTION REGISTER**
|**REGISTER 1-1:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-1:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-1:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-1:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-1:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-1:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-1:**<br>**IODIR – I/O DIRECTION REGISTER**|**REGISTER 1-1:**<br>**IODIR – I/O DIRECTION REGISTER**|
|---|---|---|---|---|---|---|---|
|||||||||
|R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1<br>R/W-1||||||||
|IO7|IO6|IO5|IO4|IO3|IO2|IO1|IO0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
|||||||||
bit 7-0 **IO<7:0>:** Controls the direction of data I/O <7:0>
- `1` = Pin is configured as an input
- `0` = Pin is configured as an output
DS20002121C-page 16
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## 1.6.2 INPUT POLARITY REGISTER
This register allows the user to configure the polarity on the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will reflect the inverted value on the pin.
## **REGISTER 1-2:**
## **IPOL – INPUT POLARITY PORT REGISTER**
|**REGISTER 1-2:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-2:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-2:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-2:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-2:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-2:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-2:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|**REGISTER 1-2:**<br>**IPOL – INPUT POLARITY PORT REGISTER**|
|---|---|---|---|---|---|---|---|
|||||||||
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|IP7|IP6|IP5|IP4|IP3|IP2|IP1|IP0|
|bit 7<br>bit 0||||||||
|**Legend:**||||
|---|---|---|---|
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n = Value at POR|‘1’ = Bit is set|‘0’ = Bit is cleared|x = Bit is unknown|
bit 7-0
**IP<7:0>:** Controls the polarity inversion of the input pins <7:0>
- `1` = GPIO register bit will reflect the opposite logic state of the input pin
- `0` = GPIO register bit will reflect the same logic state of the input pin
DS20002121C-page 17
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## 1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER
The GPINTEN register controls the Interrupt-on-Change feature for each pin.
If a bit is set, the corresponding pin is enabled for Interrupt-on-Change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for Interrupt-on-Change.
## **REGISTER 1-3:**
## **GPINTEN – INTERRUPT-ON-CHANGE PINS**
|**REGISTER 1-3:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-3:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-3:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-3:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-3:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-3:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-3:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|**REGISTER 1-3:**<br>**GPINTEN – INTERRUPT-ON-CHANGE PINS**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|GPINT7|GPINT6|GPINT5|GPINT4|GPINT3|GPINT2|GPINT1|GPINT0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
bit 7-0 **GPINT<7:0>:** General-purpose I/O interrupt-on-change pins <7:0> `1` = Enable GPIO input pin for Interrupt-on-Change event
`0` = Disable GPIO input pin for Interrupt-on-Change event
Refer to the INTCON and DEFVAL registers.
DS20002121C-page 18
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## 1.6.4 DEFAULT COMPARE REGISTER FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the DEFVAL register. If enabled (via GPINTEN and INTCON) to compare against the DEFVAL register, an opposite value on the associated pin will cause an Interrupt to occur.
## **REGISTER 1-4: DEFVAL – DEFAULT VALUE REGISTER**
|**REGISTER 1-4:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-4:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-4:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-4:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-4:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-4:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-4:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|**REGISTER 1-4:**<br>**DEFVAL – DEFAULT VALUE REGISTER**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|DEF7|DEF6|DEF5|DEF4|DEF3|DEF2|DEF1|DEF0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**||||
|---|---|---|---|
|R = Readable bit|W = Writable bit|U = Unimplemented bit, read as ‘0’||
|-n = Value at POR|‘1’ = Bit is set|‘0’ = Bit is cleared|x = Bit is unknown|
bit 7-0 **DEF<7:0>:** Sets the compare value for pins configured for Interrupt-on-Change from defaults <7:0>. Refer to the INTCON register.
If the associated pin level is the opposite from the register bit, an Interrupt occurs.
Refer to the INTCON and GPINTEN registers.
DS20002121C-page 19
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## 1.6.5 INTERRUPT CONTROL REGISTER
The INTCON register controls how the associated pin value is compared for the Interrupt-on-Change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value.
## **REGISTER 1-5:**
## **INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**
|**REGISTER 1-5:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-5:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-5:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-5:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-5:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-5:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-5:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|**REGISTER 1-5:**<br>**INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER**|
|---|---|---|---|---|---|---|---|
|||||||||
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|IOC7|IOC6|IOC5|IOC4|IOC3|IOC2|IOC1|IOC0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
|||||||||
bit 7-0 **IOC<7:0>:** Controls how the associated pin value is compared for Interrupt-on-Change <7:0>. `1` = Pin value is compared against the associated bit in the DEFVAL register
`0` = Pin value is compared against the previous pin value
Refer to the DEFVAL and GPINTEN registers.
DS20002121C-page 20
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## 1.6.6 CONFIGURATION REGISTER
The Interrupt Polarity (INTPOL) bit sets the polarity of the INT pin. This bit is functional only when the ODR bit is cleared, configuring the INT pin as active push-pull.
The Sequential Operation (SEQOP) bit controls the incrementing function of the address pointer. If the address pointer is disabled, the address pointer does not automatically increment after each byte is clocked during a serial transfer. This feature is useful when it is desired to continuously poll (read) or modify (write) a register.
The Interrupt Clearing Control (INTCC) bit configures how Interrupts are cleared. When set (INTCC = `1` ), the Interrupt is cleared when the INTCAP register is read. When cleared (INTCC = `0` ), the Interrupt is cleared when the GPIO register is read.
The Interrupt can only be cleared when the Interrupt condition is inactive. Refer to **Section 1.7.4 “Clearing Interrupts”** for details.
The Open-Drain (ODR) control bit enables/disables the INT pin for open-drain configuration.
## **REGISTER 1-6:**
## **IOCON – I/O EXPANDER CONFIGURATION REGISTER**
|**REGISTER 1-6:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-6:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-6:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-6:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-6:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-6:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-6:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|**REGISTER 1-6:**<br>**IOCON – I/O EXPANDER CONFIGURATION REGISTER**|
|---|---|---|---|---|---|---|---|
|U-0<br>U-0<br>R/W-0<br>U-0<br>U-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|—|—|SEQOP|—|—|ODR|INTPOL|INTCC|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
- bit 7 **Unimplemented** : Read as ‘ `0` ’ bit 6 **Unimplemented** : Read as ‘ `0` ’ bit 5 **SEQOP:** Sequential Operation mode bit. `1` = Sequential operation disabled, address pointer does not increment `0` = Sequential operation enabled, address pointer increments
- bit 4 **Unimplemented** : Read as ‘ `0` ’ bit 3 **Unimplemented:** Read as ‘ `0` ’ bit 2 **ODR:** Configures the INT pin as an open-drain output. `1` = Open-drain output (overrides the INTPOL bit) `0` = Active driver output (INTPOL bit sets the polarity)
- bit 1 **INTPOL:** Sets the polarity of the INT output pin. `1` = Active-High `0` = Active-Low
- bit 0 **INTCC:** Interrupt Clearing Control `1` = Reading INTCAP register clears the Interrupt `0` = Reading GPIO register clears the Interrupt
DS20002121C-page 21
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## 1.6.7 PULL-UP RESISTOR CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the port pins. If a bit is set, the corresponding port pin is internally pulled up with an internal resistor.
## **REGISTER 1-7:**
## **GPPU – GPIO PULL-UP RESISTOR REGISTER**
|**REGISTER 1-7:**<br>**GPPU – GPIO PULL-UP RESISTOR REGISTER**|**REGISTER 1-7:**<br>**GPPU – GPIO PULL-UP RESISTOR REGISTER**|**REGISTER 1-7:**<br>**GPPU – GPIO PULL-UP RESISTOR REGISTER**|**REGISTER 1-7:**<br>**GPPU – GPIO PULL-UP RESISTOR REGISTER**|**REGISTER 1-7:**<br>**GPPU – GPIO PULL-UP RESISTOR REGISTER**|**REGISTER 1-7:**<br>**GPPU – GPIO PULL-UP RESISTOR REGISTER**|**REGISTER 1-7:**<br>**GPPU – GPIO PULL-UP RESISTOR REGISTER**|**REGISTER 1-7:**<br>**GPPU – GPIO PULL-UP RESISTOR REGISTER**|
|---|---|---|---|---|---|---|---|
|||||||||
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|PU7|PU6|PU5|PU4|PU3|PU2|PU1|PU0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
|||||||||
bit 7-0 **PU<7:0>:** Controls the internal pull-up resistors on each pin (when configured as an input or output) <7:0>.
`1` = Pull-Up enabled
`0` = Pull-Up disabled
**==> picture [469 x 283] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 1-10: TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS<br>GPIO Pin Internal Pull-Up Current vs. VDD<br>400<br>350<br>T = -40°C<br>300<br>250<br>T = +25°C<br>200<br>150<br>T = +125°C<br>100<br>T = +85°C<br>50<br>0<br>1.5 2 2.5 3 3.5 4 4.5 5 5.5<br>V<br>DD (V)<br>IPU (µA)<br>**----- End of picture text -----**<br>
DS20002121C-page 22
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## 1.6.8 INTERRUPT FLAG REGISTER
The INTF register reflects the Interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A set bit indicates that the associated pin caused the Interrupt.
This register is read-only. Writes to this register will be ignored.
## **REGISTER 1-8:**
## **INTF – INTERRUPT FLAG REGISTER**
|**REGISTER 1-8:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-8:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-8:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-8:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-8:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-8:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-8:**<br>**INTF – INTERRUPT FLAG REGISTER**|**REGISTER 1-8:**<br>**INTF – INTERRUPT FLAG REGISTER**|
|---|---|---|---|---|---|---|---|
|R-0<br>R-0<br>R-0<br>R-0<br>R-0<br>R-0<br>R-0<br>R-0||||||||
|INT7|INT6|INT5|INT4|INT3|INT2|INT1|INT0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
bit 7-0 **INT<7:0>:** Reflects the interrupt condition on the port. Will reflect the change only if interrupts are enabled (GPINTEN) <7:0>.
- `1` = Pin caused Interrupt
- `0` = Interrupt not pending
DS20002121C-page 23
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## 1.6.9 INTERRUPT CAPTURE REGISTER
The INTCAP register captures the GPIO port value at the time the Interrupt occurred. The register is read-only’ and is updated only when an Interrupt occurs. The register will remain unchanged until the Interrupt is cleared via a read of INTCAP or GPIO.
## **REGISTER 1-9:**
## **INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**
|**REGISTER 1-9:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-9:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-9:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-9:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-9:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-9:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-9:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|**REGISTER 1-9:**<br>**INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER**|
|---|---|---|---|---|---|---|---|
|R-x<br>R-x<br>R-x<br>R-x<br>R-x<br>R-x<br>R-x<br>R-x||||||||
|ICP7|ICP6|ICP5|ICP4|ICP3|ICP2|ICP1|ICP0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
bit 7-0 **ICP<7:0>:** Reflects the logic level on the port pins at the time of Interrupt due to pin change <7:0>. `1` = Logic-High
`0` = Logic-Low
DS20002121C-page 24
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## 1.6.10 PORT REGISTER
The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register.
## **REGISTER 1-10:**
## **GPIO – GENERAL PURPOSE I/O PORT REGISTER**
|**REGISTER 1-10:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-10:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-10:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-10:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-10:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-10:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-10:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|**REGISTER 1-10:**<br>**GPIO – GENERAL PURPOSE I/O PORT REGISTER**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|GP7|GP6|GP5|GP4|GP3|GP2|GP1|GP0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
|||||||||
bit 7-0 **GP<7:0>:** Reflects the logic level on the pins <7:0>.
`1` = Logic-High
- `0` = Logic-Low
DS20002121C-page 25
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## 1.6.11 OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs.
## **REGISTER 1-11: OLAT – OUTPUT LATCH REGISTER 0**
|**REGISTER 1-11:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-11:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-11:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-11:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-11:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-11:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-11:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|**REGISTER 1-11:**<br>**OLAT – OUTPUT LATCH REGISTER 0**|
|---|---|---|---|---|---|---|---|
|R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0<br>R/W-0||||||||
|OL7|OL6|OL5|OL4|OL3|OL2|OL1|OL0|
|bit 7<br>bit 0||||||||
|||||||||
|**Legend:**<br>R = Readable bit<br>W = Writable bit<br>U = Unimplemented bit, read as ‘0’<br>-n = Value at POR<br>‘1’ = Bit is set<br>‘0’ = Bit is cleared<br>x = Bit is unknown||||||||
bit 7-0 **OL<7:0>:** Reflects the logic level on the output latch <7:0>.
- `1` = Logic-High
- `0` = Logic-Low
DS20002121C-page 26
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **1.7 Interrupt Logic**
If enabled, the MCP23X09 activates the INT interrupt output when one of the port pins changes state or when a pin does not match the pre-configured default. Each pin is individually configurable as follows:
- Enable/disable interrupt via GPINTEN
- Can Interrupt on either pin change or change from default as configured in DEFVAL
Both conditions are referred to as Interrupt-on-Change (IOC).
The Interrupt Control Module uses the following registers/bits:
- GPINTEN – Interrupt enable register
## 1.7.4 CLEARING INTERRUPTS
The Interrupt will remain active until the INTCAP or GPIO register is read (depending on IOCON.INTCC). Writing to these registers will not affect the Interrupt. The Interrupt condition will be cleared after the LSb of the data is clocked out during a read operation of GPIO or INTCAP (depending on IOCON.INTCC).
**Note:** Assuming IOCON.INTCC = `0` (INT cleared on GPIO read), the value in INTCAP can be lost if GPIO is read before INTCAP while another IOC is pending. After reading GPIO, the Interrupt will clear and then set due to the pending IOC, causing the INTCAP register to update.
- INTCON – Controls the source for the IOC
- DEFVAL – Contains the register default for IOC operation
- IOCON (ODR and INTPOL) – Configures the INT pin as push-pull, open-drain and active level (high or low).
## 1.7.1 IOC FROM PIN CHANGE
If enabled, the MCP23X09 will generate an Interrupt if a mismatch condition exists between the current port value and the previous port value. Only IOC-enabled pins will be compared. See the GPINTEN and INTCON registers.
## 1.7.2 IOC FROM REGISTER DEFAULT
If enabled, the MCP23X09 will generate an Interrupt if a mismatch occurs between the DEFVAL register and the port. Only IOC-enabled pins will be compared. See the GPINTEN, INTCON and DEFVAL registers.
## 1.7.3 INTERRUPT OPERATION
The INT interrupt output can be configured as active-low, active-high or open-drain via the IOCON register.
Only those pins that are configured as an input (IODIR register) with Interrupt-on-Change (IOC) enabled (GPINTEN register) can cause an Interrupt. Pins configured as an output have no effect on the interrupt output pin.
Input change activity on a port input pin that is enabled for IOC will generate an internal device Interrupt and the device will capture the value of the port and copy it into INTCAP.
The first Interrupt event will cause the port contents to be copied into the INTCAP register. Subsequent Interrupt conditions on the port will not cause an Interrupt to occur as long as the Interrupt is not cleared by a read of INTCAP or GPIO.
DS20002121C-page 27
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## 1.7.5 INTERRUPT CONDITIONS
There are two possible configurations to cause Interrupts (configured via INTCON):
1. Pins configured for **Interrupt-on-Pin-Change** will cause an Interrupt to occur if a pin changes to the opposite state. The default state is reset after an Interrupt occurs. For example, an Interrupt occurs by an input changing from `1` to `0` . The new initial state for the pin is a logic `0` .
2. Pins configured for **Interrupt-on-Change from register value** will cause an Interrupt to occur if the corresponding input pin differs from the register bit. The Interrupt condition will remain as long as the condition exists, regardless of whether the INTAP or GPIO is read.
See Figures 1-11 and 1-12 for more information on the interrupt operations.
## **FIGURE 1-11:**
## **INTERRUPT-ON-PIN-CHANGE**
**==> picture [184 x 97] intentionally omitted <==**
**----- Start of picture text -----**<br>
GPx<br>INT ACTIVE ACTIVE<br>Port value Read GPIO Port value<br>is captured or INTCAP is captured<br>into INTCAP into INTCAP<br>**----- End of picture text -----**<br>
**FIGURE 1-12: INTERRUPT-ON-CHANGE FROM REGISTER DEFAULT**
**==> picture [196 x 206] intentionally omitted <==**
**----- Start of picture text -----**<br>
DEFVAL<br>GP: 7 6 5 4 3 2 1 0<br>X X X X X 1 X X<br>GP2<br>INT ACTIVE AC T IVE<br>Port value<br>is captured Read GPIO<br>into INTCAP or INTCAP<br>(INT clears only if Interrupt<br>condition does not exist.)<br>**----- End of picture text -----**<br>
DS20002121C-page 28
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **2.0 ELECTRICAL CHARACTERISTICS**
## **Absolute Maximum Ratings[(†)]**
|Ambient temperature under bias.............................................................................................................-40°C to +125°C|
|---|
|Storage temperature .............................................................................................................................. -65°C to +150°C|
|Voltage on VDDwith respect to VSS......................................................................................................... -0.3V to +7.0V|
|Voltage on RESET<br>with respect to VSS..................................................................................................... -0.3V to +14V|
|Voltage on all other pins with respect to VSS(except VDDand GPIOA/B) ..................................... -0.6V to (VDD+ 0.6V)|
|Voltage on GPIO Pins .................................................................................................................................. -0.6V to 5.5V|
|Total power dissipation**(Note 1)**..........................................................................................................................700 mW|
|Maximum current out of VSSpin ...........................................................................................................................200 mA|
|Maximum current into VDDpin ..............................................................................................................................125 mA|
|Input clamp current, IIK(VI< 0 or VI> VDD)20 mA|
|Output clamp current, IOK(VO< 0 or VO> VDD)20 mA|
|Maximum output current sunk by any output pin ....................................................................................................25 mA|
|Maximum output current sunk by any output pin (VDD= 1.8V)...............................................................................10 mA|
|ESD protection on all pins (HBM:MM) ..............................................................................................................4 kV:400V|
|†|**Notice:**Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage|
|---|---|
||to the device. This is a stress rating only and functional operation of the device at those or any other|
||conditions above those indicated in the operation listings of this specification is not implied. Exposure to|
||maximum rating conditions for extended periods may affect device reliability.|
**Note 1:** Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL).
DS20002121C-page 29
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **2.1 DC Characteristics**
||**DC Characteristics**|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|
|---|---|---|---|---|---|---|---|
|**Param.**<br>**No.**|<br>**Characteristic**|**Sym.**|**Min.**|**Typ.(2)**|**Max.**|**Units**|**Conditions**|
|D001|SupplyVoltage|VDD|1.8|—|5.5|V||
|D002|VDDStart Voltage<br>to Ensure Power-On Reset|VPOR|—|VSS|—|V||
|D003|VDDRise Rate to Ensure<br>Power-On Reset|SVDD|0.05|—|—|V/ms|Design guidance only.<br>Not tested.|
|D004|SupplyCurrent|IDD|—|—|1|mA|SCL/SCK = 1 MHz|
|D005|Standby (Idle) current|IDDS|—|—|1|µA|–40°CTA+85°C|
||||—|—|6|µA|+85°CTA+125°C|
||**Input Low-Voltage**|||||||
|D031|CS<br>, GPIO,SCL/SCK,<br>SDA, SI, RESET|VIL|VSS|—|0.2 VDD|V||
||**Input High-Voltage**|||||||
|D041|CS<br>,SCL/SCK, SDA, SI,<br>RESET|VIH|0.8 VDD|—|VDD|V||
||GPIO|VIH|0.8 VDD|—|5.5|V||
||**Input Leakage Current**|||||||
|D060|I/Oportpins|IIL|—|—|±1|µA|VSSVPINVDD|
||**Output Leakage Current**|||||||
|D065|I/Oportpins|ILO|—|—|±1|µA|VSSVPINVDD|
|D070|GPIO internal pull-up<br>current|IPU|—|220|—|µA|VDD= 5V, GP Pins = VSS<br>**(Note 1)**|
||**Output Low-Voltage**|||||||
|D080|GPIO|VOL|—|—|0.6|V|IOL= 8.5 mA, VDD= 4.5V<br>(open-drain)|
||INT||—|—|0.6||IOL= 1.6 mA, VDD= 4.5V|
||SO, SDA||—|—|0.6||IOL= 3.0 mA, VDD= 1.8V|
||SDA||—|—|0.8||IOL= 3.0 mA, VDD= 4.5V|
||**Output High-Voltage**|||||||
|D090|INT, SO|VOH|VDD– 0.7|—|—|V|IOH= -3.0 mA, VDD= 4.5V|
||||VDD– 0.7|—|—||IOH= -400µA, VDD= 1.8V|
||**Capacitive Loading Specs on Output Pins**|||||||
|D101|GPIO, SO, INT|CIO|—|—|50|pF|These are load conditions for<br>the timing specifications.<br>Refer toFigure 2-1.<br>SDA test condition is 135pF.|
|D102|SDA|CB|—|—|400**(1)**|||
- **Note 1:** This parameter is characterized, not 100% tested.
- **2:** Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.
DS20002121C-page 30
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **2.2 AC CHARACTERISTICS**
## **FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS**
**==> picture [286 x 102] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>Pin<br>1 k<br>SCL and 50 pF<br>SDA pin<br>MCP23009<br>135 pF<br>**----- End of picture text -----**<br>
## **FIGURE 2-2: RESET AND DEVICE RESET TIMER TIMING**
**==> picture [444 x 172] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>RESET<br>30 32<br>31<br>Internal<br>RESET<br>34<br>Output pin<br>**----- End of picture text -----**<br>
## **TABLE 2-1: RESET AND DEVICE RESET TIMER REQUIREMENTS**
|**AC Characteristics**|**AC Characteristics**|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|
|---|---|---|---|---|---|---|---|
|**Param.**<br>**No.**|**Sym.**|**Characteristic**|**Min.**|**Typ.(2)**|**Max.**|**Units**|**Conditions**|
|30|TRSTL|RESET<br>Pulse Width(low)|1|—|—|µs|VDD= 5.0V|
|32|THLD|Device active after reset high|—|0|—|µs|VDD= 5.0V|
|31|TPOR|POR at devicepower-up|—|20|—|µs|VDD= 5.0V|
|34|TIOZ|Output high-impedance from<br>RESET<br>Low|—|—|1|µs||
**Note 1:** This parameter is characterized, not 100% tested.
- **2:** Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.
DS20002121C-page 31
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **TABLE 2-2: GP AND INT PINS**
|**AC Characteristics**|**AC Characteristics**|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|
|---|---|---|---|---|---|---|---|
|**Param.**<br>**No.**|**Sym.**|**Characteristic**|**Min.**|**Typ.(2)**|**Max.**|**Units**|**Conditions**|
|50|tGPOV|Serial data to output valid|—|—|500|ns||
|51|tINTD|Interruptpin disable time|—|—|600|ns||
|52|tGPIV|GP input change to register valid|—|450|—|ns|**Note 1**|
|53|tGPINT|IOC event to INT active|—|—|600|ns||
|54|tGLITCH|Glitch filter on GPpins|—|—|50|ns|**Note 1**|
**Note 1:** This parameter is characterized, not 100% tested. **2:** Data in the Typical (“Typ.”) column is at 5V, +25C, unless otherwise stated.
## **FIGURE 2-3: GPIO AND INT TIMING**
**==> picture [417 x 262] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCL<br>SDA<br>In D1 D0<br>LSb of data byt e zero<br>during a write or read<br>command, depe n ding<br>on parameter 50<br>GPn<br>Output<br>Pin<br>51<br>INT<br>Pin<br>INT pin active INT pin<br>inactive<br>53<br>GPn<br>Input<br>Pin<br>52<br>Register<br>Loaded<br>**----- End of picture text -----**<br>
DS20002121C-page 32
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **TABLE 2-3: HARDWARE ADDRESS LATCH TIMING**
|**AC Characteristics**|**AC Characteristics**|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified for<br>1.8VVDD5.5V at -40CTA+125C.|
|---|---|---|---|---|---|---|---|
|**Param.**<br>**No.**|**Sym.**|**Characteristic**|**Min.**|**Typ.(2)**|**Max.**|**Units**|**Conditions**|
|40|tADEN|Time from VDDstable after<br>POR to ADC enable|—|0|—|µs|**Note 1**|
|41|tADDRLAT|Time from ADC enable to<br>address decode and latch|—|50|—|ns|**Note 1**|
|42|tADDIS|Time from raising edge of<br>serial clock to ADC disable|—|10|—|ns|**Note 1**|
|**Note 1:**<br>This parameter is characterized, not 100% tested.<br>**2:**<br>Data in the Typical (“Typ.”) column is at 5V, +25C, unless otherwise stated.||||||||
## **FIGURE 2-4: HARDWARE ADDRESS LATCH TIMING**
**==> picture [442 x 170] intentionally omitted <==**
**----- Start of picture text -----**<br>
40<br>VDD<br>41<br>adc_en<br>i2c_addr[2:0]<br>42<br>SCL<br>**----- End of picture text -----**<br>
DS20002121C-page 33
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
**==> picture [469 x 171] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIGURE 2-5: I [2] C™ BUS START/STOP BITS TIMING<br>SCL<br>91 93<br>90 92<br>SDA<br>Start Stop<br>Condition Condition<br>Note 1: Refer to Figure 2-1 for load conditions.<br>**----- End of picture text -----**<br>
## **FIGURE 2-6: I[2] C™ BUS DATA TIMING**
**==> picture [399 x 125] intentionally omitted <==**
**----- Start of picture text -----**<br>
10 3 100 102<br>10 1<br>SCL<br>90 106<br>91 107 92<br>SDA<br>In<br>109 109 110<br>SDA<br>Out<br>Note 1: Refer to Figure 2-1 for load conditions.<br>**----- End of picture text -----**<br>
DS20002121C-page 34
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **TABLE 2-4: I[2] C™ BUS DATA REQUIREMENTS (SLAVE MODE)**
|**I2C™ AC Characteristics**|**I2C™ AC Characteristics**|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|
|---|---|---|---|---|---|---|---|
|**Param.**<br>**No.**|<br>**Characteristic**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**|
|100|Clock High Time:|THIGH||||||
||100 kHz mode||4.0|—|—|µs|1.8V – 5.5V|
||400 kHz mode||0.6|—|—|µs|1.8V – 5.5V|
||3.4 MHz mode||0.06|—|—|µs|2.7V – 5.5V|
|101|Clock Low Time:|TLOW||||||
||100 kHz mode||4.7|—|—|µs|1.8V – 5.5V|
||400 kHz mode||1.3|—|—|µs|1.8V – 5.5V|
||3.4 MHz mode||0.16|—|—|µs|2.7V – 5.5V|
|102|SDA and SCL Rise Time:|TR<br>**(Note 1)**||||||
||100 kHz mode||—|—|1000|ns|1.8V – 5.5V|
||400 kHz mode||20 + 0.1 CB**(2)**|—|300|ns|1.8V – 5.5V|
||3.4 MHz mode||10|—|80|ns|2.7V – 5.5V|
|103|SDA and SCL Fall Time:|TF<br>**(Note 1)**||||||
||100 kHz mode||—|—|300|ns|1.8V – 5.5V|
||400 kHz mode||20 + 0.1 CB**(2)**|—|300|ns|1.8V – 5.5V|
||3.4 MHz mode||10|—|80|ns|2.7V – 5.5V|
|90|Start Condition SetupTime:|TSU:STA||||||
||100 kHz mode||4.7|—|—|µs|1.8V – 5.5V|
||400 kHz mode||0.6|—|—|µs|1.8V – 5.5V|
||3.4 MHz mode||0.16|—|—|µs|2.7V – 5.5V|
|91|Start Condition Hold Time:|THD:STA||||||
||100 kHz mode||4.0|—|—|µs|1.8V – 5.5V|
||400 kHz mode||0.6|—|—|µs|1.8V – 5.5V|
||3.4 MHz mode||0.16|—|—|µs|2.7V – 5.5V|
|106|Data Input Hold Time:|THD:DAT||||||
||100 kHz mode||0|—|3.45|µs|1.8V – 5.5V|
||400 kHz mode||0|—|0.9|µs|1.8V – 5.5V|
||3.4 MHz mode||0|—|0.07|µs|2.7V – 5.5V|
|107|Data Input SetupTime:|TSU:DAT||||||
||100 kHz mode||250|—|—|ns|1.8V – 5.5V|
||400 kHz mode||100|—|—|ns|1.8V – 5.5V|
||3.4 MHz mode||0.01|—|—|µs|2.7V – 5.5V|
|92|StopCondition SetupTime:|TSU:STO||||||
||100 kHz mode||4.0|—|—|µs|1.8V – 5.5V|
||400 kHz mode||0.6|—|—|µs|1.8V – 5.5V|
||3.4 MHz mode||0.16|—|—|µs|2.7V – 5.5V|
- **Note 1:** This parameter is characterized, not 100% tested.
- **2:** CB is specified from 10 to 400 (pF).
- **3:** This parameter is not applicable in high-speed mode (3.4 MHz).
DS20002121C-page 35
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **TABLE 2-4: I[2] C™ BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)**
|**I2C™ AC Characteristics**|**I2C™ AC Characteristics**|**I2C™ AC Characteristics**|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|**Electrical Characteristics:**Unless otherwise indicated, all limits are<br>specified for 1.8VVDD5.5V at -40CTA+125C,<br>RPU (SCL, SDA)= 1 k, CL (SCL, SDA)= 135pF.|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Param.**<br>**No.**|<br>**Characteristic**||**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|||**Conditions**|||||
|109|Output Valid From Clock:||TAA||||||||||||
||100 kHz mode|||—|—|3.45|µs|||1.8V – 5.5V|||||
||400 kHz mode|||—|—|0.9|µs|||1.8V – 5.5V|||||
||3.4 MHz mode|||—|—|0.18|µs|||2.7V – 5.5V|||||
|110|Bus Free Time:||TBUF<br>**(Note 3)**||||||||||||
||100 kHz mode|||4.7|—|—|µs|||1.8V – 5.5V|||||
||400 kHz mode|||1.3|—|—|µs|||1.8V – 5.5V|||||
||3.4 MHz mode|||N/A|—|N/A|µs|||2.7V – 5.5V|||||
||Bus Capacitive Loading:||CB<br>**(Note 2)**||||||||||||
||100 kHz and 400 kHz|||—|—|400|pF|||**Note 1**|||||
||3.4 MHz|||—|—|100|pF|||**Note 1**|||||
||Input Filter Spike<br>Suppression:(SDA and SCL)||TSP||||||||||||
||100 kHz and 400 kHz|||—|—|50|ns|||**Note 1**|||||
||3.4 MHz|||—|—|10|ns|||**Note 1**|||||
|**FIGURE 2-7:**<br>**SPI INPUT TIMING**<br>**Note 1:**<br>This parameter is characterized, not 100% tested.<br>**2:**<br>CBis specified from 10 to 400 (pF).<br>**3:**<br>This parameter is not applicable in high-speed mode (3.4 MHz).|||||||||||||||
|CS<br>SCK<br>SI<br>SO||1<br>5<br>4<br>7<br>6<br>MSB in<br>high impedance<br>Mode 1,1<br>Mode 0,0|||||||||3||11||
||||||||||||||||
||||||||||||10||||
||||||2<br>LSB in||||||||||
||||||||||||||||
||||||||||||||||
||||||||||||||||
||||||||||||||||
||||||||||||||||
DS20002121C-page 36
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **FIGURE 2-8: SPI OUTPUT TIMING**
**==> picture [444 x 148] intentionally omitted <==**
**----- Start of picture text -----**<br>
CS<br>2<br>8 9<br>SCK Mode 1,1<br>Mode 0,0<br>12<br>14<br>13<br>SO<br>MSB out LSB out<br>don’t care<br>SI<br>**----- End of picture text -----**<br>
DS20002121C-page 37
2009-2014 Microchip Technology Inc.
## **MCP23009/MCP23S09**
## **TABLE 2-5: SPI INTERFACE AC CHARACTERISTICS**
|**SPI Interface AC Characteristics**|**SPI Interface AC Characteristics**|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|**Electrical Characteristics:**Unless otherwise indicated, all limits are specified<br>for 1.8VVDD5.5V at -40CTA+125C.|
|---|---|---|---|---|---|---|---|
|**Param.**<br>**No.**|**Characteristic**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**|
||Clock Frequency|FCLK|—|—|10|MHz|1.8V – 5.5V|
|1|CS<br>SetupTime|TCSS|50|—|—|ns||
|2|CS<br>Hold Time|TCSH|50|—|—|ns|1.8V – 5.5V|
|3|CS<br>Disable Time|TCSD|50|—|—|ns|1.8V – 5.5V|
|4|Data SetupTime|TSU|10|—|—|ns|1.8V – 5.5V|
|5|Data Hold Time|THD|10|—|—|ns|1.8V – 5.5V|
|6|CLK Rise Time|TR|—|—|2|µs|**Note 1**|
|7|CLK Fall Time|TF|—|—|2|µs|**Note 1**|
|8|Clock High Time|THI|45|—|—|ns|1.8V – 5.5V|
|9|Clock Low Time|TLO|45|—|—|ns|1.8V – 5.5V|
|10|Clock DelayTime|TCLD|50|—|—|ns||
|11|Clock Enable Time|TCLE|50|—|—|ns||
|12|Output Valid from Clock<br>Low|TV|—|—|45|ns|1.8V – 5.5V|
|13|Output Hold Time|THO|0|—|—|ns||
|14|Output Disable Time|TDIS|—|—|100|ns||
**Note 1:** This parameter is characterized, not 100% tested.
**FIGURE 2-9: TYPICAL PERFORMANCE CURVE FOR SPI TV SPECIFICATION (PARAM #12)**
**==> picture [398 x 273] intentionally omitted <==**
**----- Start of picture text -----**<br>
T<br>V vs. VDD<br>40<br>35<br>30 T = +125°C<br>25<br>T = +85°C<br>20 T = -40 ° C<br>15<br>10<br>T = +25°C<br>5<br>0<br>1.5 2 2.5 3 3.5 4 4.5 5 5.5<br>V<br>DD (V)<br> (ns)<br>V<br>T<br>**----- End of picture text -----**<br>
DS20002121C-page 38
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **3.0 PACKAGING INFORMATION**
**==> picture [422 x 243] intentionally omitted <==**
**----- Start of picture text -----**<br>
3.1 Package Marking Information<br>16-Lead QFN (3x3x0.9 mm) Example<br>2S9<br>EYWW E432<br>256<br>- wn a<br>18-Lead PDIP (300 mil) Example<br>piIpiririrpiririritr4 piroririririrpirird<br>XXXXXXXXXXXXXXXXX MCP23S09<br>) XXXXXXXXXXXXXXXXX \ E/P ^^ - e3<br>1432256<br>o A YYWWNNN O o ® O<br>Citot aia O o<br>18-Lead SOIC (7.50 mm) Example<br>**----- End of picture text -----**<br>
18-Lead SOIC (7.50 mm) Example ~~1 fo~~ 1 ~~ff ff~~ XXXXXXXXXXXX **MCP23S09** E/SO ^^ e3 XXXXXXXXXXXX - 1432 XXXXXXXXXXXX _ 256 ~~ee Le |~~ FU UUUUUUU FU UUUUUUU 20-Lead SSOP (5.30 mm) Example ~~WET HAE~~ XXXXXXXXXXX XXXXXXXXXXX **MCP23009** E/SS ^^ e3 ~~A~~ YYWWNNN ~~L~~ 1432256 A JUUUUUUUUL WUUUUUUUUL **Legend:** XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC[®] designator for Matte Tin (Sn) ***** This package is Pb-free. The Pb-free JEDEC designator ( ) e3 can be found on the outer packaging for this package. **Note** : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
20-Lead SSOP (5.30 mm)
DS20002121C-page 39
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
**==> picture [235 x 184] intentionally omitted <==**
**==> picture [255 x 268] intentionally omitted <==**
DS20002121C-page 40
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS20002121C-page 41
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
**==> picture [123 x 61] intentionally omitted <==**
DS20002121C-page 42
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**==> picture [407 x 243] intentionally omitted <==**
**----- Start of picture text -----**<br>
N<br>NOTE 1 | p u ra ri ri rier ) 7<br>E1<br>G 2 at<br>a a t<br>1 2 3<br>SP a apap t D pt asad o e |e val<br>4 | E<br>A A2<br>L c<br>A1<br>b1<br>b e eB<br>**----- End of picture text -----**<br>
DS20002121C-page 43
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
**==> picture [286 x 443] intentionally omitted <==**
DS20002121C-page 44
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**==> picture [466 x 584] intentionally omitted <==**
**----- Start of picture text -----**<br>
Note: For the most current package drawings, please see the Microchip Packaging Specification located at<br>http://www.microchip.com/packaging<br>**----- End of picture text -----**<br>
DS20002121C-page 45
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
**==> picture [172 x 182] intentionally omitted <==**
DS20002121C-page 46
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**==> picture [385 x 262] intentionally omitted <==**
**----- Start of picture text -----**<br>
D<br>N<br>E<br>SMQQXN E1 |<br>SS NQN I | ~ <2 “it<br>NOTE 1<br>JUUUUUUU KY){Ws 3<br>EL aN<br>1 2<br>e<br>b<br>c<br>A A2<br>φ<br>A1<br>L1 L<br>**----- End of picture text -----**<br>
DS20002121C-page 47
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
**Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
**==> picture [158 x 218] intentionally omitted <==**
DS20002121C-page 48
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **APPENDIX A: REVISION HISTORY**
## **Revision C (August 2014)**
The following is the list of modifications:
1. Added ESD data in the Absolute Maximum Ratings[(†)] section.
2. Updated Figure 1-1.
3. Updated the DC Characteristics table.
4. Updated the Package Marking Information section.
5. Minor typographical changes.
## **Revision B (May 2009)**
The following is the list of modifications:
1. Added the 3x3 QFN package (MG package marking).
2. Updated Revision History.
## **Revision A (December 2008)**
- Original Release of this Document.
DS20002121C-page 49
2009-2014 Microchip Technology Inc.
**MCP23009/MCP23S09**
## **PRODUCT IDENTIFICATION SYSTEM**
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
|**Device:**<br>MCP23009:<br>8-Bit I/O Expander w/ I2C™ Interface<br>MCP23009T:<br>8-Bit I/O Expander w/ I2C Interface<br>(Tape and Reel)<br>MCP23S09:<br>8-Bit I/O Expander w/ SPI Interface<br>MCP23S09T:<br>8-Bit I/O Expander w/ SPI Interface<br>(Tape and Reel)<br>**Temperature**<br>**Range:**<br>E<br>= -40C to +125C (Extended)<br>**Package:**<br>MG<br>= Plastic Quad Flat, No Lead Package –<br>3x3x0.9 mm Body, 16-Lead<br>P<br>= Plastic Dual In-Line – 300 mil Body, 18-Lead<br>SO<br>= Plastic Small Outline – Wide, 7.50 mm Body,<br>18-Lead<br>SS<br>= Lead Plastic Shrink Small Outline –<br>5.30 mm Body, 20-Lead<br>**PART NO.**<br>**-**<br>**X**<br>**/XX**<br>**Package**<br>**Temperature**<br>**Range**<br>**Device**|**Examples:**<br>a)<br>MCP23009-E/MG:<br>Extended Temperature,<br>16LD QFN package<br>b)<br>MCP23009-E/P:<br>Extended Temperature,<br>18LD PDIP package<br>c)<br>MCP23009-E/SO:<br>Extended Temperature,<br>18LD SOIC package<br>d)<br>MCP23009T-E/SO: Tape and Reel,<br>Extended Temperature,<br>18LD SOIC package<br>e)<br>MCP23009-E/SS:<br>Extended Temperature,<br>20LD SSOP package<br>f)<br>MCP23009T-E/SS: Tape and Reel,<br>Extended Temperature,<br>20LD SSOP package<br>a)<br>MCP23S09-E/MG: Extended Temperature,<br>16LD QFN package<br>b)<br>MCP23S09T-E/MG: Tape and Reel,<br>Extended Temperature,<br>16LD QFN package<br>c)<br>MCP23S09-E/P:<br>Extended Temperature,<br>18LD PDIP package<br>d)<br>MCP23S09-E/SO:<br>Extended Temperature,<br>18LD SOIC package<br>e)<br>MCP23S09T-E/SO: Tape and Reel,<br>Extended Temperature,<br>18LD SOIC package|
|---|---|
DS20002121C-page 50
2009-2014 Microchip Technology Inc.
**Note the following details of the code protection feature on Microchip devices:**
- Microchip products meet the specification contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
- There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
- Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE **.** Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
## **Trademarks**
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC[32] logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-540-6
## **QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV** == == **ISO/TS 16949**
_Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC[®] MCUs and dsPIC[®] DSCs, KEELOQ[®] code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified._
DS20002121C-page 51
2009-2014 Microchip Technology Inc.
## **Worldwide Sales and Service**
## **AMERICAS**
**Corporate Office** 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com
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## **ASIA/PACIFIC**
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## **ASIA/PACIFIC**
**India - Bangalore** Tel: 91-80-3090-4444 Fax: 91-80-3090-4123
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**Japan - Osaka** Tel: 81-6-6152-7160 Fax: 81-6-6152-9310
**Japan - Tokyo** Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771
**Korea - Daegu** Tel: 82-53-744-4301 Fax: 82-53-744-4302
**Korea - Seoul** Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934
**Malaysia - Kuala Lumpur** Tel: 60-3-6201-9857 Fax: 60-3-6201-9859
**Malaysia - Penang** Tel: 60-4-227-8870 Fax: 60-4-227-4068
**Philippines - Manila** Tel: 63-2-634-9065 Fax: 63-2-634-9069
**Singapore** Tel: 65-6334-8870 Fax: 65-6334-8850
**Taiwan - Hsin Chu** Tel: 886-3-5778-366 Fax: 886-3-5770-955
**Taiwan - Kaohsiung** Tel: 886-7-213-7830
**Taiwan - Taipei** Tel: 886-2-2508-8600 Fax: 886-2-2508-0102
**Thailand - Bangkok** Tel: 66-2-694-1351 Fax: 66-2-694-1350
## **EUROPE**
**Austria - Wels** Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 **Denmark - Copenhagen** Tel: 45-4450-2828 Fax: 45-4485-2829
**France - Paris** Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
**Germany - Dusseldorf** Tel: 49-2129-3766400
**Germany - Munich** Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
**Germany - Pforzheim** Tel: 49-7231-424750
**Italy - Milan** Tel: 39-0331-742611 Fax: 39-0331-466781
**Italy - Venice** Tel: 39-049-7625286
**Netherlands - Drunen** Tel: 31-416-690399 Fax: 31-416-690340
**Poland - Warsaw** Tel: 48-22-3325737
**Spain - Madrid** Tel: 34-91-708-08-90 Fax: 34-91-708-08-91
**Sweden - Stockholm** Tel: 46-8-5090-4654
**UK - Wokingham** Tel: 44-118-921-5800 Fax: 44-118-921-5820
03/25/14
DS20002121C-page 52
2009-2014 Microchip Technology Inc.
Updated at February 9, 2023
Microchip Technology Inc. is a leading global provider of smart, connected, and secure embedded control solutions. Known for enabling engineers to design with confidence, the company delivers a comprehensive product portfolio that reduces total system costs and accelerates time to market across the industrial, automotive, communications, and computing sectors. Our extensive selection of Microchip components highlights the manufacturer's strength in both discrete semiconductors and advanced wireless connectivity. We carry a robust lineup of highly efficient single MOSFETs and Schottky diodes tailored for demanding power management and switching applications. Alongside these essential discretes, engineers can source a wide array of ready-to-use networking modules, prominently featuring Bluetooth and WLAN adapters that streamline the development of modern IoT and connected devices. Rounding out the offering is a diverse range of Microchip integrated circuits and specialized components. This includes versatile I/O expanders for simplified system integration, precision timing solutions such as MEMS oscillators and pulse generators, as well as AC/DC LED driver ICs and sub-2.4GHz RF transceivers. Backed by Microchip's renowned commitment to exceptional quality and reliable performance, these components provide scalable, dependable building blocks for complex electronic designs.
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
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When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
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We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
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